CN113689785A - Display device - Google Patents
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- CN113689785A CN113689785A CN202110510090.9A CN202110510090A CN113689785A CN 113689785 A CN113689785 A CN 113689785A CN 202110510090 A CN202110510090 A CN 202110510090A CN 113689785 A CN113689785 A CN 113689785A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
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Abstract
The invention discloses a display device which is provided with a peripheral area and a display area and comprises a plurality of data lines, a plurality of scanning lines, a plurality of transfer lines, a plurality of pixels and a plurality of shielding wires. The plurality of data lines extend from the peripheral area along a first direction into the display area. The plurality of scanning lines are positioned in the display area and extend along a second direction which is staggered with the first direction. The plurality of transfer lines extend into the display area from the peripheral area and are respectively electrically connected to the scanning lines. The pixels are respectively electrically connected to the scanning line and the data line, wherein the first data line and the at least two patch cords are positioned between two adjacent pixels. A first shielding wire of the shielding wires is positioned between the first data wire and the at least two patch cords, and a second shielding wire of the shielding wires is positioned between two adjacent patch cords of the at least two patch cords.
Description
Technical Field
The present invention relates to a display device, and more particularly, to a display device having stable data line potentials.
Background
In the display produced by the profile cutting method, the signal sources of the gate and the source are required to be placed on the same side for cutting. Therefore, vertical gate transfer lines are disposed between adjacent pixels in the display area of the display, and the gate transfer lines are generally parallel to the data lines. However, a fixed capacitor exists between the parallel and adjacent data line and the gate transfer line, and the capacitor causes capacitive coupling of signals, and affects the potential of the data line when the gate signal is turned on or off, so that the potential of the data line fluctuates and is unstable, thereby causing abnormal display brightness.
Disclosure of Invention
The invention provides a display device having stable data line potential.
One embodiment of the present invention provides a display device having a peripheral region and a display region, and including: a plurality of data lines extending from the peripheral region into the display region, wherein the data lines extend along a first direction; a plurality of scanning lines located in the display area and extending along a second direction crossing the first direction; a plurality of transfer lines extending from the peripheral area into the display area and electrically connected to the scan lines respectively; the pixel structure comprises a plurality of pixels, a plurality of first switching wires and a plurality of second switching wires, wherein the pixels are respectively electrically connected to a scanning line and a data line, and the first data line and the at least two switching wires are positioned between two adjacent pixels; and a plurality of shielding wires, wherein the first shielding wire is positioned between the first data wire and the at least two patch cords, and the second shielding wire is positioned between the adjacent two of the at least two patch cords.
In an embodiment of the invention, the shielding wires are electrically connected to each other.
In an embodiment of the invention, the second shielding conductive line has an opening.
In an embodiment of the invention, four patch cords and five shielding wires are disposed between two adjacent pixels in the pixel.
In an embodiment of the invention, the pixel includes a plurality of sub-pixels, each of the sub-pixels includes a switching element and a pixel electrode, the pixel electrode is electrically connected to the switching element, and the shielding wire and the pixel electrode belong to the same film layer.
In an embodiment of the invention, the display device further includes a common electrode, wherein the shielding wire is electrically connected to the common electrode.
In an embodiment of the invention, the display device further includes a dummy data line, wherein at least two patch cords are located between the first data line and the dummy data line.
In an embodiment of the invention, a third shielding conductive line of the shielding conductive lines is located between the dummy data line and the patch cord.
In an embodiment of the invention, the dummy data line and the first data line are connected through a conductive layer, and the conductive layer and the scan line belong to a same film layer.
In an embodiment of the invention, the data line, the patch cord and the dummy data line belong to the same film layer.
In an embodiment of the invention, the data line, the patch cord and the dummy data line belong to different film layers.
In an embodiment of the invention, the at least two patch cords belong to different layers.
One embodiment of the present invention provides a display device having a peripheral region and a display region, wherein the display region has a switching line region, the switching line region has a side region and a central region, and the side region is located between the peripheral region and the central region, wherein the display device includes: a plurality of data lines extending from the peripheral region into the display region, wherein the data lines extend along a first direction; a plurality of scanning lines located in the display area and extending along a second direction crossing the first direction; the plurality of transfer lines extend into the transfer line area from the peripheral area and are respectively electrically connected to the scanning lines; the pixel structure comprises a plurality of pixels, a plurality of first switching wires and a plurality of second switching wires, wherein the pixels are respectively electrically connected to a scanning line and a data line, and the first data line and the at least two switching wires are positioned between two adjacent pixels; a plurality of shielded conductors located in the central region; and a plurality of shielding patterns located in the central region; the first shielding conducting wire is positioned between the first data wire and the at least two patch cords, the second shielding conducting wire is positioned between the adjacent two of the at least two patch cords, each shielding pattern is positioned at the connection position of each patch cord and the corresponding scanning line, and each shielding pattern simultaneously overlaps the at least two patch cords and the corresponding scanning lines.
In an embodiment of the invention, each of the shielding patterns is connected to the first shielding conductive line and the second shielding conductive line.
In an embodiment of the invention, the display device further includes a dummy data line, wherein at least two patch cords are located between the first data line and the dummy data line.
In an embodiment of the invention, the first data line and the dummy data line are connected in the side area.
In an embodiment of the invention, the display area further has a non-patch line area, the non-patch line area is located between the patch line area and the peripheral area, and in the non-patch line area, the dummy data line and the second data line are located between two adjacent pixels.
In an embodiment of the invention, the second data line is electrically connected to the dummy data line.
In an embodiment of the invention, the display device further includes a plurality of common electrode lines, wherein at least two common electrode lines are located between the second data line and the dummy data line.
In an embodiment of the invention, the number of the at least two common electrode lines and the number of the at least two transfer lines are the same.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a schematic top view of a display device 10 according to an embodiment of the invention;
FIG. 2 is an enlarged view of region I of FIG. 1;
FIG. 3 is a schematic top view of a display device 20 according to an embodiment of the present invention;
FIG. 4A is a schematic top view of a display device 30 according to an embodiment of the invention;
FIG. 4B is an enlarged schematic view of region V of the display device 30 of FIG. 4A;
FIG. 4C is a schematic cross-sectional view taken along section line A-A' of FIG. 4B;
FIG. 5 is an enlarged view of the display device 30 of FIG. 4A in a region II shown in FIG. 1;
FIG. 6 is an enlarged view of the display device 30 of FIG. 4A in the area III shown in FIG. 1;
FIG. 7 is an enlarged view of the display device 30 of FIG. 4A in a region IV as shown in FIG. 1;
FIG. 8A is a schematic top view of a display device 40 according to an embodiment of the invention;
FIG. 8B is a schematic cross-sectional view taken along section line B-B' of FIG. 8A;
FIG. 8C is a schematic cross-sectional view taken along section line C-C' of FIG. 8A;
fig. 9 is a schematic cross-sectional view of a display device 50 according to an embodiment of the invention.
Description of the symbols
10. 20, 30, 40, 50: display device
A-A ', B-B ', C-C ': section line
AA: display area
BF: buffer layer
BP: insulating layer
CA1, CA 2: central zone
CH: semiconductor layer
CL, CL1, CL 2: common electrode
CM1, CM2, CM3, CM 4: common electrode wire
D1: a first direction
D2: second direction
DC: driving circuit
DDL: dummy data line
DE: drain electrode
DL, DL1, DL 2: data line
EA1, EA 2: side edge area
G1, G2, G3, G4, Gn: adapter cable
GE: grid electrode
GI: gate insulating layer
GL, GL 1: scanning line
I. II, III, IV, V, VI: region(s)
M0, M1, M2, M3, M4: conductive layer
ML1, ML2, ML 3: conducting wire
NA: peripheral zone
NTA: non-patch cord area
O2, O4: opening of the container
P1: conductive pattern
P2: conductive pattern
PE: pixel electrode
PV: passivation layer
PX, PX1, PX 2: pixel
S1, S2, S3, S4, S5, S6, S7, Sn: shielded conductor
S21, S22, S41, S42: sub-conductor
SB: substrate
And SE: source electrode
SM: shielding pattern
SM1, SM 2: shielding block
SP: sub-pixel
SW: switching element
TA: switching line region
V1, V2, V3, V4, V5, V6: through hole
Detailed Description
Fig. 1 is a schematic top view of a display device 10 according to an embodiment of the invention. Fig. 2 is an enlarged view of region I in fig. 1. The display device 10 has a peripheral area NA and a display area AA. The display device 10 includes a plurality of data lines DL, a plurality of scan lines GL, a plurality of transfer lines Gn, a plurality of pixels PX, and a plurality of shield wires Sn. The plurality of data lines DL extend from the peripheral area NA into the display area AA, wherein the data lines DL extend along a first direction D1. The plurality of scan lines GL are located in the display area AA and extend along a second direction D2, wherein the second direction D2 is staggered with respect to the first direction D1. The plurality of transfer lines Gn extend from the peripheral area NA into the display area AA, and are electrically connected to the scan lines GL, respectively. The plurality of pixels PX are electrically connected to the scan line GL and the data line DL, respectively, wherein the data line DL1 and the at least two patch lines Gn are located between two adjacent pixels PX in the plurality of pixels PX. The shielding conductors S1 of the shielding conductors Sn are located between the data line DL1 and the patch lines Gn, and the shielding conductors S2 are located between two adjacent patch lines Gn.
In the present embodiment, the patch cord Gn is separated from the data line DL1 by the shielding conductor S1, so as to reduce the capacitive coupling between the patch cord Gn and the data line DL1, thereby avoiding the variation of the potential of the data line DL1 and enabling the data line DL1 to have a stable potential. In addition, the shielding wires S2 between adjacent patch cords Gn can make the loads of the patch cords Gn relatively similar, so as to avoid uneven brightness of the display device 10.
Hereinafter, embodiments of each element and film layer of the display device 10 will be described with reference to the drawings, but the present invention is not limited thereto.
Referring to fig. 1, in the present embodiment, the display device 10 is circular, but the invention is not limited thereto. In some embodiments, the display device 10 may have a rectangular, oval, polygonal, or irregular shape, and the shape of the display device 10 may be selected as desired.
The display device 10 may have a peripheral area NA and a display area AA, wherein the peripheral area NA surrounds the display area AA. In this embodiment, the display device 10 further includes a driving circuit DC located in the peripheral area NA. In the present embodiment, the display device 10 is driven by one side, and the driving circuit DC is located on the upper side of the display area AA, but the invention is not limited thereto. In some embodiments, the display device 10 may be dual-edge driven, and the driving circuit DC may be located at the upper and lower sides or the left and right sides of the display area AA.
In this embodiment, the display area AA may have a patch area TA and a non-patch area NTA, where the patch area TA is an area where the patch cord Gn is disposed, and the patch cord Gn is not disposed in the non-patch area NTA. In the embodiment, the patch cord area TA is located in the central area of the display area AA, and the non-patch cord areas NTA are located on two sides of the patch cord area TA, but the invention is not limited thereto, and the configurations of the patch cord area TA and the non-patch cord areas NTA may be changed as needed. In the present embodiment, the switching region TA may have a side region EA1 and a central region CA1, wherein the side region EA1 is located between the peripheral region NA and the central region CA 1. The non-patch panel NTA may also have a side area EA2 and a central area CA2, and the side area EA2 is located between the peripheral area NA and the central area CA 2.
Referring to fig. 1 and fig. 2, the display device 10 includes a plurality of data lines DL, a plurality of scan lines GL, a plurality of transfer lines Gn, a plurality of pixels PX and a plurality of shielding wires Sn on a substrate SB. The data line DL is electrically connected to the driving circuit DC. For example, the data line DL is electrically connected to a source driving element (not shown) in the driving circuit DC. The data lines DL extend from the peripheral area NA into the display area AA, the data lines DL in the display area AA extend along the first direction D1, and the data lines DL in the peripheral area NA may not be parallel to each other.
The scan line GL is located in the display area AA and extends along a second direction D2 that is staggered from the first direction D1. The transfer lines Gn extend from the peripheral area NA into the transfer line area TA of the display area AA, and one ends of the transfer lines Gn are electrically connected to the scan lines GL, respectively, and the other ends of the transfer lines Gn are electrically connected to the driving circuit DC, for example, the transfer lines Gn may be electrically connected to gate driving elements (not shown) in the driving circuit DC. In this way, the transfer lines Gn can respectively transmit the gate driving signals from the driving circuits DC to the corresponding scanning lines GL.
Referring to fig. 2, in the present embodiment, the display device 10 includes a plurality of sub-pixels SP, and each sub-pixel SP is electrically connected to a corresponding scan line GL and a data line DL. For example, each sub-pixel SP includes a switching element SW and a pixel electrode PE electrically connected to the switching element SW, wherein the switching element SW is electrically connected to a corresponding one of the scan lines and a corresponding one of the data lines. In the present embodiment, the sub-pixel SP includes a red sub-pixel, a green sub-pixel, and a blue sub-pixel. For example, the sub-pixel SP overlapping the red filter element (not shown) is a red sub-pixel, the sub-pixel SP overlapping the green filter element (not shown) is a green sub-pixel, and the sub-pixel SP overlapping the blue filter element (not shown) is a blue sub-pixel. In the present embodiment, the sub-pixels SP are arrayed into a plurality of pixels PX. For example, each pixel PX includes one red sub-pixel, one green sub-pixel, and one blue sub-pixel. In some embodiments, each pixel PX may further include sub-pixels of other colors. In the present embodiment, each pixel PX includes three sub-pixels SP, and each pixel PX is electrically connected to one scan line and three data lines.
In the patch cord area TA, one data line DL and at least two patch cords Gn may be disposed between two adjacent pixels PX. For example, in the present embodiment, a data line DL1 and four patch lines G1-G4 are disposed between two adjacent pixels PX1 and PX 2. In some embodiments, one data line DL1 and three patch lines Gn may be disposed between adjacent pixels PX1, PX 2. In some embodiments, one data line DL and five patch lines Gn may be disposed between adjacent pixels PX1, PX 2.
In the present embodiment, the data line DL1 is located between the pixel PX1 and the patch cord G1. The display device 10 may further include a dummy data line DDL, and the transfer lines G1 to G4 are located between the data line DL1 and the dummy data line DDL, which is located between the transfer line G4 and the pixel PX 2. In the embodiment, the data line DL1, the transfer lines G1-G4 and the dummy data line DDL may belong to the same film layer, but the invention is not limited thereto. By providing the dummy data line DDL, the capacitive coupling generated between the data line DL1 and the pixel PX1 may be cancelled by the capacitive coupling between the dummy data line DDL and the pixel PX 2.
In the central area CA1 of the patch panel TA, the shielding wires Sn of the display device 10 may be disposed between the data line DL1, the patch lines G1 to G4, and the dummy data line DDL, respectively. For example, in the present embodiment, the display device 10 includes three shielding wires S1 to S3, wherein the shielding wire S1 is located between the data line DL1 and the patch cord G1; the shielded conductor S2 is located between the patch cord G2 and the patch cord G3; and the shielding conductive line S3 is located between the patch cord G4 and the dummy data line DDL, but the invention is not limited thereto. In this way, the shielding wire S1 can separate the data line DL1 from the patch cord G1 to reduce the capacitive coupling between the data line DL1 and the patch cord G1, and the shielding wire S2 and the shielding wire S3 can make the loads of the patch cords G2 to G4 close to the patch cord G1, thereby avoiding uneven brightness.
Fig. 3 is a schematic top view of a display device 20 according to an embodiment of the invention. The display device 20 shown in fig. 3 is different from the display device 10 shown in fig. 1 to 2 in that: the display device 20 includes five shielding wires S1-S5, wherein the shielding wire S1 is located between the data line DL1 and the patch cord G1; the shielded conductor S2 is located between the patch cord G1 and the patch cord G2; the shielded conductor S3 is located between the patch cord G2 and the patch cord G3; the shielded conductor S4 is located between the patch cord G3 and the patch cord G4; and the shield conductive line S5 is located between the transfer line G4 and the dummy data line DDL. The shielding wires Sn are arranged between any two of the data lines DL1, the transfer lines G1-G4 and the dummy data lines DDL, so that the loads of the transfer lines G1-G4 can be fully homogenized, and the condition that the loads are not uniform due to slight contraposition deviation in the manufacturing process is avoided to be more serious.
Fig. 4A is a schematic top view of a display device 30 according to an embodiment of the invention. Fig. 4B is an enlarged schematic view of a region V of the display device 30 of fig. 4A. FIG. 4C is a schematic cross-sectional view taken along section line A-A' of FIG. 4B. The display device 30 as shown in fig. 4A to 4C is different from the display device 20 of fig. 3 in that: the shielding wire S2 has an opening O2, the shielding wire S4 has an opening O4, wherein the shielding wire S2 includes a sub-wire S21 and a sub-wire S22, and the opening O2 is located between the sub-wire S21 and the sub-wire S22; while the shielding conductor S4 includes a sub-conductor S41 and a sub-conductor S42, and the opening O4 is located between the sub-conductor S41 and the sub-conductor S42. In the present embodiment, the openings O2 and O4 can reduce the capacitance between the shielding wires S2 and S4 and the nearby conductive layer, and prevent short circuit between the shielding wires S2 and S4 and the nearby conductive layer.
Referring to fig. 4B and fig. 4C, in the present embodiment, the switching element SW includes a gate GE, a semiconductor layer CH, a source SE and a drain DE. The gate electrode GE overlaps the semiconductor layer CH, and a region where the semiconductor layer CH overlaps the gate electrode GE may be regarded as a channel region of the switching element SW. The source SE and the drain DE of the switching element SW are separated from each other, and the source SE and the drain DE contact the semiconductor layer CH, respectively. The pixel electrode PE is electrically connected to the drain electrode DE. The switching element SW can be turned on or off by a signal transmitted by the scan line GL, and the switching element SW can transmit a signal transmitted by the data line DL to the pixel electrode PE when turned on.
The source SE and the drain DE of the switching element SW may belong to the same film layer, and the material of the source SE, the drain DE and the gate GE of the switching element SW may include a metal with good conductivity, such as aluminum, molybdenum, titanium, etc., but the invention is not limited thereto. In order to avoid an unnecessary short circuit between the respective members, a gate insulating layer GI is disposed between the gate electrode GE and the semiconductor layer CH, and a passivation layer PV is disposed between the film layer forming the source electrode SE and the drain electrode DE and the pixel electrode PE. Although the gate electrode GE in the present embodiment is located below the semiconductor layer CH, the switching element SW is a bottom-gate transistor. However, in other embodiments, the gate electrode GE may be located above the semiconductor layer CH, so that the switching element SW is a top-gate transistor.
In the embodiment, the shielding wires S1 to S5 and the pixel electrode PE belong to the same film layer, and the shielding wires S1 to S5 are made of transparent conductive materials. In some embodiments, the shielding wires S1-S5 may use an alloy, a nitride of a metal material, an oxide of a metal material, an oxynitride of a metal material, or other suitable materials, or a stack of at least two of the above conductive materials, such as indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium gallium zinc oxide, or other suitable oxides, but the invention is not limited thereto.
The display device 30 further includes a common electrode CL, and the shielding conductive lines S1 to S5 are electrically connected to the common electrode CL, respectively, so that the shielding conductive lines S1 to S5 have the same potential as the common electrode CL. For example, in the present embodiment, the common electrode CL includes a common electrode CL1 and a common electrode CL2, and the common electrode CL1 and the common electrode CL2 are respectively located at two sides of the scan line GL. The shield wires S1 to S5 may be electrically connected to each other through a wire ML1, and the wire ML1 may be connected to the common electrode CL1 through a via V1. In addition, the conductive line ML1 can also be connected with the conductive line ML2 through a through hole V2, and the conductive line ML2 can be connected with the common electrode CL2 through a through hole V3, a conductive line ML3 and a through hole V4, so that the common electrode CL1 and the common electrode CL2 can be connected to form a mesh electrode. In this way, even after the display device 30 is profile cut, the common electrode CL1 and the common electrode CL2 can still be electrically connected.
FIG. 5 is an enlarged view of the display device 30 of FIG. 4A in a region II shown in FIG. 1. In the side area EA1 of the patch cord area TA of the display device 30, the dummy data line DDL and the data line DL1 are connected through the conductive layer M1, so that the dummy data line DDL and the data line DL1 have the same potential. In some embodiments, the conductive layer M1 may be the same as the scan line GL, but the invention is not limited thereto. In some embodiments, the data line DL1 may be connected to the conductive layer M1 through the conductive pattern P1, and the dummy data line DDL may be connected to the conductive layer M1 through the conductive pattern P2. The conductive patterns P1 and P2 may belong to the same layer as the shielding wires S1 to S5 of the display device 30 of fig. 4A, and the shielding wires S1 to S5 do not extend to the side area EA1, so as to avoid short circuit with the conductive patterns P1 and P2.
FIG. 6 is an enlarged view of the display device 30 of FIG. 4A in the area III shown in FIG. 1. In the present embodiment, in the central area CA1 of the patch cord area TA, the patch cords G1 to G4 may be connected to four scan lines GL, wherein each of the patch cords G1 to G4 is connected to a corresponding one of the scan lines GL. The four scan lines GL connected to the transfer lines G1-G4 may be sequentially arranged along the first direction D1, but the invention is not limited thereto. In addition, the shield pattern SM may be provided at a portion where the patch lines G1 to G4 are connected to the scanning line GL.
For example, in the present embodiment, the shielding pattern SM is located between the data line DL1 and the dummy data line DDL, and the shielding pattern SM may include a shielding block SM1 and a shielding block SM 2.
In some embodiments, the shielding block SM1 connects the shielding wires S1-S5, and the shielding block SM1 overlaps the common electrode CL1, the common electrode CL2, the transfer lines G1-G4, and the scan line GL1 at the same time. The shielding blocks SM1 are used to cover the patch cables G1-G4, so that the electric field of the patch cables G1-G4 can be prevented from affecting the adjacent pixel electrodes PE. In some embodiments, the patch cord G1 may be connected to the shielding block SM2 through a via V5, and the shielding block SM2 may be connected to the scan line GL1 through a via V6. Since the through hole V5 and the through hole V6 can be formed by the conventional manufacturing process, the manufacturing process step and the photo mask for forming the through hole in the overlapping region VI of the transfer line G1 and the scan line GL1 can be eliminated.
FIG. 7 is an enlarged view of the display device 30 of FIG. 4A in a region IV as shown in FIG. 1. In the embodiment, the non-patch cord area NTA is located between the patch cord area TA and the peripheral area NA. In the non-transfer area NTA, a data line DL2 and a dummy data line DDL may be disposed between adjacent pixels, and the data line DL2 and the dummy data line DDL are electrically connected in the side area EA 2.
Since the non-patch cord area NTA is not provided with the patch cord Gn, in the non-patch cord area NTA, a plurality of common electrode wires may be provided between the data line DL2 and the dummy data line DDL, and the number of the common electrode wires may be the same as the number of patch cords between adjacent pixels in the patch cord area TA, so that the capacitive load of the non-patch cord area NTA is close to that of the patch cord area TA. For example, in the present embodiment, four common electrode lines CM1, CM2, CM3, and CM4 are disposed between the data line DL2 and the dummy data line DDL.
In addition, a shielding conductive line S6 may be disposed between the data line DL2 and the common electrode line CM1, and a shielding conductive line S7 may be disposed between the dummy data line DDL and the common electrode line CM4, so as to reduce capacitive coupling between the common electrode lines CM1 and CM4 and the data line DL2 and the dummy data line DDL, thereby preventing the potentials of the data line DL2 and the dummy data line DDL from being changed, and enabling the data line DL2 to have a stable potential.
Fig. 8A is a schematic top view of a display device 40 according to an embodiment of the invention. FIG. 8B is a schematic cross-sectional view taken along section line B-B' of FIG. 8A. FIG. 8C is a schematic cross-sectional view taken along section line C-C' of FIG. 8A. The display device 40 shown in fig. 8A to 8C is different from the display device 20 shown in fig. 3 in that: in the central area CA1 of the patch cord area TA, the data line DL1, the patch cords G1 to G4, and the dummy data line DDL belong to different film layers.
For example, in the present embodiment, the patch cord G1, the patch cord G3 and the dummy data line DDL belong to the conductive layer M0, and the data line DL1, the patch cord G2 and the patch cord G4 belong to the conductive layer M2. Therefore, the patch cords G1-G4 also belong to different layers. The conductive layer M0 is located on the substrate SB, the buffer layer BF and the gate insulating layer GI are disposed between the conductive layer M0 and the conductive layer M2, and the passivation layer PV is located on the conductive layer M2. Any adjacent wires in the data line DL1, the transfer lines G1-G4 and the dummy data line DDL belong to different film layers, so that the possibility that the adjacent wires are short-circuited due to manufacturing process errors can be eliminated, and the distance between the adjacent wires is minimized.
Referring to fig. 8C, in the side area EA1 of the patch cord area TA of the display device 40, the dummy data line DDL is connected to the data line DL1 through the conductive layer M4, so that the dummy data line DDL and the data line DL1 have the same potential.
Fig. 9 is a schematic cross-sectional view of a display device 50 according to an embodiment of the invention. The display device 50 shown in fig. 9 is different from the display device 40 shown in fig. 8B in that: the patch cord G1, the patch cord G3, and the dummy data line DDL belong to the conductive layer M3, and the data line DL1, the patch cord G2, and the patch cord G4 belong to the conductive layer M2.
In the present embodiment, the gate insulating layer GI is located on the substrate SB, the conductive layer M2 is disposed on the gate insulating layer GI, the passivation layer PV is located between the conductive layer M2 and the conductive layer M3, and the insulating layer BP is located on the conductive layer M3. Any adjacent wires in the data line DL1, the transfer lines G1-G4 and the dummy data line DDL belong to different film layers, so that the possibility that the adjacent wires are short-circuited due to manufacturing process errors can be eliminated, and the distance between the adjacent wires is minimized.
In summary, the shielding wires are used to separate the patch cord from the data line, so that the capacitive coupling between the patch cord and the data line can be reduced, and the potential of the data line can be prevented from changing, so that the potential of the data line can be kept stable. In addition, the shielding wires are arranged between the adjacent transfer wires, so that the loads of the transfer wires are close, and the uneven brightness of the display device can be avoided.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, and that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.
Claims (20)
1. A display device having a peripheral region and a display region, the display device further comprising:
a plurality of data lines extending from the peripheral region into the display region, wherein the data lines extend along a first direction;
a plurality of scanning lines located in the display area and extending along a second direction crossing the first direction;
a plurality of transfer lines extending from the peripheral area into the display area and electrically connected to the scan lines respectively;
a plurality of pixels electrically connected to the scan lines and the data lines, respectively, wherein a first data line and at least two patch cords are disposed between two adjacent pixels; and
and the second shielding wire is positioned between the adjacent two of the at least two patch cords.
2. The display device of claim 1, wherein the shielding wires are electrically connected to each other.
3. The display device of claim 1, wherein the second shielding conductive line has an opening.
4. The display device as claimed in claim 1, wherein four patch cords and five shielding wires are disposed between two adjacent pixels.
5. The display device of claim 1, wherein each of the pixels comprises a plurality of sub-pixels, each of the sub-pixels comprises a switching element and a pixel electrode, the pixel electrode is electrically connected to the switching element, and the shielding wires and the pixel electrode belong to the same film layer.
6. The display device of claim 1, further comprising a common electrode, wherein the shielding wires are electrically connected to the common electrode.
7. The display device of claim 1, further comprising a dummy data line, wherein the at least two patch cords are located between the first data line and the dummy data line.
8. The display device according to claim 7, wherein a third shielding conductive line of the shielding conductive lines is located between the dummy data line and the at least two patch cords.
9. The display device according to claim 7, wherein the dummy data line is connected to the first data line via a conductive layer, and the conductive layer and the scan lines are in a same layer.
10. The display device of claim 7, wherein the data lines, the plurality of patch cords, and the dummy data line belong to a same layer.
11. The display device of claim 7, wherein the data lines, the plurality of patch cords, and the dummy data line belong to different layers.
12. The display device of claim 11, wherein the at least two patch cords belong to different layers.
13. A display device is provided with a peripheral area and a display area, and is characterized in that the display area is provided with a switching line area, the switching line area is provided with a side area and a central area, and the side area is positioned between the peripheral area and the central area, wherein the display device comprises:
a plurality of data lines extending from the peripheral region into the display region, wherein the data lines extend along a first direction;
a plurality of scanning lines located in the display area and extending along a second direction crossing the first direction;
a plurality of transfer lines extending from the peripheral area into the transfer line area and electrically connected to the scan lines respectively;
a plurality of pixels electrically connected to the scan lines and the data lines, respectively, wherein a first data line and at least two patch cords are disposed between two adjacent pixels;
a plurality of shield conductors located in the central region; and
a plurality of shielding patterns located in the central region;
the first shielding conducting wire is positioned between the first data wire and the at least two transfer wires, the second shielding conducting wire is positioned between the adjacent two of the at least two transfer wires, each shielding pattern is positioned at the connection position of each transfer wire and the corresponding scanning wire, and each shielding pattern simultaneously overlaps the at least two transfer wires and the corresponding scanning wires.
14. The display device according to claim 13, wherein each of the shielding patterns connects the first shielding conductive line and the second shielding conductive line.
15. The display device of claim 13, further comprising a dummy data line, wherein the at least two patch cords are positioned between the first data line and the dummy data line.
16. The display device of claim 15, wherein the first data line and the dummy data line are connected at the side region.
17. The display device according to claim 15, wherein the display region further has a non-transfer line region between the transfer line region and the peripheral region, and the dummy data line and the second data line are between adjacent ones of the pixels in the non-transfer line region.
18. The display device of claim 17, wherein the second data line is electrically connected to the dummy data line.
19. The display device according to claim 17, further comprising a plurality of common electrode lines, wherein at least two common electrode lines are located between the second data line and the dummy data line.
20. The display device according to claim 19, wherein the at least two common electrode lines and the at least two patch cords are the same in number.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
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| US202063027026P | 2020-05-19 | 2020-05-19 | |
| US63/027,026 | 2020-05-19 | ||
| US202063060259P | 2020-08-03 | 2020-08-03 | |
| US63/060,259 | 2020-08-03 | ||
| TW110103330A TWI756040B (en) | 2020-05-19 | 2021-01-28 | Display device |
| TW110103330 | 2021-01-28 |
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| CN113689785A true CN113689785A (en) | 2021-11-23 |
| CN113689785B CN113689785B (en) | 2023-04-25 |
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| CN202110510090.9A Active CN113689785B (en) | 2020-05-19 | 2021-05-11 | Display device |
| CN202121002721.8U Withdrawn - After Issue CN215495771U (en) | 2020-05-19 | 2021-05-11 | Display device |
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| CN113689785B (en) | 2023-04-25 |
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