CN113678249A

CN113678249A - Electrostatic discharge protection circuit and chip with same

Info

Publication number: CN113678249A
Application number: CN202080018787.8A
Authority: CN
Inventors: 张均军
Original assignee: Shenzhen Goodix Technology Co Ltd
Current assignee: Shenzhen Goodix Technology Co Ltd
Priority date: 2020-06-12
Filing date: 2020-06-12
Publication date: 2021-11-19
Also published as: WO2021248501A1

Abstract

An electrostatic discharge protection circuit and a chip with the same are provided, wherein the electrostatic discharge protection circuit comprises an RC module (101), an alarm module (102) and a discharge module (103); the output voltage of the RC module (101) increases when the input voltage increases; the alarm module (102) receives an input voltage of the RC module (101) and an output voltage of the RC module (101), the alarm voltage of the alarm module (102) is increased when the input voltage of the RC module (101) is increased, and when the alarm voltage is greater than or equal to the output voltage of the RC module (101), an electrostatic alarm signal is output; the leakage module (103) receives an input voltage of the RC module (101) and an output voltage of the RC module (101), when the input voltage of the RC module (101) is increased, the leakage voltage of the leakage module (103) is increased, when the leakage voltage is larger than or equal to the output voltage of the RC module (101), electrostatic leakage is carried out, and the alarm voltage is larger than the leakage voltage. The protection circuit can carry out electrostatic discharge according to advance knowledge, improves the working stability of the chip and improves the user experience.

Description

Electrostatic discharge protection circuit and chip with same

Technical Field

The embodiment of the application relates to the technical field of electronics, in particular to an electrostatic discharge protection circuit and a chip with the same.

Background

During the production, testing, transportation, use, etc. of chips, various degrees of electrostatic Discharge (ESD) events occur. When the electrostatic discharge event occurs, a large amount of charges can be instantaneously injected into the chip from the outside to the inside. If the chip encounters an electrostatic discharge event during operation or an impact of external electrostatic coupling, the system of the chip may enter an abnormal state (such as an abnormal reset, a runaway, or a deadlock), which may affect the normal operation of the chip. Whether a chip can withstand an electrostatic discharge event is an important detection criterion for chip Electromagnetic Compatibility (EMC) testing.

Through encapsulating the chip, partial static electricity can be prevented from being directly released to a chip internal circuit, but pins (such as a power supply pin, a clock pin, a communication pin and the like) of the chip exposed outside still can be exposed in the static environment, in order to avoid static electricity from being released to the chip internal circuit through the partial pins, a static electricity leakage protection circuit can be arranged in the chip, and static electricity leakage is carried out through the static electricity leakage protection circuit, so that the chip internal circuit is prevented from being damaged. For example, an electrostatic discharge protection circuit may be disposed at an input/output PAD (IO PAD) of the chip, and when performing electrostatic discharge, the electrostatic discharge protection circuit may guide static electricity to be discharged in an input/output power supply ring capable of passing a large current.

Although the chip is provided with the electrostatic discharge protection circuit, the damage to the internal circuit of the chip when an electrostatic discharge event occurs can be avoided, the chip cannot be controlled to take any software or hardware precautionary measures for electrostatic discharge of the electrostatic discharge protection circuit because whether the electrostatic discharge protection circuit is about to perform electrostatic discharge cannot be known in advance. If such a countermeasure is lacked, on one hand, electrostatic discharge occurring in a complex electromagnetic environment may cause devices in the chip to be broken down, resulting in abnormal chip current, or causing the chip to be damaged completely, etc., causing unrecoverable hardware damage to the chip, on the other hand, during the electrostatic discharge of the electrostatic discharge protection circuit, the voltage of each node on the discharge path may change instantaneously, and thus a series of operation errors (e.g., abnormal reset, program deadlock, etc.) may occur to the chip, and although these operation errors are non-physical damages recoverable through external intervention such as power-off or reset, etc., the chip may still cause a larger error to occur at the system level, thereby reducing the stability of the chip operation and damaging the user experience.

Disclosure of Invention

In view of the above, an embodiment of the present invention provides an esd protection circuit and a chip having the esd protection circuit, so as to overcome some or all of the problems in the prior art.

The embodiment of the application provides an electrostatic discharge protection circuit, which comprises an RC module, an alarm module and a discharge module;

when the input voltage of the RC module is increased, the output voltage of the RC module is increased;

the alarm module receives the input voltage of the RC module and the output voltage of the RC module, the alarm voltage of the alarm module is increased when the input voltage of the RC module is increased, and when the alarm voltage is greater than or equal to the output voltage of the RC module, the static alarm signal is output;

the leakage module receives the input voltage of the RC module and the output voltage of the RC module, the leakage voltage of the leakage module is increased when the input voltage of the RC module is increased, static leakage is carried out when the leakage voltage is larger than or equal to the output voltage of the RC module, and the alarm voltage is larger than the leakage voltage.

The embodiment of the application provides a chip with an electrostatic discharge protection circuit, and the chip with the electrostatic discharge protection circuit comprises the electrostatic discharge protection circuit provided by the embodiment of the application.

In the electrostatic discharge protection circuit that this application embodiment provided, when taking place the electrostatic discharge incident, because receive static high voltage impact in the twinkling of an eye, the input voltage of RC module can rise sharply, the output voltage of RC module this moment, the warning voltage of warning module and the bleeder voltage of bleeder module all increase, wherein because warning voltage is greater than bleeder voltage, consequently, the moment that warning voltage is greater than the output voltage of RC module is earlier than the moment that bleeder voltage is greater than the output voltage of RC module, ensure to report an emergency and ask for help or increased vigilance the module earlier output static warning signal, with the warning will carry out electrostatic discharge, later the bleeder module just carries out electrostatic discharge. Therefore, the electrostatic discharge protection circuit provided by the embodiment of the application can output the electrostatic warning signal to warn that the electrostatic discharge event is about to occur before electrostatic discharge, so that the chip can take software or hardware precautionary measures or post-remedial measures aiming at the electrostatic discharge event, and the probability of unrecoverable hardware damage or operation error of the chip during electrostatic discharge is reduced, thereby improving the working stability of the chip and improving the user experience.

Drawings

Some specific embodiments of the present application will be described in detail hereinafter by way of illustration and not limitation with reference to the accompanying drawings. The same reference numbers in the drawings identify the same or similar elements or components. Those skilled in the art will appreciate that the drawings are not necessarily drawn to scale. In the drawings:

fig. 1 is a schematic circuit structure diagram of an electrostatic discharge protection circuit according to an embodiment of the present disclosure;

fig. 2 is a schematic circuit structure diagram of an electrostatic discharge protection circuit according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of voltage variation with time according to an embodiment of the present disclosure;

fig. 4 is a schematic circuit structure diagram of an electrostatic discharge protection circuit according to an embodiment of the present disclosure;

fig. 5 is a schematic circuit structure diagram of an electrostatic discharge protection circuit according to an embodiment of the present disclosure;

fig. 6 is a schematic circuit structure diagram of an electrostatic discharge protection circuit according to an embodiment of the present disclosure;

fig. 7 is a schematic circuit structure diagram of an electrostatic discharge protection circuit according to an embodiment of the present disclosure;

fig. 8 is a schematic circuit structure diagram of a pulse extension alarm module according to an embodiment of the present application;

fig. 9 is a schematic circuit structure diagram of a pulse extension alarm module according to an embodiment of the present application;

fig. 10 is a schematic circuit structure diagram of an electrostatic discharge protection circuit according to an embodiment of the present application.

Detailed Description

It is not necessary for any particular embodiment of the invention to achieve all of the above advantages at the same time.

In order to make those skilled in the art better understand the technical solutions in the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, but not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application shall fall within the scope of the protection of the embodiments in the present application.

The event of uncontrolled transfer of static charge from one object to another is generally referred to as a static discharge event. When an electrostatic discharge event occurs, a large amount of charges can be instantly filled into the chip from outside to inside, and if the chip encounters the electrostatic discharge event during operation or the impact of external electrostatic coupling, a system of the chip enters an abnormal state, so that the normal operation of the chip is influenced.

In order to avoid static electricity from being released to the internal circuit of the chip through the pin, a static electricity leakage protection circuit (such as an RC clamp static electricity leakage protection circuit, or a transient suppression diode static electricity leakage protection circuit) may be disposed in the chip, and static electricity leakage is performed through the static electricity leakage protection circuit, so as to avoid damage to the internal circuit of the chip. The electrostatic discharge protection circuit may be a device in the protection chip in different voltage domains, and may be configured to respectively set a corresponding electrostatic discharge protection circuit for an input/output interface of each voltage domain.

Specifically, as shown in fig. 1, the electrostatic discharge protection circuit includes: the ESD protection circuit comprises a resistor R0, a capacitor C0, an inverter P0 and an N-type transistor N0, wherein one end of the resistor R0 is connected with the electrostatic discharge end V0, the other end of the resistor R0 is connected with one end of the capacitor C0, the other end of the capacitor C0 is grounded, the connection position of the resistor R0 and the capacitor C0 is connected with a first input end of the inverter P0, a second input end of the inverter P0 is connected with the electrostatic discharge end V0, the inverter P0 is provided with a ground end, a drain of the N-type transistor N0 is connected with the electrostatic discharge end V0, a gate of the N-type transistor N0 is connected with an output end of the inverter P0, and a source of the N-type transistor N0 is grounded. The electrostatic discharge end V0 may be connected to a pin or a component of the chip where an electrostatic discharge event is likely to occur, for example, the electrostatic discharge end V0 may be connected to an input interface or an output interface of the chip, and a ground end of the electrostatic discharge protection circuit may be connected to a ground end of a power ring of the chip through which a large current is allowed to pass; for another example, the electrostatic discharge terminal V0 may be connected to a power supply pin of an input/output PAD (IO PAD), and a ground terminal of the electrostatic discharge protection circuit may be connected to a ground pin of the input/output PAD, so that static electricity is led to be discharged in an input/output power supply ring through which a large current can flow when an electrostatic discharge event occurs at the input/output PAD. For another example, the esd protection circuit V0 may be connected to a power terminal of the power ring of the chip, and a ground terminal of the esd protection circuit may be connected to a ground terminal of the power ring of the chip.

In the electrostatic discharge protection circuit shown in fig. 1, the junction of the resistor R0 and the capacitor C0 is connected to the first input terminal of the inverter P0, and the voltage at the junction of the resistor R0 and the capacitor C0 is the same as the voltage at the first input terminal of the inverter P0. The second input terminal of the inverter P0 is connected to the esd protection circuit V0, and the voltage of the second input terminal of the inverter P0 is the same as the voltage of the esd protection circuit V0. The breakover voltage of the inverter P0 is proportional to the voltage at the second input of the inverter P0. When the voltage of the first input terminal of the inverter P0 is the same as the voltage of the second input terminal of the inverter P0, the breakover voltage of the inverter P0 is lower than the voltage of the first input terminal of the inverter P0, the output terminal of the inverter P0 is connected to the ground terminal of the inverter P0, and the output terminal of the inverter P0 outputs a low voltage. When the breakover voltage of the inverter P0 is greater than or equal to the voltage of the first input terminal of the inverter P0, the output terminal of the inverter P0 is connected to the second input terminal of the inverter P0, and the output terminal of the inverter P0 outputs a high voltage.

When the chip normally operates (i.e., when no electrostatic discharge event occurs to a pin or device of the chip that is turned on with the electrostatic discharge terminal V0), the voltage at the connection point of the resistor R0 and the capacitor C0 is the same as the voltage at the electrostatic discharge terminal V0, the voltage at the first input terminal of the inverter P0 is the same as the voltage at the second input terminal of the inverter P0, the breakover voltage of the inverter P0 is smaller than the voltage at the first input terminal of the inverter P0, the output terminal of the inverter P0 is turned on with the ground terminal of the inverter P0, the output terminal of the inverter P0 outputs a low voltage, the gate of the N-type transistor N0 receives the low voltage, the drain of the N-type transistor N0 is turned off with the source of the N-type transistor N0, and the electrostatic discharge terminal V0 is disconnected from ground, thereby preventing the electrostatic discharge terminal V0 from being grounded when the chip normally operates.

When an electrostatic discharge event occurs on a pin or a device in the chip that is in conduction with the electrostatic discharge terminal V0, the voltage of the electrostatic discharge terminal V0 rises, the breakover voltage of the inverter P0 and the voltage at the connection between the resistor R0 and the capacitor C0 also rise, wherein the breakover voltage of the inverter P0 rises faster than the voltage at the connection between the resistor R0 and the capacitor C0, when the breakover voltage of the inverter P0 is greater than or equal to the voltage at the connection between the resistor R0 and the capacitor C0 (i.e., the breakover voltage of the inverter P0 is greater than or equal to the voltage at the first input terminal of the inverter P0), the output terminal of the inverter P0 is in conduction with the second input terminal of the inverter P0, the output terminal of the inverter P0 outputs a high voltage, the gate of the N0 receives the high voltage signal, the drain of the N-type transistor N0 is in conduction with the source of the N-type transistor N0, and the electrostatic discharge terminal V0 is in conduction with the ground, the static electricity at the static electricity discharge end V0 is led to the ground.

In view of this, embodiments of the present disclosure provide an esd protection circuit and a chip having the same, so as to overcome the technical defect in the prior art that whether an esd protection circuit is to perform an esd protection cannot be known in advance.

The following further describes specific implementations of embodiments of the present application with reference to the drawings of the embodiments of the present application.

Example one

Fig. 2 is a schematic circuit structure diagram of an electrostatic discharge protection circuit according to an embodiment of the present disclosure, and fig. 4 is a schematic circuit structure diagram of an electrostatic discharge protection circuit according to an embodiment of the present disclosure, as shown in fig. 2 and fig. 4, in the electrostatic discharge protection circuit according to an embodiment of the present disclosure, the electrostatic discharge protection circuit includes: an RC module 101, an alarm module 102, and a bleeding module 103. Wherein the output voltage of the RC module 101 increases when the input voltage increases.

The alarm module 102 receives an input voltage of the RC module 101 and an output voltage of the RC module 101, increases the alarm voltage of the alarm module 102 when the input voltage of the RC module 101 increases, and outputs an electrostatic alarm signal when the alarm voltage is greater than or equal to the output voltage of the RC module 101.

The leakage module 103 receives the input voltage of the RC module 101 and the output voltage of the RC module 101, the leakage voltage of the leakage module 103 increases when the input voltage of the RC module 101 increases, and when the leakage voltage is greater than or equal to the output voltage of the RC module 101, electrostatic leakage is performed, and the alarm voltage is greater than the leakage voltage.

Illustratively, the alarm module 102 outputs the electrostatic alarm signal such that the signal output by the alarm module 102 toggles from a low voltage to a high voltage. The input of the RC module 101 may be connected to a device in the chip where an electrostatic discharge event may occur, for example, as shown in fig. 5, the input of the RC module 101 may be connected to a power supply pin VDDIO PAD 110 of an input output PAD (IO PAD). For another example, as shown in fig. 6, the ground of the electrostatic discharge protection circuit may be connected to the ground VSSIO PAD 120 of the input/output PAD (IO PAD).

An increase in the input voltage of the RC module 101 may cause an electrostatic discharge event at the input of the RC module 101, for example, an electrostatic discharge event of a Human Body Model (HBM), and the input voltage of the RC module 101 may increase instantaneously. In addition, as the input voltage of the RC module 101 increases, the output voltage of the RC module 101, the alarm voltage of the alarm module 102, and the bleed voltage of the bleed module 103 all increase.

In the electrostatic discharge protection circuit provided by the embodiment of the application, when an electrostatic discharge event occurs, because static high voltage impact is received in the twinkling of an eye, the input voltage of the RC module can rise sharply, at this moment, the output voltage of the RC module, the alarm voltage of the alarm module and the discharge voltage of the discharge module are increased, wherein because the alarm voltage is greater than the discharge voltage, the moment when the alarm voltage is greater than or equal to the output voltage of the RC module is earlier than the moment when the discharge voltage is greater than the output voltage of the RC module, it is ensured that the alarm module outputs an electrostatic alarm signal first, so as to warn that electrostatic discharge is to be performed, and then the discharge module performs electrostatic discharge. Therefore, the electrostatic discharge protection circuit provided by the embodiment of the application can output the electrostatic warning signal to warn that the electrostatic discharge event is about to occur before electrostatic discharge, so that the chip can take software or hardware precautionary measures or post-remedial measures aiming at the electrostatic discharge event, and the probability of unrecoverable hardware damage or operation error of the chip during electrostatic discharge is reduced, thereby improving the working stability of the chip and improving the user experience.

Example two

On the basis of the first embodiment, in the electrostatic discharge protection circuit provided in the second embodiment of the present application, both the initial value of the alarm voltage of the alarm module and the initial value of the discharge voltage of the discharge module are smaller than the initial value of the output voltage of the RC module, and both the increase rate of the alarm voltage of the alarm module and the increase rate of the discharge voltage of the discharge module are greater than the increase rate of the output voltage of the RC module.

Illustratively, the initial value of the output voltage of the RC module is a value of the output voltage of the RC module when no electrostatic discharge event occurs at the input end of the RC module (i.e. the chip where the electrostatic discharge protection circuit is located is in a normal operation state). Likewise, the initial value of the alarm voltage of the alarm module may be understood as the value of the alarm voltage of the alarm module when no electrostatic discharge event occurs at the input of the RC module, and the initial value of the bleed voltage of the bleed module may be understood as the value of the bleed voltage of the bleed module when no electrostatic discharge event occurs at the input of the RC module.

For example, fig. 3 is a schematic diagram of a voltage variation with time provided by an embodiment of the present application, as shown in fig. 3, a time t0 is a time when an electrostatic discharge event occurs at an input end of an RC module, before a time t0, a chip where an electrostatic discharge protection circuit is located is in a normal operation state, an initial value of an output voltage Vc of the RC module is the same as an input voltage VDD of the RC module, and both a warning voltage Vth _ inv _ det of the warning module and a discharge voltage Vth _ inv _ ramp of the discharge module before the time t0 are smaller than the output voltage Vc of the RC module, the discharge voltage Vth _ inv _ ramp of the discharge module is smaller than the warning voltage Vth _ inv _ ramp of the warning module, before the time t0, the warning module does not output an electrostatic warning signal and the discharge module does not perform electrostatic discharge.

At time t0, an electrostatic discharge event occurs at the input terminal of the RC module, the input voltage VDD of the RC module starts to rise sharply, and at this time, the output voltage VC of the RC module, the alarm voltage Vth _ inv _ det of the alarm module, and the discharge voltage Vth _ inv _ clamp of the discharge module all start to rise. The speed increase of the alarm voltage Vth _ inv _ det of the alarm module and the bleeder voltage Vth _ inv _ clamp of the bleeder module are both larger than the speed increase of the output voltage VC of the RC module.

Because the alarm voltage Vth _ inv _ det of the alarm module is always greater than the bleeder voltage Vth _ inv _ clamp of the bleeder module, the alarm voltage Vth _ inv _ det of the alarm module is increased to be the same as the output voltage VC of the RC module at the time t1, the alarm module outputs an electrostatic alarm signal at the time t1, the bleeder voltage Vth _ inv _ clamp of the bleeder module is also increased to be the same as the output voltage VC of the RC module at the time t2 after the time t1, and the bleeder module performs electrostatic bleeder at the time t 1.

For example, in an embodiment of the present application, as shown in fig. 4, the RC module 101 may include a first resistor 211 and a first capacitor 221 connected in series, and a connection point of the first resistor 211 and the first capacitor 221 is an output voltage terminal of the RC module 101. The alarm module 102 may include a first inverter 212. The first input end of the first inverter 212 receives the input voltage of the RC module 101, the second input end of the first inverter 212 receives the output voltage of the RC module 101, and when the alarm voltage is greater than the output voltage of the RC module 101, the first input end of the first inverter 212 is connected to the output end of the first inverter 212, and the electrostatic alarm signal is output. The bleeding module may include a second inverter 213 and a first switching unit 223. A first input terminal of the second inverter 213 receives the input voltage of the RC module 101, a second input terminal of the second inverter 213 receives the output voltage of the RC module 101, and when the alarm voltage is greater than or equal to the output voltage of the RC module, an output terminal of the second inverter 213 is connected to the first input terminal of the first switching unit 223. The first input terminal of the first switching unit 223 is connected to the output terminal of the second inverter 213, and when the output voltage of the second inverter 213 is greater than the first switching voltage, the first switching unit 223 is turned on to implement electrostatic discharge.

The warning voltage may be a breakover voltage of the first inverter 212, and the discharging voltage may be a breakover voltage of the second inverter 213.

It should be noted that the breakover voltage of the inverter is proportional to the power supply voltage of the inverter, and the breakover voltage of the inverter is smaller than the power supply voltage of the inverter. When the breakover voltage of the inverter is less than the voltage input into the inverter, the output end of the inverter is conducted with the grounding end of the inverter, and the output end of the inverter outputs low voltage. When the breakover voltage of the inverter is greater than or equal to the voltage input to the inverter, the output end of the inverter is conducted with the power supply end voltage of the inverter, and the output end of the inverter outputs high voltage, namely the power supply voltage. In an embodiment of the present application, the first inverter 212 receives a power supply voltage, i.e. an input voltage of the RC module 101, through a first input terminal, and the first inverter 212 receives an input voltage, i.e. an output voltage of the RC module 101, through a second input terminal; the second inverter 213 receives the supply voltage, i.e. the input voltage of the RC-module 101, via a first input terminal, and the second inverter 213 receives the input voltage, i.e. the output voltage of the RC-module 101, via a second input terminal.

When the first inverter 212 is composed of NMOS and PMOS transistors, the transition voltage Vth _ inv _ det of the first inverter 212 can be determined according to

Determining that VDD is the power voltage of the first inverter 212, i.e. the input voltage of the RC module 101, Vthp is the conduction voltage of the PMOS transistor in the first inverter 212, Vthn is the secondThe turn-on voltage of the NMOS transistor in one inverter 212, β p is the transconductance parameter of the PMOS transistor in the first inverter 212, and β n is the transconductance parameter of the NMOS transistor in the first inverter 212. The transconductance parameter betan of the NMOS tube can be adjusted by adjusting the width-to-length ratio of the NMOS tube, and the transconductance parameter betap of the PMOS tube can be adjusted by adjusting the width-to-length ratio of the PMOS tube. The conduction voltage Vthn of the NMOS tube and the transconductance parameter betan of the NMOS tube can be adjusted by adjusting the preparation process of the NMOS tube, and the conduction voltage Vthp of the PMOS tube and the transconductance parameter betap of the PMOS tube can be adjusted by adjusting the preparation process of the PMOS tube. By adjusting the conduction voltage Vthn of the NMOS transistor in the first inverter 212, the transconductance parameter β n of the NMOS transistor, the conduction voltage Vthp of the PMOS transistor, and the transconductance parameter β p of the PMOS transistor, the breakover voltage Vth _ inv _ det of the first inverter 212, i.e., the ratio of the alarm voltage to the input voltage of the RC module 101, can be adjusted, and the ratio of the increase in the alarm voltage to the increase in the input voltage of the RC module 101 can be adjusted.

Similarly, when the second inverter 213 is composed of an NMOS transistor and a PMOS transistor, by adjusting the turn-on voltage Vthn1 of the NMOS transistor, the transconductance parameter β n1 of the NMOS transistor, the turn-on voltage Vthp1 of the PMOS transistor, and the transconductance parameter β p1 of the PMOS transistor in the second inverter 212, the ratio of the breakover voltage Vth _ inv _ clamp (i.e., the bleed voltage) of the second inverter 213 to the input voltage of the RC module 101 can be adjusted, and the ratio of the speed increase of the bleed voltage to the speed increase of the input voltage of the RC module 101 can be adjusted.

Since the initial value of the alarm voltage may be understood as the value of the alarm voltage when no electrostatic discharge event occurs at the input of the RC module 101, the initial value of the bleed voltage may be understood as the value of the bleed voltage when no electrostatic discharge event occurs at the input of the RC module 101. And the output voltage of the RC module 101 is equal to the voltage on the first capacitor 221. When the electrostatic discharge event does not occur at the input end of the RC module 101, the voltage on the first capacitor 221 is equal to the input voltage of the RC module 101, that is, the initial value of the output voltage of the RC module 101 is the input voltage of the RC module 101, so that the ratio of the alarm voltage to the input voltage of the RC module 101 and the ratio of the discharge voltage to the input voltage of the RC module 101 are adjusted according to the above method, so that the alarm voltage and the discharge voltage are both smaller than the input voltage of the RC module 101, and it can be ensured that the initial value of the alarm voltage and the initial value of the discharge voltage are both smaller than the initial value of the output voltage of the RC module.

In addition, since the output voltage of the RC module 101 is equal to the voltage on the first capacitor 221 in the RC module, the voltage on the first capacitor 221 cannot change abruptly, and the increase rate of the voltage on the first capacitor 221 is smaller than the increase rate of the input voltage of the RC module 101, so that the output voltage of the RC module 101 is smaller than the increase rate of the input voltage of the RC module 101. By adjusting the ratio of the alarm voltage increase rate to the input voltage increase rate of the RC module 101 and the ratio of the bleed voltage increase rate to the input voltage increase rate of the RC module 101, the alarm voltage increase rate and the bleed voltage increase rate can both be greater than the input voltage increase rate of the RC module 101, thereby ensuring that the alarm voltage increase rate and the bleed voltage increase rate are both greater than the output voltage increase rate of the RC module.

The initial value of the alarm voltage of the alarm module and the initial value of the leakage voltage of the leakage module are smaller than the initial value of the output voltage of the RC module, so that the static leakage protection circuit can not output a static alarm signal under the initial state, the leakage module can not perform static leakage, and the normal work of other components in a chip can not be influenced by the static leakage protection circuit. The alarm voltage of the alarm module is increased more than the output voltage of the RC module, so that the alarm voltage of the alarm module is increased to be more than the output voltage of the RC module along with the increase of time, and the output alarm module outputs an electrostatic alarm signal; similarly, the speed increase of the bleed-off voltage of the bleed-off module is greater than the speed increase of the output voltage of the RC module, so that the bleed-off voltage of the bleed-off module increases to be greater than the output voltage of the RC module along with the increase of time, and the bleed-off module performs electrostatic discharge.

EXAMPLE III

On the basis of the first embodiment, as shown in fig. 4, in the electrostatic discharge protection circuit provided in the third embodiment of the present application, the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102, and a discharge module 103. The RC module 101 includes a first resistor 211 and a first capacitor 221 connected in series, one end of the first capacitor 221 is grounded, the other end of the first capacitor 221 is connected to the first resistor 211, the other end of the first resistor 211 is an input voltage end of the RC module 101, and a connection point between the first resistor 211 and the first capacitor 221 is an output voltage end of the RC module 101.

Specifically, the first resistor 211 may also be a plurality of resistors connected in series or in parallel, which is not limited in the embodiment of the present application, and fig. 4 shows that the first resistor 211 is taken as one resistor as an example. The first capacitor 221 may also be a plurality of capacitors connected in series or in parallel, which is not limited in this embodiment of the application, and fig. 4 shows the first capacitor 221 as one capacitor.

The first resistor 211 and the first capacitor 221 connected in series form an RC circuit structure, and when the voltage input from the input voltage terminal of the RC module 101 increases, the voltage on the first capacitor 221 also increases. The charging time constant of the RC circuit structure can be adjusted by adjusting the resistance value of the first resistor 211 and the capacitance value of the first capacitor 221, and the charging time constant of the RC circuit structure is positively correlated with the increase rate of the voltage across the first capacitor 221, so that the increase rate of the voltage across the first capacitor 221, that is, the increase rate of the output voltage at the output voltage terminal of the RC module 101 can be adjusted by adjusting the resistance value of the first resistor 211 and the capacitance value of the first capacitor 221.

The bleed-off module 103 performs electrostatic bleed-off when the bleed-off voltage is greater than or equal to the output voltage of the RC module 101. If the input voltage of the RC module 101 is not increased and the bleeding voltage is not increased, by slowing down the increase of the output voltage at the output voltage end of the RC module 101, the time when the bleeding voltage is greater than or equal to the output voltage of the RC module 101, that is, the time when the bleeding module 103 performs electrostatic bleeding, can be advanced; by accelerating the increase of the output voltage at the output voltage end of the RC module 101, the time when the bleed-off voltage is greater than or equal to the output voltage of the RC module 101, that is, the time when the electrostatic bleed-off is performed by the advanced bleed-off module 103, can be delayed.

The alarm module 102 outputs the static alarm signal when the alarm voltage is greater than or equal to the output voltage of the RC module 101, and if the input voltage of the RC module 101 increases and the alarm voltage increases, the time when the alarm voltage is greater than or equal to the output voltage of the RC module 101, that is, the time when the alarm module 102 outputs the static alarm signal, can be advanced by slowing down the increase in the output voltage of the output voltage terminal of the RC module 101; by accelerating the increase of the output voltage end of the RC module 101, the time when the alarm voltage is greater than or equal to the output voltage of the RC module 101, that is, the time when the alarm module 102 outputs the electrostatic alarm signal, can be delayed.

In summary, by adjusting the resistance of the first resistor 211 and the capacitance of the first capacitor 221, the time when the leakage module 103 performs the electrostatic leakage and the time when the alarm module 102 outputs the electrostatic alarm signal can be adjusted on the premise that the input voltage, the leakage voltage, and the alarm voltage of the RC module 101 are not increased.

Preferably, the resistance value of the first resistor 211 may be 1m Ω, and the capacitance value of the first capacitor 221 may be 1 pF.

Example four

On the basis of the first embodiment, as shown in fig. 4, in the electrostatic discharge protection circuit provided in the fourth embodiment of the present application, the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102, and a discharge module 103. Wherein the alarm module 102 includes a first inverter 212. The first inverter 212 is configured to receive an input voltage of the RC module 101 through a first input terminal, receive an output voltage of the RC module 101 through a second input terminal of the first inverter 212, and when the alarm voltage is greater than the output voltage of the RC module 101, the first input terminal of the first inverter 212 is connected to the output terminal of the first inverter 212, so as to output the electrostatic alarm signal.

Specifically, when the first input terminal of the first inverter 212 is connected to the output terminal of the first inverter 212, the output terminal of the first inverter 212 may output the input voltage of the RC module 101, so that the electrostatic warning signal is a high voltage.

The first inverter 212 may be a Complementary Metal Oxide Semiconductor (CMOS) circuit, may also be composed of at least two field effect transistors, or may be composed of a plurality of logic gate circuits, and the like, and embodiments of the present application do not specifically limit a specific implementation manner of the first inverter 212.

The alarm voltage may be a breakover voltage of the second inverter 213. It should be noted that the breakover voltage of the inverter is proportional to the power supply voltage of the inverter, and the breakover voltage of the inverter is smaller than the power supply voltage of the inverter. When the breakover voltage of the inverter is less than the input voltage of the inverter, the output end of the inverter is grounded, and the output end of the inverter outputs low voltage. When the breakover voltage of the inverter is greater than or equal to the voltage input to the inverter, the output end of the inverter is conducted with the power supply end voltage of the inverter, and the output end of the inverter outputs high voltage, namely the power supply voltage. In this embodiment, the first inverter 212 receives the power supply voltage, i.e. the input voltage of the RC module 101, through a first input terminal, and the first inverter 212 receives the input voltage, i.e. the output voltage of the RC module 101, through a second input terminal.

For example, when the first inverter 212 is composed of an NMOS transistor and a PMOS transistor, the warning voltage may be the breakover voltage Vth _ inv _ det of the first inverter 212. The transition voltage Vth _ inv _ det of the first inverter 212 can be determined according to

It is determined that VDD is the power voltage of the first inverter 212, i.e., the input voltage of the RC module 101, Vthp is the turn-on voltage of the PMOS transistor in the first inverter 212, Vthn is the turn-on voltage of the NMOS transistor in the first inverter 212, β p is the transconductance parameter of the PMOS transistor in the first inverter 212, and β n is the transconductance parameter of the NMOS transistor in the first inverter 212. The transconductance parameter betan of the NMOS tube can be adjusted by adjusting the width-to-length ratio of the NMOS tube, and the transconductance parameter betap of the PMOS tube can be adjusted by adjusting the width-to-length ratio of the PMOS tube. The conduction voltage Vthn of the NMOS tube and the transconductance parameter beta n of the NMOS tube can be adjusted by adjusting the preparation process of the NMOS tube, and the conduction voltage Vthp of the PMOS tube and the transconductance parameter beta p of the PMOS tube can be adjusted by adjusting the preparation process of the PMOS tube. By adjusting the conduction voltage Vthn of the NMOS tube, the transconductance parameter betan of the NMOS tube, the conduction voltage Vthp of the PMOS tube and the transconductance parameter betap of the PMOS tube in the first inverter 212, the first inverter 212 can be controlledThe breakover voltage Vth _ inv _ det, i.e., the ratio of the alarm voltage to the input voltage of the RC module 101, is adjusted, and the ratio of the increase in the alarm voltage to the increase in the input voltage of the RC module 101 can also be adjusted.

Optionally, in an embodiment of the present application, when the alarm voltage of the first inverter 212 is smaller than the output voltage of the RC module 101, the ground terminal of the first inverter 212 is connected to the output terminal of the first inverter 212.

Specifically, when the alarm voltage is less than the output voltage of the RC module 101, it may be understood that the electrostatic discharge event is ended, when the alarm voltage of the first inverter 212 is less than the output voltage of the RC module 101, the ground terminal of the first inverter 212 is conducted with the output terminal of the first inverter 212, the output voltage of the output terminal of the first inverter 212 is 0, and when the output voltage of the output terminal of the first inverter 212 is 0, it may be considered that the output terminal of the first inverter 212 does not output the electrostatic alarm signal, so that an alarm is not given after the electrostatic discharge event is ended, the chip is prevented from executing an unnecessary processing operation after the electrostatic discharge event is ended, and the processing resources of the chip are saved.

EXAMPLE five

On the basis of the first embodiment, as shown in fig. 4, in the electrostatic discharge protection circuit provided in the fifth embodiment of the present application, the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102, and a discharge module 103. Wherein, the bleeding module includes a second inverter 213 and a first switch unit 223.

A first input terminal of the second inverter 213 receives the input voltage of the RC module 101, a second input terminal of the second inverter 213 receives the output voltage of the RC module 101, and when the alarm voltage is greater than or equal to the output voltage of the RC module, an output terminal of the second inverter 213 is connected to the first input terminal of the first switching unit 223.

The first input terminal of the first switching unit 223 is connected to the output terminal of the second inverter 213, and when the output voltage of the second inverter 213 is greater than the first switching voltage, the first switching unit 223 is turned on to implement electrostatic discharge.

Specifically, the second input terminal of the first switch unit 223 is connected to the input terminal of the RC module 101, the output terminal of the first switch unit 223 is grounded, and when the output voltage of the second inverter 213 is greater than the first switch voltage, the second input terminal of the first switch unit 223 is conducted with the output terminal of the first switch unit 223, so as to guide the static electricity at the input terminal of the RC module 101 to the ground, thereby achieving static electricity discharge.

The bleed voltage may be a breakover voltage of the second inverter 213. It should be noted that the breakover voltage of the inverter is proportional to the power supply voltage of the inverter, and the breakover voltage of the inverter is smaller than the power supply voltage of the inverter. When the breakover voltage of the inverter is less than the input voltage of the inverter, the output end of the inverter is grounded, and the output end of the inverter outputs low voltage. When the breakover voltage of the inverter is greater than or equal to the voltage input to the inverter, the output end of the inverter is conducted with the power supply end voltage of the inverter, and the output end of the inverter outputs high voltage, namely the power supply voltage. In this embodiment, the second inverter 213 receives the power supply voltage, i.e. the input voltage of the RC module 101, through a first input terminal, and the second inverter 213 receives the input voltage, i.e. the output voltage of the RC module 101, through a second input terminal.

For example, when the second inverter 213 is composed of an NMOS transistor and a PMOS transistor, the breakover voltage Vth _ inv _ clamp of the second inverter 213 may be determined according to

It is determined that VDD is the power voltage of the second inverter 213, i.e., the input voltage of the RC module 101, Vthp1 is the turn-on voltage of the PMOS transistor in the second inverter 213, Vthn1 is the turn-on voltage of the NMOS transistor in the second inverter 213, β p1 is the transconductance parameter of the PMOS transistor in the second inverter 213, and β n1 is the transconductance parameter of the NMOS transistor in the second inverter 213. The transconductance parameter betan 1 of the NMOS tube can be adjusted by adjusting the width-to-length ratio of the NMOS tube, and the transconductance parameter betap 1 of the PMOS tube can be adjusted by adjusting the width-to-length ratio of the PMOS tube. The conduction voltage Vthn1 of the NMOS tube and the transconductance parameter beta n1 of the NMOS tube can be adjusted by adjusting the preparation process of the NMOS tube, and the conduction voltage Vthp1 of the PMOS tube and the transconductance parameter beta p1 of the PMOS tube can be adjusted by adjusting the preparation process of the PMOS tube. By adjusting the second inverseThe turn-on voltage Vthn1 of the NMOS transistor, the transconductance parameter β n1 of the NMOS transistor, the turn-on voltage Vthp1 of the PMOS transistor, and the transconductance parameter β p1 of the PMOS transistor in the inverter 213 may adjust the ratio of the breakover voltage Vth _ inv _ clamp, i.e., the bleeder voltage, of the second inverter 213 to the input voltage of the RC module 101, and may also adjust the ratio of the increase in the alarm voltage to the increase in the input voltage of the RC module 101.

The first switching unit 223 may be composed of one or more transistors, and when the first switching unit 223 includes a plurality of transistors, the plurality of transistors may perform corresponding switching actions when the output voltage of the second inverter 213 is greater than the first switching voltage, respectively, to turn on the first switching unit 223. The embodiment of the present application does not specifically limit the composition of the first switching unit 223. In fig. 4, it is exemplified that the first switch unit 223 includes a single N-type transistor, wherein a gate of the N-type transistor receives the output voltage of the second inverter 213, a drain of the N-type transistor is connected to the input terminal of the RC module 101, a source of the N-type transistor is grounded, and when a voltage at the gate of the N-type transistor is greater than the first switch voltage, the drain of the N-type transistor is conducted to the source of the N-type transistor, and static electricity at the input terminal of the RC module 101 is conducted to the ground through the N-type transistor to implement static electricity discharge.

EXAMPLE six

On the basis of any one of the first to fifth embodiments, fig. 7 is a schematic circuit structure diagram of an electrostatic discharge protection circuit provided in the embodiment of the present application, and as shown in fig. 7, in the electrostatic discharge protection circuit provided in the sixth embodiment of the present application, the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102, and a discharge module 103. The electrostatic discharge protection circuit further includes a pulse extension alarm module 104, where the pulse extension alarm module 104 delays the electrostatic alarm signal and outputs a delayed electrostatic alarm signal whose duration is longer than the duration of the electrostatic alarm signal.

Specifically, the duration time of the electrostatic discharge event is often short (for example, the electrostatic discharge event disappears after lasting about 100 nS), when the alarm signal occurs, the speed of taking a precautionary measure on hardware by the chip may be very fast, but the speed of software processing may not respond to the alarm signal in time, the pulse extension alarm module 104 delays the electrostatic alarm signal and outputs a delayed electrostatic alarm signal whose duration time is longer than that of the electrostatic alarm signal, so that it is convenient for the circuit module in the chip where the MCU or the electrostatic discharge protection circuit is located, which is used for processing the electrostatic discharge event, to respond to the delayed electrostatic alarm signal whose duration time is longer than that of the electrostatic alarm signal when not responding to the alarm signal in time, for example, to perform subsequent error correction, and the like, thereby improving the working stability of the chip and improving the user experience.

EXAMPLE seven

On the basis of the sixth embodiment, fig. 8 is a schematic circuit structure diagram of a pulse extension alarm module provided in the seventh embodiment of the present application, as shown in fig. 7 and fig. 8, in an electrostatic discharge protection circuit provided in the seventh embodiment of the present application, the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102, a discharge module 103, and a pulse extension alarm module 104, where the pulse extension alarm module 104 includes a second switch unit 114, a third switch unit 124, a second capacitor 134, and a third inverter 144.

The second switch unit 114 is turned on when the first input terminal of the second switch unit 114 receives the electrostatic warning signal, and is turned off when the first input terminal of the second switch unit 114 does not receive the electrostatic warning signal.

The third switching unit 124 is turned off when the first input terminal of the third switching unit 124 receives the electrostatic warning signal, and turned on when the first input terminal of the third switching unit 124 does not receive the electrostatic warning signal.

And a second capacitor 134 for charging when the second switching unit 114 is turned off and the third switching unit 134 is turned on, and discharging when the second switching unit 114 is turned on and the third switching unit 134 is turned off.

The third inverter 144 has a first input terminal receiving the voltage of the second capacitor 134, and outputs a delayed electrostatic warning signal when the voltage of the second capacitor 134 is smaller than the pulse spreading voltage.

Specifically, a first input end of the second switch unit 114 is connected to the output end of the alarm module 102, a second input end of the second switch unit 114 is connected to a first end of the second capacitor 134, and an output end of the second switch unit 114 is grounded. The first input terminal of the third switching unit 124 is connected to the output terminal of the alarm module 102, the second input terminal of the third switching unit 124 receives the input voltage of the RC module 101, the output terminal of the third switching unit 124 is connected to the first terminal of the second capacitor 134, and the second terminal of the second capacitor 134 is grounded. A second input terminal of the third inverter 144 receives the input voltage of the RC module 101, and the third inverter 144 has a ground terminal.

When the output terminal of the alarm module 102 outputs the electrostatic alarm signal, the first input terminal of the second switch unit 114 receives the electrostatic alarm signal output by the output terminal of the alarm module 102, the second input terminal of the second switch unit 114 is connected to the output terminal of the second switch unit 114, the first terminal of the second capacitor 134 is grounded, meanwhile, the first input terminal of the third switching unit 124 receives the electrostatic warning signal output by the output terminal of the warning module 102, the second input terminal of the third switching unit 124 is disconnected from the output terminal of the third switching unit 124, the output terminal of the third switching unit 124 does not output any voltage to the first terminal of the second capacitor 134, the first terminal of the second capacitor 134 discharges, so that the voltage of the second capacitor 134 is in a state of being smaller than the pulse extension voltage, the first input terminal of the third inverter 144 receives the voltage of the second capacitor 134, and the delay electrostatic warning signal is output through the output terminal of the third inverter 144.

When the output end of the alarm module 102 does not output the static electricity alarm signal, the first input end of the second switch unit 114 does not receive the static electricity alarm signal output by the output end of the alarm module 102, the second input end of the second switch unit 114 is disconnected from the output end of the second switch unit 114, so that the first end of the second capacitor 134 is disconnected from the ground, and meanwhile, when the first input end of the third switch unit 124 does not receive the static electricity alarm signal output by the output end of the alarm module 102, the second input end of the third switch unit 124 is connected with the output end of the third switch unit 124, the input voltage of the RC module 101 is output to the first end of the second capacitor 134 through the output end of the third switch unit 124, and the second capacitor 134 is charged, so that the voltage of the second capacitor 134 is increased. The first input end of the third inverter 144 receives the voltage of the second capacitor 134, and when the voltage of the second capacitor 134 is not increased to be greater than or equal to the pulse extension voltage, the third inverter 144 still outputs the delay static warning signal; when the voltage of the second capacitor 134 increases to be greater than or equal to the pulse extension voltage, the third inverter 144 stops outputting the delayed electrostatic warning signal, wherein a time length from a time when the output terminal of the alarm module 102 does not output the electrostatic warning signal to a time when the voltage of the second capacitor 134 increases to be greater than or equal to the pulse extension voltage may be understood as a time difference between a duration of the delayed electrostatic warning signal and a duration of the electrostatic warning signal.

It should be noted that the time when the third inverter 144 outputs the delayed electrostatic warning signal is later than the time when the warning module 102 outputs the electrostatic warning signal, but the time difference between the two times is very short and can be ignored.

The second switch unit 114 may be composed of one or more transistors, and when the second switch unit 114 includes a plurality of transistors, the plurality of transistors may respectively perform corresponding switching actions to turn on the second switch unit 114 when the first input terminal of the second switch unit 114 receives the electrostatic warning signal, or may respectively perform corresponding switching actions to turn off the second switch unit 114 when the first input terminal of the second switch unit 114 does not receive the electrostatic warning signal. The embodiment of the present application does not specifically limit the composition of the second switching unit 114.

The third switching unit 124 may be composed of one or more transistors, and when the third switching unit 124 includes a plurality of transistors, the plurality of transistors may respectively perform corresponding switching actions to turn on the third switching unit 124 when the first input terminal of the third switching unit 124 receives the static electricity warning signal, or may respectively perform corresponding switching actions to turn off the third switching unit 124 when the first input terminal of the third switching unit 124 does not receive the static electricity warning signal. The embodiment of the present application does not specifically limit the composition of the third switching unit 124. The second capacitor 134 may also include a plurality of capacitors connected in series or in parallel, which is not limited in the embodiments of the present application.

The third inverter 144 may be a complementary metal oxide semiconductor circuit, and may also be composed of at least two field effect transistors, or a plurality of logic gates, and the like, and the embodiment of the present application is not limited to a specific implementation manner of the third inverter 144.

The pulse extension voltage may be a breakover voltage of the third inverter 144. It should be noted that the breakover voltage of the inverter is proportional to the power supply voltage of the inverter, and the breakover voltage of the inverter is smaller than the power supply voltage of the inverter. When the breakover voltage of the inverter is less than the input voltage of the inverter, the output end of the inverter is grounded, and the output end of the inverter outputs low voltage. When the breakover voltage of the inverter is greater than or equal to the voltage input to the inverter, the output end of the inverter is conducted with the power supply end voltage of the inverter, and the output end of the inverter outputs high voltage, namely the power supply voltage. In the present embodiment, the third inverter 144 receives the power voltage, i.e. the input voltage of the RC module 101, through the second input terminal, and the third inverter 144 receives the input voltage, i.e. the voltage of the second capacitor 134, through the first input terminal.

For example, when the third inverter 144 is composed of an NMOS transistor and a PMOS transistor, the pulse spreading voltage may be the breakover voltage Vth _ inv _ pulse of the third inverter 144. The breakover voltage Vth _ inv _ pulse of the third inverter 144 can be determined according to

It is determined that VDD is the power voltage of the third inverter 144, i.e., the input voltage of the RC module 101, Vthp2 is the turn-on voltage of the PMOS transistor in the third inverter 144, Vthn2 is the turn-on voltage of the NMOS transistor in the third inverter 144, β p2 is the transconductance parameter of the PMOS transistor in the third inverter 144, and β n2 is the transconductance parameter of the NMOS transistor in the third inverter 144. The transconductance parameter betan 2 of the NMOS tube can be adjusted by adjusting the width-to-length ratio of the NMOS tube, and the transconductance parameter betap 2 of the PMOS tube can be adjusted by adjusting the width-to-length ratio of the PMOS tube. The conduction voltage Vthn2 of the NMOS tube and the transconductance parameter beta n2 of the NMOS tube can be adjusted by adjusting the preparation process of the NMOS tube, and the conduction voltage Vthp2 of the PMOS tube and the transconductance parameter beta p2 of the PMOS tube can be adjusted by adjusting the preparation process of the PMOS tube. By adjusting the turn-on voltage Vthn2 of the NMOS transistor, the transconductance parameter β n2 of the NMOS transistor, the turn-on voltage Vthp2 of the PMOS transistor, and the transconductance parameter β p2 of the PMOS transistor in the third inverter 144, the breakover voltage Vth _ inv _ pulse of the third inverter 144, i.e., the ratio of the pulse expansion voltage to the input voltage of the RC module 101, can be adjusted, and the ratio of the increase rate of the pulse expansion voltage to the increase rate of the input voltage of the RC module 101 can be adjusted.

It should be noted that, when the voltage of the second capacitor 134 is charged to be greater than or equal to the pulse extension voltage (i.e., when the voltage of the second capacitor 134 is increased to be greater than or equal to the pulse extension voltage), the voltage input to the first input terminal of the third inverter 144 is greater than or equal to the pulse extension voltage, and the third inverter 144 stops outputting the delayed electrostatic warning signal, so that the duration of the delayed electrostatic warning signal can be adjusted by adjusting the charging speed of the voltage of the second capacitor 134. By adjusting the resistance between the first input terminal of the third switching unit 124 and the output terminal of the third switching unit 124 and the capacitance of the second capacitor 134, the RC time constant between the third switching unit 124 and the second capacitor 134 can be adjusted, so as to adjust the charging speed of the second capacitor 134.

Example eight

On the basis of the seventh embodiment, as shown in fig. 7 and fig. 8, in the electrostatic discharge protection circuit provided in the eighth embodiment of the present application, the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102, a discharge module 103, and a pulse extension alarm module 104, where the pulse extension alarm module 104 includes a second switching unit 114, a third switching unit 124, a second capacitor 134, and a third inverter 144. A second input terminal of the third inverter 114 is connected to the input voltage terminal of the RC module 101, and when the voltage of the second capacitor 134 is smaller than the pulse spreading voltage, a second input terminal of the third inverter 144 is connected to the output terminal of the third inverter 144.

The second input end of the third inverter 144 receives the input voltage of the RC module 101, when the voltage of the second capacitor 134 received by the first input end of the third inverter 144 is smaller than the pulse extension voltage, the second input end of the third inverter 144 is connected to the output end of the third inverter 144, and the output end of the third inverter 144 outputs the input voltage signal of the RC module 101, so that the delayed electrostatic warning signal is a high voltage, and the voltage value of the delayed electrostatic warning signal is ensured to meet the requirement.

Further, when the voltage of the second capacitor 134 received by the first input terminal of the third inverter 144 is greater than or equal to the pulse extension voltage, the ground terminal of the third inverter 144 is connected to the output terminal of the third inverter 144, the delayed electrostatic warning signal is a high voltage, and the output terminal of the third inverter 144 stops outputting the delayed electrostatic warning signal.

Example nine

Based on the eighth embodiment, as shown in fig. 7 and fig. 8, in the electrostatic discharge protection circuit provided in the ninth embodiment of the present application, the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102, a discharge module 103, and a pulse extension alarm module 104, where the pulse extension alarm module 104 includes a second switching unit 114, a third switching unit 124, a second capacitor 134, and a third inverter 144.

The third switching unit 124 includes a P-type transistor, a gate of the P-type transistor receives the electrostatic warning signal, a drain of the P-type transistor receives the input voltage of the RC module 11, a source of the P-type transistor is connected to the second capacitor 134, and the P-type transistor is turned on when the electrostatic warning signal is greater than or equal to the first switching threshold.

Since the process of setting the transistor in the chip is mature, the cost is low, and the third switching unit 144 includes a P-type transistor, the third switching unit 144 can be turned on when the electrostatic warning signal is greater than or equal to the first switching threshold value on the premise of low manufacturing cost.

Example ten

On the basis of the eighth embodiment, as shown in fig. 7 and fig. 9, in the electrostatic discharge protection circuit provided in the tenth embodiment of the present application, the electrostatic discharge protection circuit includes an RC module 101, an alarm module 102, a discharge module 103, and a pulse extension alarm module 104, where the pulse extension alarm module 104 includes a second switching unit 114, a third switching unit 124, a second capacitor 134, and a third inverter 144.

The third switching unit 124 includes n P-type transistors, n is greater than or equal to 2, where n is a natural number, gates of the n P-type transistors receive the electrostatic warning signal, a drain of a first-stage P-type transistor of the n P-type transistors receives the input voltage of the RC module 11, a source of a previous-stage P-type transistor of the n P-type transistors is connected to a drain of an adjacent next-stage P-type transistor, a source of an nth-stage P-type transistor of the n P-type transistors is connected to the second capacitor 134, and the n P-type transistors are turned on when the electrostatic warning signal is greater than or equal to the first switching threshold.

By the third switching unit 144 comprising n P-type transistors, n ≧ 2, compared with the case where the third switching unit 144 comprises only one transistor, the third switching unit 144 can be turned on when the electrostatic warning signal is greater than or equal to the first switching threshold, and at the same time, the resistance of the third switching unit 144 is increased, and the charging time of the second capacitor 134 is extended, thereby extending the duration of the delayed electrostatic warning signal, which is lower in cost compared with the scheme of extending the duration of the delayed electrostatic warning signal by adjusting the structure of the second capacitor 134 or setting a resistance in the third switching unit 144.

EXAMPLE eleven

Fig. 10 is a schematic circuit structure diagram of an electrostatic discharge protection circuit according to an embodiment of the present application, and as shown in fig. 10, on the basis of the first embodiment, in the electrostatic discharge protection circuit according to the eleventh embodiment of the present application, the electrostatic discharge protection circuit further includes a processing module 200.

The processing module 200 receives the static electricity warning signal and performs at least one of a static electricity discharge prevention method and a static electricity discharge remediation method in response to the static electricity warning signal.

The static discharge prevention method includes suspending a program currently executed by the processing module 200.

The method for remedying the electrostatic discharge includes retransmitting data, which is transmitted by the processing module 200 within an electrostatic discharge time interval after the electrostatic warning signal is ended, where the electrostatic discharge time interval is a time interval between the time when the processing module 200 receives the electrostatic warning signal and the time when the processing module 200 stops receiving the electrostatic warning signal.

Specifically, the processing module 200 may be a Micro Controller Unit (MCU), or a circuit module for processing an electrostatic discharge event in a chip where the electrostatic discharge protection circuit is located.

In the electrostatic discharge protection circuit provided in the embodiment of the present application, the processing module 200 receives the electrostatic warning signal, and executes at least one of an electrostatic discharge prevention method and an electrostatic discharge remediation method in response to the electrostatic warning signal. The static discharge prevention method includes suspending the currently executed program of the processing module 200, and by executing the static discharge prevention method, the error of the currently executed program of the processing module 200 caused by the occurrence of the static discharge event can be avoided. The data sent by the processing module 200 in the electrostatic discharge time interval may be corrupted due to the influence of the electrostatic discharge event, and by retransmitting the data after the electrostatic warning signal is ended, the module receiving the data sent by the processing module 200 can acquire the data sent by the processing module 200 without corruption.

Example twelve

On the basis of any one of the first to eleventh embodiments, a chip having an esd protection circuit according to a twelfth embodiment of the present application includes the esd protection circuit according to any one of the first to twelfth embodiments.

The chip that this application embodiment provided includes electrostatic discharge protection circuit, in this electrostatic discharge protection circuit, when taking place electrostatic discharge incident, owing to receive static high-voltage impact in the twinkling of an eye, the input voltage of RC module can rise sharply, the output voltage of RC module this moment, the warning voltage of warning module and the bleeder voltage of bleeder module all increase, wherein because warning voltage is greater than bleeder voltage, consequently the moment that the output voltage of warning voltage is greater than or equal to RC module is earlier than the moment that the bleeder voltage is greater than or equal to the output voltage of RC module, ensure to report an emergency and ask for help or increased vigilance the module earlier and export electrostatic warning signal, just carry out electrostatic discharge with the warning, later the bleeder module. Therefore, the electrostatic discharge protection circuit provided by the embodiment of the application can output the electrostatic warning signal to warn that the electrostatic discharge event is about to occur before electrostatic discharge, so that the chip can take software or hardware precautionary measures or post-remedial measures aiming at the electrostatic discharge event, and the probability of unrecoverable hardware damage or operation error of the chip during electrostatic discharge is reduced, thereby improving the working stability of the chip and improving the user experience.

For convenience of description, the above devices are described as being divided into various units by function, and are described separately. Of course, the functions of the various elements may be implemented in the same or in multiple hardware implementations.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The embodiments in the present specification are described in a progressive manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.

The above description is only an example of the present application and is not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. The electrostatic discharge protection circuit is characterized by comprising an RC module, an alarm module and a discharge module;

the alarm module receives the input voltage of the RC module and the output voltage of the RC module, the alarm voltage of the alarm module is increased when the input voltage of the RC module is increased, and an electrostatic alarm signal is output when the alarm voltage is greater than or equal to the output voltage of the RC module;

the leakage module receives the input voltage of the RC module and the output voltage of the RC module, the leakage voltage of the leakage module is increased when the input voltage of the RC module is increased, electrostatic leakage is performed when the leakage voltage is larger than or equal to the output voltage of the RC module, and the alarm voltage is larger than the leakage voltage.

2. The electrostatic discharge protection circuit of claim 1, wherein an initial value of the alarm voltage of the alarm module and an initial value of the discharge voltage of the discharge module are both smaller than an initial value of the output voltage of the RC module, and an increase rate of the alarm voltage of the alarm module and an increase rate of the discharge voltage of the discharge module are both larger than an increase rate of the output voltage of the RC module.

3. The esd protection circuit of claim 1, wherein the RC module comprises a first resistor and a first capacitor connected in series, one end of the first capacitor is grounded, the other end of the first capacitor is connected to the first resistor, the other end of the first resistor is an input voltage end of the RC module, and a connection point of the first resistor and the first capacitor is an output voltage end of the RC module.

4. The electrostatic discharge protection circuit of claim 1, wherein the alarm module comprises a first inverter;

and when the alarm voltage is greater than or equal to the output voltage of the RC module, the second input end of the first phase inverter is conducted with the output end of the first phase inverter, and the static alarm signal is output.

5. The ESD protection circuit of claim 4, wherein a ground terminal of the first inverter is connected to an output terminal of the first inverter when the alarm voltage is less than the output voltage of the RC module.

6. The electrostatic discharge protection circuit according to claim 1, wherein the discharge module includes a second inverter and a first switching unit;

the first input end of the second phase inverter receives the input voltage of the RC module, the second input end of the second phase inverter receives the output voltage of the RC module, and when the alarm voltage is greater than or equal to the output voltage of the RC module, the first input end of the second phase inverter is conducted with the output end of the second phase inverter;

the first input end of the first switch unit is connected with the output end of the second inverter, and when the output voltage of the second inverter is greater than the first switch voltage, the first switch unit is conducted to realize electrostatic discharge.

7. The electrostatic discharge protection circuit according to any one of claims 1-6, further comprising a pulse extension alarm module, wherein the pulse extension alarm module delays the electrostatic discharge alarm signal and outputs a delayed electrostatic discharge alarm signal having a duration longer than a duration of the electrostatic discharge alarm signal.

8. The electrostatic discharge protection circuit of claim 7, wherein the pulse extension alarm module comprises a second switch unit, a third switch unit, a second capacitor, and a third inverter;

the second switch unit is switched on when the first input end of the second switch unit receives the static warning signal, and is switched off when the first input end of the second switch unit does not receive the static warning signal;

the third switching unit is turned off when the first input end of the third switching unit receives the static electricity alarm signal, and is turned on when the first input end of the third switching unit does not receive the static electricity alarm signal;

the second capacitor is charged when the second switch unit is turned off and the third switch unit is turned on, and is discharged when the second switch unit is turned on and the third switch unit is turned off;

and a first input end of the third inverter receives the voltage of the second capacitor, and outputs the delay static warning signal when the voltage of the second capacitor is smaller than the pulse extension voltage.

9. The esd protection circuit of claim 8, wherein the second input terminal of the third inverter is connected to the input voltage terminal of the RC module, and the second input terminal of the second inverter is connected to the output terminal of the second inverter when the voltage of the second capacitor is smaller than the pulse spreading voltage.

10. The esd protection circuit of claim 9, wherein a ground terminal of the third inverter is connected to the output terminal of the third inverter when the voltage of the second capacitor is greater than or equal to the pulse-spreading voltage.

11. The ESD protection circuit of claim 8, wherein the third switching unit comprises n P-type transistors, n ≧ 2;

the grid electrode of the n P-type transistors receives the static electricity alarm signal, the drain electrode of the first-stage P-type transistor in the n P-type transistors receives the input voltage of the RC module, the source electrode of the previous-stage P-type transistor in the n P-type transistors is connected with the drain electrode of the adjacent next-stage P-type transistor, the source electrode of the nth-stage P-type transistor in the n P-type transistors is connected with the second capacitor, and the n P-type transistors are conducted when the static electricity alarm signal is larger than or equal to the first switch threshold value.

12. The esd protection circuit of claim 8, wherein the third switching unit comprises a P-type transistor;

the grid electrode of the P-type transistor receives the static electricity alarm signal, the drain electrode of the P-type transistor receives the input voltage of the RC module, the source electrode of the P-type transistor is connected with the second capacitor, and the P-type transistor is conducted when the static electricity alarm signal is larger than or equal to the first switch threshold value.

13. The esd protection circuit of claim 1, further comprising a processing module:

the processing module receives the static warning signal and responds to the static warning signal to execute at least one of a static discharge prevention method and a static discharge remediation method;

the static leakage prevention method comprises the steps of suspending a program currently executed by the processing module;

the static leakage remedying method comprises the step of retransmitting data sent by the processing module within a static leakage time interval after the alarm module stops outputting the static alarm signal, wherein the static leakage time interval is a time interval between the moment when the processing module receives the static alarm signal and the moment when the processing module stops receiving the static alarm signal.

14. A chip having an electrostatic discharge protection circuit, comprising an electrostatic discharge protection circuit according to any one of claims 1 to 13.