CN113678013A

CN113678013A - Power converter with inductively coupled parallel power stacks

Info

Publication number: CN113678013A
Application number: CN202080015655.XA
Authority: CN
Inventors: 约斯特·约翰·范斯特拉伦; 约书亚·特尔劳夫; N·J·H·斯拉亚特斯
Original assignee: Puzhuo Technology Innovation Service Co ltd
Current assignee: Puzhuo Technology Innovation Service Co ltd; Prodrive Technologies BV
Priority date: 2019-02-22
Filing date: 2020-02-21
Publication date: 2021-11-19
Also published as: WO2020169797A1; EP3928110A1; NL2022622B1

Abstract

A power converter (10) includes a first stack (131) and a second stack (132). The first stack and the second stack each comprise a plurality of controllable power switches (S1-S4) arranged in at least one full H-bridge and/or a plurality of half H-bridges (15). The H-bridges are connected in series within each stack. The first stack (131) and the second stack (132) are connected in parallel by an inductive component (14), in particular a coupled inductor. These controllable power switches are controlled by a pulse width modulation control schemeOperation, the pulse width modulation control scheme implements a modulation parameter (d)_com) The modulation parameters passing through first and second full H-bridges and/or half H-bridges (V) arranged at corresponding positions in the first (131) and second (132) stacks_H11，V_H21) Alternately add or subtract offset (d)_offset) To selectively adjust to allow control of differential mode current flowing between the first (131) and second (132) stacks.

Description

Power converter with inductively coupled parallel power stacks

Technical Field

The present invention relates to a power converter. In particular, the present invention relates to a multi-level power converter that overcomes problems associated with dead-time (dead-time) of transistor switching at low current levels. The power converter according to the invention is particularly suitable for use as an amplifier for driving gradient coils in a Magnetic Resonance Imaging (MRI) system.

Background

Gradient coils in an MRI system provide magnetic fields for performing imaging measurements. These gradient coils require high voltages and high currents that must be controlled. The voltage is typically about 2000V and above. The peak current required is about 600A and above. The quality and resolution of the image depends on the degree of accuracy of the magnetic field control. Therefore, a high accuracy of the current is required to prevent image artifacts.

The gradient amplifiers in an MRI scanner drive gradient coils, which typically have an inductance of several hundred muh to 1 mH. The gradient amplifier is constructed to drive the gradient coil to a specific magnetic field and usually comprises switching elements arranged in so-called switching branches, which together form an H-bridge. The switching element may be constituted by an IGBT switch with anti-parallel diodes or any other electronically controlled switch with parallel diodes may alternatively be used. These switches are controlled by a Pulse Width Modulation (PWM) scheme (e.g., unipolar or bipolar PWM) suitable for the H-bridge.

In addition to fast ramp up and ramp down currents, gradient amplifiers also need to generate bi-directional high voltages and currents. Because of this high voltage and current, high power components are required, limiting the switching frequency. For switching the required voltages and currents at high frequencies, it is known from US 2017/0045596 to use cascaded H-bridges. This allows the power demand to be distributed through the H-bridge. Furthermore, the number of effective switching frequencies and switching levels is increased. It is further known from US 2018/0231623 to couple two cascaded H-bridge inverter stacks in parallel by means of coupled inductors.

However, H-bridge topologies experience dead time (or blanking time) effects. Dead time refers to the time at which both the top and bottom switches (in other words: all switches of one branch) are commanded off. This dead time is increased to prevent the voltage source from shorting (breaking down) during the transition and to create a margin for cross conduction due to the on and off delay of the switch. Due to the margin required over the dead time, there is a moment when both the top and bottom switches of a single switching leg are closed. During this time, the output voltage of the H-bridge is determined by the sign of the current in each switching branch, since this determines which parallel diodes will conduct. This current dependent output voltage has a negative effect on the quality of the converter output signal. This effect also creates a dead band in the response of the output voltage/current to the varying control signal, particularly at low load currents. When a plurality of H-bridge units are used, the effect of dead time becomes greater since each H-bridge unit requires a certain dead time. Due to the dead zone at low output currents, the output current is difficult to control, the output quality is poor, and there is a large error between the load current and the reference signal.

US 2017/00445596 describes overcoming dead time effects by injecting a bias current in the centre of the switching legs of the H-bridge. The injected bias current forces the direction of current through the switch at low output current levels, resulting in well-defined switching transitions at these low currents. Thus, the dead time effect is shifted to higher positive and negative load currents, which effect is reduced and compensated for by the controller. One disadvantage of this approach is that each half H-bridge requires additional auxiliary circuitry. This increases the complexity of the hardware, the number of components, the probability of component failure and the cost of the amplifier.

Disclosure of Invention

It is an object of the present invention to provide a power converter having at least the same and advantageously improved performance as prior art power converters, in particular at low output current levels. It is an object of the present invention to achieve such equivalent or improved performance with less hardware and/or at a lower cost.

According to a first aspect of the present invention, there is therefore provided a power converter as set forth in the accompanying claims.

The power converter according to the invention comprises a first stack. The first stack comprises a plurality of controllable power switches arranged in one or more first H-bridges cascaded in series. The one or more first H-bridges may be at least one full H-bridge or a plurality of half H-bridges, or a combination of both.

According to the invention, the power converter comprises a second stack. The second stack comprises a plurality of controllable power switches arranged in one or more second H-bridges cascaded in series. The one or more second H-bridges may be at least one full H-bridge or a plurality of half H-bridges, or a combination of both. According to the invention, the first stack and the second stack are connected in parallel by inductive means. The inductive component may be implemented in various ways. In a particularly advantageous manner, the inductive component comprises at least one coupling inductor.

The power converter according to the invention allows to further reduce the dead time effect compared to the converter of US 2017/00445596, since it can shift the dead time effect of the power switch to even higher output current levels, wherein the operational problems are less. In addition, improved operating performance is achieved with less hardware, thereby reducing hardware complexity, which also reduces manufacturing costs.

The power converter includes a controller operably coupled to the plurality of controllable power switches of the first stack and the second stack. The controller is configured to operate the first full H-bridge and/or half H-bridge and the second full H-bridge and/or half H-bridge in an interleaved manner. This further allows increasing the number of voltage levels and the effective switching frequency, thereby reducing ripple. The controller is configured to operate the plurality of controllable power switches of the first stack and the second stack by a Pulse Width Modulation (PWM) scheme defining modulation parameters that set a common mode voltage level of the first stack and the second stack. Thus, the interleaving manner applied in the power converter of the invention is configured to adjust the modulation parameters, such as the duty cycle, applied to the first and second stacks as described herein. The modulation parameters are applied to the pulse width modulation control signal to adjust the output voltage of each H-bridge.

According to the invention, the PWM scheme implementation selectively adjusts the offset of the modulation parameter in the PWM control signals of the first and the second full H-bridge and/or half H-bridge, thereby allowing control of the differential mode current flowing between the first stack and the second stack. The PWM scheme is configured to selectively adjust the modulation parameter by alternately adding and subtracting the offset between first and second full H-bridges and/or half H-bridges disposed at corresponding positions in the first stack and the second stack. Such PWM schemes allow for non-zero circulating currents to be generated at switching events of the switches of the full H-bridge and/or the half H-bridge. As a result, dead time effects are eliminated or at least reduced in switching events and an improved soft switching behavior of the power converter is obtained.

According to a second aspect of the invention, there is provided a gradient amplifier for a magnetic resonance imaging apparatus, the gradient amplifier comprising a power converter according to the first aspect.

According to a third aspect of the invention, there is provided a magnetic resonance imaging apparatus comprising a gradient coil and a power converter according to the first aspect. The power converter is operatively coupled to the gradient coil.

According to a fourth aspect of the invention, there is provided a method of operating a power converter as claimed in the accompanying claims.

Further advantageous aspects are set out below and in the dependent claims.

Drawings

Aspects of the present invention will now be described in more detail, with reference to the appended drawings, wherein like reference numerals represent like features, and wherein:

fig. 1 shows a topology of a power converter according to the invention;

FIG. 2 illustrates a topology of a power stack used in the power converter of FIG. 1;

figure 3 shows a first embodiment of an inductive coupling between two parallel power stacks according to the invention;

FIG. 4 shows an equivalent circuit for the common mode current of the topology of FIG. 3;

FIG. 5 shows an equivalent circuit for the differential mode current of the topology of FIG. 3;

figure 6 shows a second embodiment of an inductive coupling between two parallel power stacks according to the invention;

FIG. 7 shows an equivalent circuit for the common mode current of the topology of FIG. 6;

FIG. 8 shows an equivalent circuit for the differential mode current of the topology of FIG. 6;

figure 9 shows a third embodiment of inductive coupling between two parallel power stacks according to the invention using coupled inductors;

fig. 10 shows the layout of the coupled inductors used in fig. 9 implemented with the aid of a transformer;

FIG. 11 shows an equivalent circuit of the coupled inductor of FIG. 10;

FIG. 12 shows an equivalent circuit for the common mode current of the topology of FIG. 9;

FIG. 13 shows an equivalent circuit for the differential mode current of the topology of FIG. 9;

FIG. 14 shows another topology of a power converter according to the invention;

FIG. 15 shows a block diagram of the power converter of FIG. 14;

fig. 16 shows a schematic diagram of a control structure for controlling the power converter of the present invention;

FIG. 17 shows a block diagram of a power stack of the power converter of FIG. 14;

fig. 18 shows a first PWM scheme embodiment of the power converter of fig. 14 showing the voltage levels of the H-bridge of the two power stacks, the output voltage, and the differential mode current circulating between the power stacks;

fig. 19 shows a second PWM scheme embodiment of the power converter of fig. 14, showing the voltage levels of the H-bridge of the two power stacks, the output voltage, and the differential mode current circulating between the power stacks;

FIG. 20 shows the modulation parameter d for three system architectures (prior art with and without injection of bias current as described in the background section above and architectures according to the present invention) in steady state_comGraphical visualization of soft switching regions of leading and trailing edges of PWM pulses. For simplicity, the pulse length is not related to d_comDrawn to scale, there are only rising and falling edges.

Detailed Description

Referring to fig. 1, one possible topology of a power converter according to the present invention comprises a power stage 11, and an output filter 12 coupled between the power stage 11 and a load 9. The power stage 11 comprises a pair of

power stacks

131, 132.

Referring in more detail to fig. 2, each

power stack

131, 132 of the power stage 11 of fig. 1 comprises a plurality of H-bridges 15. Each H-bridge 15 comprises power switches S1 to S4, such as IGBT switches, arranged in two switching

legs

151, 152. Each switching leg comprises two power switches connected in series. Diodes D1-D4 are coupled in anti-parallel with respective switches S1-S4. Alternatively, a half H-bridge may be used instead of the full H-bridge 15. Each H-bridge 15 is connected to a voltage source 16, in particular a DC voltage source, advantageously providing a stable bus voltage v_busThe isolated DC-DC converter of (1). The capacitor buffer 161 is advantageously coupled in parallel with the voltage source 16 to counter (counter) sudden power demands. The switches S1-S4 are advantageously controlled by a pulse width modulation scheme (e.g., unipolar or bipolar PWM) suitable for the H-bridge, as will be explained further below.

Each H-bridge 15 may be at-v_bus0V and + V_busSwitch its output voltage v between_snH. The H-bridges 15 within the power stack are cascaded such that HThe outputs of the bridge are connected in series between

output terminals

133 and 134. Cascading the H-bridges 15 within a

single power stack

131, 132 such that the outputs v of all H-bridges are connected_snH1...nAn output voltage v combined to the power stacks 131, 132, respectively_sn1、v_sn2. Power stack output voltage v_sn1、v_sn2Output range of-nv_busTo + nv_busIn increments of v_busWhere n is the number of cascaded H bridges.

Returning to fig. 1, the two

power stacks

131, 132 are coupled in parallel by the inductive component 14. Advantageously, each stack is configured to provide half the output power, so the power components required to obtain the output power can be distributed equally over the two stacks. During operation, these power stacks sometimes have the same output voltage, sometimes with a voltage difference. The difference in output voltage between the two

power stacks

131, 132 results in a circulating current i_diff(differential mode current) flows between the two power stacks. In order to generate a controlled current and maintain that current during switching, the inductive component 14 added between the power stacks 131, 132 will limit the rise and fall of the current in case of a voltage difference between the power stacks. In addition, the common mode current i is maintained when no voltage difference is applied_DM。

The inductive component 14 may be implemented in various ways. A first possible embodiment is shown in fig. 3. The inductive component comprises two

inductors

141, 142, which are symmetrically coupled between the

respective power stacks

131, 132 and the output terminal 111. Equivalent circuits for common mode current and differential mode current are shown in fig. 4 and 5, respectively.

A second possible embodiment is shown in fig. 6. The inductive component of fig. 6 differs from the inductive component of fig. 3 in that a third inductor 140 is coupled in parallel to the

inductors

141 and 142. By doing so, the inductance is reduced from the point of view of the differential mode. Equivalent circuits for common mode current and differential mode current are shown in fig. 7 and 8, respectively.

A third possible embodiment is shown in fig. 9, where the inductive component 14 is a coupled inductor. Coupled inductors generally refer to a pair of magnetically coupled inductors 141142, one terminal of which is short-circuited between each other. Fig. 10 shows a possible embodiment of the coupled inductors by means of a transformer. The inductor 141 forms a primary winding and the inductor 142 forms a secondary winding, which are magnetically coupled through a transformer core 148. One terminal 144 of the primary winding 141 and one terminal 146 of the secondary winding 142 are electrically connected to each other and to the output terminal 147. Fig. 11 shows an equivalent circuit of the coupled inductor of fig. 10, where L refers to the inductance of the primary winding, which is advantageously the same as the inductance of the secondary winding, and

l refers to the mutual inductance. Equivalent circuits for common mode current and differential mode current are shown in fig. 12 and 13, respectively. In common mode there is only leakage inductance L_leakOccurs, while in the differential mode only the magnetizing inductance L_maVisible by differential current.

By coupling the two power stacks in parallel through inductive components, a topology is obtained that is able to circulate current through the power stacks without affecting the output current or voltage. Therefore, when outputting the current i_DMWhen it has to become low, current i_diff"cycling" between the power stacks 131 and 132 ensures well-defined switching transitions. In addition, by taking v_sn1And v_sn2The number of switching levels can almost double to 4n + 1.

The operation of the power stacks 131, 132 is also advantageously staggered, resulting in an output voltage v_snThe effective switching frequency of (a) is doubled.

Referring to fig. 14, an alternative power stage 21 is depicted which differs from the power stage 11 of fig. 1 in that a second inductive component 24 is added in the loop of the power stack 131 and the power stack 132. The inductive component 14 is coupled between the upper output terminals of the power stacks 131, 132, while the second inductive component 24 is coupled between the lower output terminals of the power stacks. In contrast, in fig. 1, the lower output terminals of the power stacks 131, 132 are connected to ground. The

inductive components

14 and 24 may be identical.

Output voltages applied at output terminals 110-111 of power stages 11 and 21v_snAdvantageously filtered by an output filter 12 before being applied to the load 9. The output filter 12 may be a passive second order LC low pass filter. This results in a smooth output voltage v applied to the load 9_out。

Referring to fig. 15, the power converter 10 includes a controller 17. The controller 17 is operatively connected to the H-bridge 15 of each

power stack

131, 132. Advantageously, the power switches S1-S4 of each H-bridge are controllable power switches, and their operation is controlled by a controller 17, which advantageously implements a PWM scheme, in particular by a unipolar PWM scheme. The controller may further be coupled to the output filter 12, for example for measuring the output current and/or the output voltage of the

power stage

11, 21. Alternatively or additionally, a voltage and/or current sensor 171 may be provided at the output of the power converter and coupled to the controller 17.

Power converter 10 may include an AC-to-DC converter 18 coupled to an external power source to receive power. The AC to DC converter supplies power to an isolated DC-DC converter 16.

The controller 17 advantageously operates the power switches of the H-bridge 15 so as to interleave the outputs of the power stacks 131 and 132. This increases the number of switching levels and the effective switching frequency.

The controller 17 advantageously implements a PWM scheme for operating the power switches S1-S4 of the H-bridge 15. The PWM scheme is advantageously based on unipolar pulse width modulation. Each H-bridge 15 of the power stacks 131, 132 advantageously has its own PWM carrier. These PWM carriers may have the same waveform but may be phase shifted. An advantageous PWM scheme implements the modulation parameters d of the power stacks 131, 132, respectively_AAnd d_B. These modulation parameters may refer to the duty cycle of the PWM scheme. This means that the output voltages of the power stacks 131, 132 may be defined as V, respectively_H1＝d_Anv_busAnd VH₂＝d_Bnv_busWherein v is_busIs the output voltage of the DC-DC converter 16 and n is the number of cascaded H-bridges 15 within the power stack, where n is an even number or advantageously an odd number.

In one possible control embodiment of the controller 17The power stacks 131, 132 are considered as voltage sources, e.g. as described in the previous paragraph, which are integrated in the state space model of the power stage and the output filter. Such a state space model may have a modulation parameter d_AAnd d_BAs input and current i as defined in fig. 1_loadAnd i_diffAs an output. In an alternative control embodiment, the modulation parameter is redefined as d_A＝d_com+d_diffAnd d_B＝d_com-d_diff. It can be seen that by doing so, the parameter d is modulated_comCan be used to control the output current i_loadAnd d is_diffCan be used to control the circulating current (differential mode current) i_diff。

Referring to fig. 16, the controller 17 may implement a control scheme 170 including a feedback loop controller 173 for example based on the pair i via, for example, sensor 171_loadTo control the reference current i to be applied to the load 9_ref. The feedback loop controller 173 advantageously provides d_comTo the reference value of (c).

Advantageously, the control scheme 170 comprises a second controller 174 for regulating the modulation parameter d_diffTo control the circulating current i_diff. The second controller 174 is configured to ensure that i_diffRemain within the boundaries to prevent damage to the power stack and inductive components. The second controller may use a current i based on the cycle_diffA classical control strategy of measured and/or estimated values of (a). For example, the second controller 174 may determine the circulating current i_diffAnd the modulation parameter d is adjusted accordingly_diff。

Modulation parameter d output from

controllers

173, 174_comAnd d_diffIs fed to the PWM module 175 which generates PWM control signals which are applied to the power switches S1-S4 of the H-bridge 15 of the power stacks 131, 132.

By modulating the parameter d_comTo regulate the output voltage v_snThe voltage level of (c). For example, the modulation parameter d_comMay for example be set between-1 and +1And (4) changing. This means that when d_comWhen set to 0, v_snWill also be 0; when d is_comWhen set to 0.5, v_snWill be set to half the maximum output voltage, etc.

Advantageously, the PWM module 175 directs d to each H-bridge 15_comImplementing an offset d_offsetTo allow for the addition of a modulation parameter d_diffIn addition or as an alternative to controlling the circulating current (differential mode current) i flowing between the two

power stacks

131 and 132_diff。

Advantageously, the offset parameter d_offsetWith a fixed value. Advantageously, d _offset1/(2 × n), where n is the number of cascaded h-bridges. This allows the desired amount of interleaving to occur.

Alternatively, d_offsetMay be variable, e.g. it may depend on the modulation parameter d_comOr it may depend on the amplitude of the circulating current. Advantageously, the offset d_offsetIs dependent on the modulation parameter d_com. For example, offset d_offsetIs selected such that d_comAnd d_offsetThe sum of which never exceeds 1 in absolute value. This is at d_comAre particularly relevant at the boundaries of (e.g., near the range limits +1 and-1). At d_comAt the limit of the range of, e.g., d_comAt +1 and-1, offset d_offsetAdvantageously zero. For example, at d_comWhen it is between-1 + x and +1-x, d_offsetMay have a constant value x, and at d_comGradually decreases towards 0 in the range between-1 and-1 + x and +1-x to +1, so that the sum of the two never exceeds 1 in absolute value. Advantageously, x ═ 1/(2 ×) as defined above allows the effective switching frequency to be doubled.

Also can make d_offsetIs changed between H-bridges (referred to as H-bridge pairs) arranged at corresponding positions in the two

power stacks

131 and 132, i.e. different offsets (amplitudes) are applied to the two H-bridges within an H-bridge pair. Alternatively or additionally, d may also be_offsetIs changed between H-bridges of the

same power stack

131, 132.

Advantageously, the offset d is varied in a time-varying manner_offsetApplication to d_com. Advantageously, the offset d_offsetIn an opposite manner to the corresponding H-bridge of the two

power stacks

131, 132, in particular by applying d to one H-bridge_offsetAnd d_comAdd, and slave d for the corresponding H-bridge of the other power stack_comMinus d_offset. To this end, each of the two power stacks advantageously comprises an equal and advantageously odd number of cascaded H-bridges. Alternatively, the offset d_offsetMay be applied to each H-bridge 15 according to the PWM carrier. During the ramp-up of the PWM carrier, the offset d_offsetMay be positive and the offset d during the ramp down of the PWM carrier of the corresponding H-bridge_offsetMay be negative but may be equal in magnitude.

In one example embodiment, the corresponding H-bridge 15 between the two

power stacks

131 and 132 is considered to form an H-bridge pair, as shown in fig. 17. The H-bridge is schematically drawn as a source V of a first power stack 131_H11-V_H1nAnd source V of the second power stack 132_H21-V_H2n. First H bridge V_H11And V_H21Considered as a first pair, a second H bridge V_H12And V_H22Considered as a second pair, and so on. The offset d_offsetAdvantageously applied in a complementary manner to each pair (V)_H11，V_H21)、(V_H12，V_H22)、…、(V_H1n，V_H2n). For example, for V_H11Offset d_offsetIs added to d_comAnd at the other H-bridge V of the pair_H21From d_comMinus an offset d_offset. Thus, the resulting application to V_H11The modulation parameters are: d_VH11＝d_com+d_offsetAnd the resulting application to V_H21The modulation parameters are: d_VH21＝d_com-d_offset. In addition, offset d_offsetAdvantageously alternating between different H-bridge pairs. In addition, however, after each cycle, the offset advantageously crosses between H-bridges within the same pairAnd (4) replacing. This can be achieved when the PWM carriers are properly interleaved between a pair of H-bridges (e.g., they are phase shifted by 180 ° between a pair of H-bridges when the same PWM carrier is used), and offset d_offsetWhether positive or negative depends on whether the PWM carrier is ramping up or ramping down, respectively.

Fig. 18 and 19 show the output and resulting circulating current of different H-bridges of two exemplary embodiments of the present invention. In fig. 18, n is 5, d_com0 and d_offset0.1. In fig. 19, n is 5, d_com0.05 and d_offset0.1. As can be seen in FIG. 18, v is not_snWith a voltage applied thereto and a circulating current i_diffCycling between stacks. As can be seen in FIG. 19, v_snEffective switching frequency of (v) relative to v_sn1And v_sn2Is doubled, while at v_snThere is a voltage ripple equal to half the bus voltage.

One of the main advantages of the present invention is apparent from the accompanying drawings. As can be seen from fig. 18 and 19, the circulating current (differential mode current) i_diffAnd greater at low output voltage levels. In addition, at the switching instant of the bridge, a circulating current i_diffIs non-zero. The switching instants are indicated by the vertical dashed lines in fig. 18 and 19, and it can be seen that these dashed lines intersect i at a non-zero value_diffAnd (4) intersecting. As a result, dead time effects are eliminated or at least reduced, particularly at low output current values. This results in well-defined soft switching behavior at these low output current levels. Another effect of the PWM scheme of the present invention can be seen in FIGS. 18 and 19, i.e., i_diffAt v_diffIs negative at v_diffIs positive at the falling slope of (a).

The magnitude of the circulating current may be further influenced by the inductance L of the coupled inductor_maThe influence of (c). By appropriate selection of the inductance L_maIt can be realized that when modulating the parameter d_comAt zero, the circulating current is sufficiently large.

Applying an offset d_offsetPossibly making the modulation parameter d_diffBecomes redundant and the modulation parameter becomes redundantMay not be implemented. Alternatively, the parameter d is modulated_diffAdvantageously set to 0 in "normal" operating conditions and adjusted only when a fault condition occurs, in particular when the circulating current drifts during dynamic behaviour, for example circulating current i_diffExceeds a predetermined threshold. Modulation parameter d_diffMay be adjusted to return the average circulating current to zero.

By implementing the PWM scheme as above, it is observed that even when the parameter d is modulated_comA well-defined soft switching transition also occurs at 0 (see fig. 18). Furthermore, the power converter of the present invention allows for a reduction of ripple on the output current and voltage due to the increase of the effective switching frequency and due to the additional switching levels generated by the cascaded dual power stack topology.

Referring to fig. 20, a comparison of the soft switching behavior of a PWM scheme according to the present invention is visually represented with two prior art power converter architectures: the first was named 'original' as described in US 2017/0045596, but without bias current injection, and the second was named 'original + BCI', with bias current injection as described in US 2017/0045596. It can be seen that well-defined soft switching behavior occurs over a wider range of output currents compared to prior art architectures, but in particular in the currently proposed PWM schemes there is well-defined soft switching of the rising and falling edges at low output currents.

It may be conveniently noted that the present invention contemplates a power converter comprising more than two stacks coupled in parallel by inductive components such as coupled inductors. In this case, the inductive component may comprise an inductive element for each stack, and the inductive elements are inductively coupled to each other.

Claims

1. A power converter (10) comprising:

a first stack (131) comprising a plurality of controllable power switches (S1-S4) arranged in at least one first full H-bridge and/or a plurality of first half H-bridges (15), the at least one first full H-bridge and/or the plurality of half H-bridges being connected in series,

a second stack (132) comprising a plurality of controllable power switches (S1-S4) arranged in at least one second full H-bridge and/or a plurality of second half H-bridges (15), the at least one second full H-bridge and/or the plurality of half H-bridges being connected in series, wherein the first stack (131) and the second stack (132) are connected in parallel by an inductive component (14),

a controller (17) operably coupled to the plurality of controllable power switches (S1-S4) of the first stack and the second stack, wherein the controller is configured to operate the first full H-bridge and/or half H-bridge (15) and the second full H-bridge and/or half H-bridge in an interleaved manner,

wherein the controller (17) is configured to operate the plurality of controllable power switches (S1-S4) of the first and second stacks by a pulse width modulation scheme defining a common mode voltage level (v) setting the first and second stacks_sn) Modulation parameter (d)_com)，

Characterized in that the pulse width modulation scheme implements an offset (d)_offset) By means of the first and the second full H-bridge and/or half H-bridge (V) arranged at corresponding positions in the first stack (131) and the second stack (132)_H11，V_H21) Alternately add or subtract the offset (d)_offset) Selectively adjusting a modulation parameter (d) in a pulse width modulation control signal of the first and the second full H-bridge and/or half H-bridge (15)_com) Thereby allowing control of differential mode current flowing between the first stack (131) and the second stack (132).

2. The power converter of claim 1, wherein the inductive component is coupled between the first stack (131) and the second stack (132) to allow a common mode current (i) to be output from the first stack (131) and the second stack (132)_DM) And cycling the differential mode current (i) between the first stack and the second stack_diff)。

3. A power converter as claimed in claim 1 or 2, wherein the electricity isThe sensing component comprises a pair of inductors (141, 142), wherein each inductor of the pair of inductors is connected in series with the respective first and second stacks, and wherein a common mode current (i) output from the first (131) and second (132) stacks_DM) Is drawn from a point midway between the pair of inductors.

4. A power converter as claimed in claim 3, comprising a third inductor (140) connected in parallel to the pair of inductors (141, 142).

5. A power converter according to any of the preceding claims, wherein the inductive component (14) comprises a first coupled inductor connected to the first stack (131) and the second stack (132).

6. A power converter according to any of the preceding claims, wherein the pulse width modulation scheme is configured to add or subtract the offset (d) alternately during ramp up and ramp down of the pulse width modulation control signal of the respective first or second H-bridge, respectively (d)_offset) To selectively adjust the modulation parameter (d)_com)。

7. A power converter according to any preceding claim, wherein the inductive component comprises a second coupled inductor (24) connected between the first stack (131) and the second stack (132) at an opposite terminal (133) compared to the first coupled inductor (14).

8. A power converter as claimed in any preceding claim comprising an upper intermediate terminal (111) and a lower intermediate terminal (110), wherein the inductive component is connected to the upper intermediate terminal (111) and optionally to the lower intermediate terminal (110), and wherein the power converter comprises an output filter (12) coupled to the upper intermediate terminal and the lower intermediate terminal.

9. A power converter according to any of the preceding claims, wherein each of the first and the second full and/or half H-bridges (15) is connected to a voltage source (16).

10. A power converter as claimed in claim 9, wherein the voltage source (16) is an isolated DC/DC converter.

11. A gradient amplifier for a magnetic resonance imaging apparatus, the gradient amplifier comprising a power converter according to any one of the preceding claims.

12. A magnetic resonance imaging apparatus comprising a gradient coil and a power converter as claimed in any one of the preceding claims, wherein the power converter is operatively coupled to the gradient coil.

13. A method of operating a power converter (10), the method comprising:

arranging a plurality of controllable power switches (S1-S4) in a plurality of full H-bridges and/or half H-bridges (15) cascaded in series in two parallel stacks (131, 132), each stack comprising at least one full H-bridge and/or half H-bridge, wherein the parallel stacks are connected by inductive means (14, 24), and

operating the plurality of controllable power switches (S1-S4) to provide a common mode current (i) output from the two parallel stacks (131, 132)_DM) And a differential mode current (i) circulating between the two parallel stacks_diff)，

Wherein the controllable power switches (S1-S4) of the plurality of full H-bridges and/or half H-bridges are operated by pulse width modulation to obtain an interleaved operation of the plurality of full H-bridges and/or half H-bridges (15) between the two parallel stacks (131, 132),

wherein the pulse width modulation is according to a defined modulation parameter (d)_com) The modulation parameter sets a common mode voltage level (v) of the two parallel stacks (131, 132)_sn) Wherein the control scheme implements an offset (d)_offset) By being inAn H-bridge (V) of the plurality of full H-and/or half H-bridges arranged at corresponding positions in the two parallel stacks (131, 132)_H11，V_H21) Alternately add or subtract the offset (d)_offset) Selectively adjusting modulation parameters applied to the plurality of full H-bridges and/or half H-bridges (d)_com) Thereby controlling a differential mode current (i) flowing between the two parallel stacks (131, 132)_diff)。