CN113676380B - Switch port testing method, electronic equipment and system - Google Patents
Switch port testing method, electronic equipment and system Download PDFInfo
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- H04L43/00—Arrangements for monitoring or testing data switching networks
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Abstract
The invention provides a method, electronic equipment and a system for testing ports of a switch, which are applied to a switch to be tested, wherein each port of the switch to be tested is configured with a loop back device, and the method comprises the following steps: generating original test data; sending original test data to a test loop chain through an initial port of the test loop chain, so that the original test data are sequentially forwarded among N ports to be tested contained in the test loop chain, wherein the test loop chain is obtained by configuring the N ports to be tested of the switch to be tested according to preset parameters; controlling an initial port of a testing loop chain to stop forwarding data according to preset testing time, obtaining the quantity accumulated value of data packets forwarded by N ports to be tested, and judging whether N ports to be tested in the testing loop chain have faults or not according to the quantity accumulated value of the data packets forwarded by the N ports to be tested, so that the purpose of testing the reliability of ports of the switch without a testing machine is achieved.
Description
Technical Field
The present invention relates to the field of switch technologies, and in particular, to a method, an electronic device, and a system for testing a switch port.
Background
With the rapid development of high-speed signals, the single-port rate of a switching chip is higher and higher, the bandwidth is larger and larger, and the service port density of a switch product is higher and higher. Switch equipment manufacturers invest large amounts of resources in throughput and reliability coverage testing for each service port.
In the prior art, an external streaming instrument is generally used to perform a port streaming test on a switch port, so as to detect whether port communication is normal.
However, the existing method for detecting the switch port needs to rely on resources of a flow meter, and when a tester cannot be provided in a test field, the reliability test of the switch port cannot be realized.
Disclosure of Invention
The invention provides a method, electronic equipment and a system for testing ports of switches, and provides a method for testing the reliability of the ports of the switches without a testing machine.
In a first aspect, the present invention provides a method for testing a switch port, which is applied to a switch to be tested, where each port to be tested of the switch to be tested is configured with a loopback apparatus, and the method includes:
generating original test data;
sending the original test data to a test loop chain through an initial port of the test loop chain, so that the original test data are sequentially forwarded among N ports to be tested contained in the test loop chain, wherein the test loop chain is obtained by configuring the N ports to be tested of the switch to be tested according to preset parameters, and N is a positive integer greater than or equal to 2;
controlling an initial port of the test loop chain to stop forwarding data according to preset test time, acquiring the quantity accumulated value of data packets forwarded by the N ports to be tested, and judging whether the N ports to be tested in the test loop chain have faults or not according to the quantity accumulated value of the data packets forwarded by the N ports to be tested
In one possible design, the preset parameters include initial parameters, network configuration parameters, and network topology parameters, and before the sending the original test data to the test ring chain through the initial port of the test ring chain, the method further includes:
carrying out initialization configuration on the N ports to be tested according to the initial parameters;
configuring the port identification of each port according to the network topology parameters, configuring the VLAN forwarding configuration corresponding to each port according to the network configuration parameters, and determining the data forwarding sequence of the N ports according to the port identification of each port and the VLAN forwarding configuration.
In one possible design, the network topology parameter lists the port identifier of the upstream port and the port identifier of the downstream port corresponding to each network port.
In one possible design, the generating raw test data includes:
acquiring a minimum frame length corresponding to the full-load line speed of the switch to be tested and a time delay parameter corresponding to the port to be tested;
and determining the number of bytes of a data frame contained in the test data packet according to the minimum frame length, and determining the number of data packets contained in the original test data to be injected into a single port according to the time delay parameter and the number of bytes of the data frame.
In a possible design, the determining whether there is a failure in the N ports to be tested in the test ring chain according to the accumulated value of the number of data packets forwarded by the N ports to be tested includes:
acquiring the number accumulated value of the data packets forwarded by the N ports to be tested;
if the cumulative number of the data packets forwarded by the N ports to be tested is inconsistent, determining that a packet loss transmission fault exists in at least one port of the N ports to be tested;
and if the forwarding data packets of the N ports to be tested are completely consistent, judging that all the ports to be tested are normal.
In a possible design, before the controlling, according to the preset test time, the initial port of the test ring chain to stop forwarding data, the method further includes:
and if the data forwarding amount of any port to be tested is monitored to be zero, judging that at least one port of the N ports to be tested has a current-cutoff fault.
In a possible design, after determining whether there is a failure in the N ports under test in the test ring chain according to the cumulative value of the number of packets forwarded by the N ports under test, the method further includes:
and sequentially acquiring the number accumulated value of the forwarding data packets of the N ports to be tested, and determining the port identification of the port with the fault according to the number accumulated value of the forwarding data packets of each port to be tested.
In a second aspect, the present invention provides a switch port testing system, which includes a switch to be tested and N loopback apparatuses;
the switch to be tested is specifically used for implementing the switch port testing method according to the first aspect and various possible designs of the first aspect;
the N loop devices are respectively installed on N ports to be tested of the switch to be tested and are specifically used for realizing self-circulation of data sending and data receiving of the ports to be tested.
In a third aspect, the present invention provides an electronic device comprising: at least one processor and a memory;
the memory stores computer-executable instructions;
the at least one processor executing the computer-executable instructions stored by the memory causes the at least one processor to perform the switch port testing method as described above in the first aspect and various possible designs of the first aspect.
In a fourth aspect, the present invention provides a computer storage medium having stored therein computer executable instructions that, when executed by a processor, cause the at least one processor to perform the switch port testing method as set forth in the first aspect and various possible designs of the first aspect.
According to the switch port testing method, the electronic equipment and the system, the loop-back device is arranged at each port of the switch to be tested, so that original test data can be sequentially forwarded among N ports to be tested contained in the test loop chain, continuous cyclic testing of the test data among a plurality of ports of the switch is realized, a tester does not need to be additionally provided, and the purpose of testing the reliability of the ports of the switch can be realized.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a switch port test system according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a switch port provided in an embodiment of the present invention;
fig. 3 is a first flowchart illustrating a method for testing a port of a switch according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a test loop structure according to an embodiment of the present invention;
fig. 5 is a schematic flow chart of a switch port testing method according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a switch port testing apparatus according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
With the rapid development of high-speed signals, the single-port rate of a switching chip is higher and higher, the bandwidth is larger and larger, and the service port density of a switch product is higher and higher. Before a switch is delivered and delivered to a user for use, a port streaming test is usually performed to check whether port communication is normal, including whether normal forwarding is possible and whether a line speed streaming packet is lost. In the prior art, a port tapping test is usually performed on a switch port by using an external tapping instrument. However, the existing method for detecting the switch port needs to rely on resources of a streaming instrument, and when a tester cannot be provided in a test field, the reliability test of the switch port cannot be realized.
In order to solve the above technical problems, an embodiment of the present invention provides the following technical solution, where a loopback device is disposed at each port of a switch to be tested, so that original test data can be sequentially forwarded among N ports to be tested included in a test loop chain, thereby implementing a continuous loop test of the test data among multiple ports of the switch, and achieving a purpose of testing the reliability of the ports of the switch without additionally providing a tester. The following examples are given for the purpose of illustration.
Fig. 1 is a schematic structural diagram of a switch port test system according to an embodiment of the present invention. As shown in fig. 1, the switch port testing system provided in the embodiment of the present invention includes a switch to be tested and N loopback devices, where the switch to be tested can implement the switch port testing method provided in the present invention, and the N loopback devices are respectively installed on N ports to be tested of the switch to be tested, and are specifically used for implementing self-loop of data transmission and data reception of the ports to be tested.
Fig. 2 is a schematic structural diagram of a switch port according to an embodiment of the present invention, and exemplarily, as shown in fig. 2, a chip of a switch to be tested may be a BCM56780 switching chip. The switch product comprises 32 four-channel QSSF56 (Quad Small Form-factor plug, QSFP) interface ports, loop devices are mounted on 32 ports to be tested of the switch, and a Loopback loop module is connected to each specific QSFP56 port and used for setting a data sending TX interface and a data receiving RX interface of the ports to Form self-loops for sending and receiving data.
Fig. 3 is a schematic flow chart of a method for testing a port of an exchange according to an embodiment of the present invention, where an execution main body of the embodiment may be the exchange to be tested in the embodiment shown in fig. 1. On the basis of the switch provided by fig. 1, a loop back device for realizing data transmission and data reception self-circulation is installed at each port to be tested. Specifically, as shown in fig. 3, the method for testing a switch port according to the embodiment of the present invention includes the following steps:
s301: raw test data is generated.
In the embodiment of the present invention, in order to implement continuous forwarding of test data among multiple ports, the test data needs to satisfy full data transmission performance of the ports. Illustratively, acquiring a minimum frame length corresponding to a full-load linear speed of a switch to be tested and a time delay parameter corresponding to a port to be tested; and determining the number of bytes of a data frame contained in the test data packet according to the minimum frame length, and determining the number of data packets contained in the original test data to be injected into a single port according to the time delay parameter and the number of bytes of the data frame.
Specifically, the minimum frame length corresponding to the BCM56780 switch chip when the maximum full load of the port line speed can be reached is 364 bytes, and a packet with a frame length larger than 364 bytes is selected. Illustratively, the calculation formula for determining the byte length of a data frame according to the minimum frame length is shown as (1):
wherein line _ rate is the line speed, and pa _ length is the minimum frame length.
Illustratively, the QSFP56 port forwards approximately 48449612 packets per second to achieve 200Gbps line speed, taking a 512 byte frame as an example.
The latency is the time delay required by the data frame, and the unit of latency required in the formula is converted into seconds.
Wherein the value of n is shown in formula (3):
illustratively, the number of packets included in the original test data to be injected into a single port is determined according to the delay parameter and the number of bytes of the data frame. Specifically, as shown in formula (2):
illustratively, the larger the Latency, the more the data packets n should be injected to reach the linear speed of a single port, and according to the delay characteristic of the BCM56780 chip, taking the frame length of 512 bytes as an example, to reach the linear speed to the maximum extent, the maximum Latency 1040ns is taken, and n is calculated to be about 50.
Illustratively, the loop chain to be tested is composed of N ports to be tested, and the initial number M of packets corresponding to the ports to be tested when forwarding full-load data is N times of the number of packets required by a single port. Specifically, as shown in formula (4):
M＝n*N (4)
fig. 4 is a schematic diagram of a test loop chain structure according to an embodiment of the present invention. Illustratively, the ring chain to be tested consists of three ports to be tested, namely a QSFP56 (1) port, a QSFP56 (2) port and a QSFP56 (4) port, namely, the number M of the data packets is 150.
S302: the method comprises the steps that original test data are sent to a test loop chain through an initial port of the test loop chain, so that the original test data are sequentially forwarded among N ports to be tested contained in the test loop chain, wherein the test loop chain is obtained by configuring the N ports to be tested of a switch to be tested according to preset parameters, and N is a positive integer greater than or equal to 2.
In the embodiment of the invention, the snake-shaped test loop chain can be obtained by configuring Virtual Local Area Network (VLAN) Network parameters of a plurality of ports to be tested. Illustratively, QSFP56 (1) port, QSFP56 (2) port and QSFP56 (4) port in BCM56780 switch chip are selected, QSFP56 (1) port is configured as initial port. And obtaining a ring port topological structure by configuring the VLAN network parameters of the 3 test ports. Optionally, the positions of the ports to be tested included in the test loop chain may be randomly selected, and the number of the ports to be tested is a positive integer greater than or equal to 2, that is, one test loop chain at least includes two ports to be tested.
After a test loop chain of a ring port topological structure is obtained, each port to be tested is provided with a loop back device capable of carrying out data self-circulation transmission, so that the test data can be continuously and circularly forwarded in the test loop chain. For example, in the test loop chain provided by the QSFP56 (1) port, the QSFP56 (2) port and the QSFP56 (4) port, by sending the original test data to the test loop chain through the QSFP56 (1) port, the original test data is circularly forwarded according to the sequence of the QSFP56 (1) port, the QSFP56 (2) port and the QSFP56 (4), a continuous circular test of the data in the test loop chain is realized.
Illustratively, raw test data is sent to the commands employed in the test loop chain through the QSFP56 (1) port as follows:
#CPU send initial packets to QSFP56(1)ports，which is the first port of the test loop；
tx 150pbm＝cd0 Length＝512Untagged＝yes DestMac＝0x2
SourceMac＝0x1'；
s303: controlling an initial port of the test loop chain to stop forwarding data according to preset test time, obtaining the accumulated value of the quantity of data packets forwarded by the N ports to be tested, and judging whether the N ports to be tested in the test loop chain have faults or not according to the data forwarding quantity of the N ports to be tested.
In the embodiment of the present invention, the preset test time is set to 60S, for example. After the preset test time, the default original test data is subjected to multiple times of cycle tests in the test loop chain, and the test result of the test loop chain can be determined according to the accumulated value of the number of the data packets forwarded by the N ports to be tested.
Illustratively, before controlling an initial port of the test loop chain to stop forwarding data according to preset test time, if it is monitored that the data forwarding amount of any port to be tested is zero, it is determined that a cutoff fault exists in at least one port of the N ports to be tested. Before actively interrupting the streaming test loop chain, checking whether any port to be tested still forwards data, and judging whether the data forwarding is interrupted accidentally in the test process. If the data packet is not forwarded at any port to be tested before the streaming test loop chain is interrupted actively, and the test loop chain is disconnected in the test process, it is judged that the cutoff transmission fault exists at least one port to be tested in the N ports to be tested, and the first port to be tested, of which the cumulative number of the received and transmitted data packets is reduced obviously, is determined as the cutoff fault port.
Illustratively, after the initial port of the test loop chain is controlled to stop forwarding data according to the preset test time, that is, after the test of breaking the flow test loop chain is interrupted, whether the N ports to be tested in the test loop chain have a fault or not can be determined by the accumulated value of the number of data packets forwarded by the N ports to be tested. Specifically, if the accumulated values of the number of the data packets forwarded by the N ports to be tested are inconsistent, it is determined that a packet loss transmission fault exists in at least one port of the N ports to be tested; and if the accumulated values of the number of the data packets forwarded by the N ports to be tested are completely consistent, judging that the N ports to be tested are normal. Specifically, if no cutoff fault occurs and the accumulated value of the number of data packets between the N ports to be tested is different, it is determined that a packet loss transmission fault exists in at least one port of the N ports to be tested, and the packet loss transmission fault port is a port to be tested whose accumulated number of the number of data packets is less than the accumulated number of data packets of the upstream port to be tested. And if the forwarding data packets of the N ports to be tested are completely consistent, judging that all the ports to be tested are normal.
According to the switch port testing method provided by the embodiment, the loop-back device is arranged at each port of the switch to be tested, so that the original test data can be sequentially forwarded among the N ports to be tested contained in the test loop chain, the continuous cycle test of the test data among a plurality of ports of the switch is realized, a tester does not need to be additionally provided, and the purpose of testing the reliability of the ports of the switch can be realized.
In a possible implementation manner, after judging whether the N ports to be tested in the test loop chain have faults according to the accumulated value of the number of the data packets forwarded by the N ports to be tested, sequentially acquiring the accumulated value of the number of the forwarded data packets of the N ports to be tested, and determining the port identifier of the port with the faults according to the accumulated value of the number of the forwarded data packets of each port to be tested.
In the embodiment of the present invention, if it is determined that N ports to be tested in the test loop chain have a fault, the port having the fault may be determined according to the number of forwarding packets of each port to be tested. When judging that a test loop chain consisting of the QSFP56 (1) port, the QSFP56 (2) port and the QSFP56 (4) port has packet loss transmission faults or current-cut transmission faults, monitoring the number of data packets received by the QSFP56 (1) port, the QSFP56 (2) port and the QSFP56 (4) port in sequence, and determining the failed port. Specifically, the original test data includes 50 data packets, and the comparison relationship between the number of the data packets received by the QSFP56 (1) port, the QSFP56 (2) port, and the QSFP56 (4) port is monitored in sequence as follows: if the number of the data packets at the QSFP56 (1) port is greater than that at the QSFP56 (2) port, and the number of the data packets at the QSFP56 (2) port is equal to that at the QSFP56 (4) port, it can be determined that a packet loss transmission fault exists at the QSFP56 (2) port.
The switch port testing method provided in this embodiment provides a specific implementation method for determining a failed port by sequentially obtaining the number of forwarded data packets of each port to be tested, thereby implementing a reliability test of each port to be tested.
Fig. 5 is a schematic flowchart of a switch port testing method according to an embodiment of the present invention. In the embodiment of the present invention, the preset parameters include initial parameters, network configuration parameters, and network topology parameters, and on the basis of the embodiment provided in fig. 3, a specific implementation method is described in detail before the original test data is sent to the test loop chain through the initial port of the test loop chain in S302. As shown in fig. 5, the method includes:
s501: and carrying out initialization configuration on the N ports to be tested according to the initial parameters.
Illustratively, the initial parameters are all set to be null values, that is, the N ports to be tested are subjected to emptying configuration. Specifically, on the basis of the BCM56780 switching chip provided in the embodiment of the present invention, the command for performing initialization configuration on the N ports to be tested is as follows:
#vlan clear all；
#vlan remote 1pbm＝all。
s502: configuring the port identification of each port according to the network topology parameters, configuring the VLAN forwarding configuration corresponding to each port according to the network configuration parameters, and determining the data forwarding sequence of the N ports according to the port identification of each port and the VLAN forwarding configuration.
In the embodiment of the invention, for example, a QSFP56 (1) port, a QSFP56 (2) port and a QSFP56 (4) port in the BCM56780 switch chip are selected as ports to be tested. Specifically, the port identifier of each port is configured according to the network topology parameters as follows:
QSFP56 1：cd0
QSFP56 2：cd1
QSFP56 4：cd3
illustratively, the VLAN forwarding configuration is a port default VLAN. Exemplarily, and configuring the VLAN forwarding configuration corresponding to each port according to the network configuration parameters, as follows:
#QSFP56 1：
pvlan set cd0 100；
#QSFP56 2：
pvlan set cd1 101；
#QSFP56 4：
pvlan set cd3 103。
after default VLANs of ports corresponding to the QSFP56 (1) port, the QSFP56 (2) port and the QSFP56 (4) port are configured, the data forwarding sequence of the N ports is determined according to the port identification of each port and the VLAN forwarding configuration. The port identification of the upstream port and the port identification of the downstream port corresponding to each network port are listed in the network topology parameters. Specifically, the commands corresponding to the data forwarding order of the N ports are determined according to the port identifier of each port and the VLAN forwarding configuration as follows:
vlan create 100pbm＝cd0,cd1 ubm＝cd0,cd1；
vlan create 101pbm＝cd1,cd3 ubm＝cd1,cd3；
vlan create 103pbm＝cd3,cd0 ubm＝cd3,cd0。
as can be seen, the data forwarding order of the N ports is QSFP56 (1) port, QSFP56 (2) port, and QSFP56 (4) port.
For example, the configuration commands of all ports to be tested can be updated to the configuration file 3ports_snake _loop.
#Clear all vlan configuration；
vlan clear all
vlan remote 1pbm＝all
#Set default VLAN for all ports
for i＝0,31'pvlan set cd$i 10$i'
#Create VLAN membership for adjacent port pairs：
#loop by QSFP56 1、QSFP56 2、QSFP56 4
vlan create 100pbm＝cd0,cd1 ubm＝cd0,cd1；
vlan create 101pbm＝cd1,cd3 ubm＝cd1,cd3；
vlan create 103pbm＝cd3,cd0 ubm＝cd3,cd0。
#loop by other QSFP56 ports
…
According to the switch port testing method provided by the embodiment, the network address corresponding to each port is configured, the data forwarding sequence of the N ports is determined according to the network topology parameters and the network address corresponding to each port, the link to be tested of the snake-shaped ring topology structure is provided, and the loop device is configured for each port to be tested, so that continuous cycle testing of test data among a plurality of ports of the switch is realized, a tester does not need to be additionally provided, and the purpose of testing the reliability of the switch port can be realized.
Fig. 6 is a schematic structural diagram of a switch port testing apparatus according to an embodiment of the present invention. As shown in fig. 6, the switch port test apparatus includes: a generation module 601, a transmission module 602, and a determination module 603.
A generating module 601, configured to generate original test data; a sending module 602, configured to send the original test data to a test loop chain through an initial port of the test loop chain, so that the original test data is sequentially forwarded among N ports to be tested included in the test loop chain, where the test loop chain is obtained by configuring, according to preset parameters, the N ports to be tested of the switch to be tested, and N is a positive integer greater than or equal to 2; the determining module 603 is configured to control an initial port of the test loop chain to stop forwarding data according to preset test time, obtain an accumulated value of the number of data packets forwarded by the N ports to be tested, and determine whether a fault exists in the N ports to be tested in the test loop chain according to the accumulated value of the number of data packets forwarded by the N ports to be tested.
In a possible implementation manner, the preset parameters include initial parameters, network configuration parameters, and network topology parameters, and the switch port testing apparatus further includes a configuration module specifically configured to perform initialization configuration on the N ports to be tested according to the initial parameters; and configuring the port identification of each port according to the network topology parameters, configuring the VLAN forwarding configuration corresponding to each port according to the network configuration parameters, and determining the data forwarding sequence of the N ports according to the port identification of each port and the VLAN forwarding configuration.
In a possible implementation manner, the generating module 601 is specifically configured to obtain a minimum frame length corresponding to a full line speed of the switch to be tested and a time delay parameter corresponding to the port to be tested; and determining the number of bytes of a data frame contained in the test data packet according to the minimum frame length, and determining the number of data packets contained in the original test data to be injected into a single port according to the time delay parameter and the number of bytes of the data frame.
In a possible implementation manner, the determining module 603 is specifically configured to obtain an accumulated value of the number of data packets forwarded by the N ports to be tested; if the accumulated values of the number of the data packets forwarded by the N ports to be tested are inconsistent, determining that a packet loss transmission fault exists in at least one port of the N ports to be tested; and if the accumulated values of the number of the data packets forwarded by the N ports to be tested are completely consistent, judging that the N ports to be tested are normal.
In a possible implementation manner, the switch port testing apparatus further includes a monitoring module, which is specifically configured to determine that a cutoff fault exists in at least one of the N ports to be tested if it is monitored that the data forwarding amount of any port to be tested is zero.
In a possible implementation manner, the switch port testing apparatus further includes a determining module, where the determining module is specifically configured to sequentially obtain the cumulative value of the number of forwarding packets of the N ports to be tested, and determine, according to the cumulative value of the number of forwarding packets of each port to be tested, the port identifier of the port with the fault.
The apparatus provided in this embodiment may be used to implement the technical solutions of the above method embodiments, and the implementation principles and technical effects are similar, which are not described herein again.
Fig. 7 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present invention. As shown in fig. 7, the electronic apparatus of the present embodiment includes: a processor 701 and a memory 702; wherein
A memory 702 for storing computer-executable instructions;
the processor 701 is configured to execute the computer execution instructions stored in the memory to implement the steps performed by the server in the above embodiments. Reference may be made in particular to the description relating to the method embodiments described above.
Alternatively, the memory 702 may be separate or integrated with the processor 701.
When the memory 702 is provided separately, the server further includes a bus 703 for connecting the memory 702 and the processor 701.
The embodiment of the invention also provides a computer storage medium, wherein a computer execution instruction is stored in the computer storage medium, and when a processor executes the computer execution instruction, the switch port testing method is realized.
An embodiment of the present invention further provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the switch port testing method described above is implemented.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and for example, the division of the modules is only one logical division, and other divisions may be realized in practice, for example, a plurality of modules may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.
The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to implement the solution of the present embodiment.
In addition, functional modules in the embodiments of the present invention may be integrated into one processing unit, or each module may exist alone physically, or two or more modules are integrated into one unit. The unit formed by the modules can be realized in a hardware mode, and can also be realized in a mode of hardware and a software functional unit.
The integrated module implemented in the form of a software functional module may be stored in a computer-readable storage medium. The software functional module is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) or a processor to execute some steps of the methods described in the embodiments of the present application.
It should be understood that the Processor may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor, or in a combination of the hardware and software modules within the processor.
The memory may comprise a high-speed RAM memory, and may further comprise a non-volatile storage NVM, such as at least one disk memory, and may also be a usb disk, a removable hard disk, a read-only memory, a magnetic or optical disk, etc.
The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended ISA (Extended Industry Standard Architecture) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, the buses in the figures of the present application are not limited to only one bus or one type of bus.
The storage medium may be implemented by any type or combination of volatile or non-volatile memory devices, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.
An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be integral to the processor. The processor and the storage medium may reside in an Application Specific Integrated Circuits (ASIC). Of course, the processor and the storage medium may reside as discrete components in an electronic device or host device.
Those of ordinary skill in the art will understand that: all or a portion of the steps of implementing the above-described method embodiments may be performed by hardware associated with program instructions. The program may be stored in a computer-readable storage medium. When executed, the program performs steps comprising the method embodiments described above; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and these modifications or substitutions do not depart from the spirit of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A switch port testing method, applied to a switch to be tested, where each port of the switch to be tested is configured with a loopback apparatus, the method comprising:
generating original test data;
sending the original test data to a test loop chain through an initial port of the test loop chain, so that the original test data is sequentially subjected to continuous cyclic forwarding among N ports to be tested included in the test loop chain, wherein the test loop chain is obtained by configuring the N ports to be tested of the switch to be tested according to preset parameters, N is a positive integer greater than or equal to 2, the positions of the ports to be tested included in the test loop chain are randomly selected, and the number of the ports to be tested is a positive integer greater than or equal to 2;
controlling an initial port of the test loop chain to stop forwarding data according to preset test time, obtaining the quantity accumulated value of the data packets forwarded by the N ports to be tested, and judging whether the N ports to be tested in the test loop chain have faults or not according to the quantity accumulated value of the data packets forwarded by the N ports to be tested.
2. The method of claim 1, wherein the preset parameters comprise initial parameters, network configuration parameters, and network topology parameters, and before the sending the original test data into the test ring chain through the initial port of the test ring chain, the method further comprises:
carrying out initialization configuration on N ports to be tested according to the initial parameters;
configuring the port identification of each port according to the network topology parameters, configuring the VLAN forwarding configuration corresponding to each port according to the network configuration parameters, and determining the data forwarding sequence of the N ports according to the port identification of each port and the VLAN forwarding configuration.
3. The method according to claim 2, wherein the network topology parameter lists the port identifier of the upstream port and the port identifier of the downstream port corresponding to each network port.
4. The method of claim 1, wherein generating raw test data comprises:
acquiring a minimum frame length corresponding to the full-load line speed of the switch to be tested and a time delay parameter corresponding to the port to be tested;
and determining the number of bytes of a data frame contained in the test data packet according to the minimum frame length, and determining the number of data packets contained in the original test data to be injected into a single port according to the time delay parameter and the number of bytes of the data frame.
5. The method according to claim 1, wherein said determining whether there is a failure in the N ports under test in the test ring chain according to the cumulative number of packets forwarded by the N ports under test comprises:
acquiring the number accumulated value of the data packets forwarded by the N ports to be tested;
if the accumulated values of the number of the data packets forwarded by the N ports to be tested are inconsistent, determining that a packet loss transmission fault exists in at least one port of the N ports to be tested;
and if the accumulated values of the number of the data packets forwarded by the N ports to be tested are completely consistent, judging that the N ports to be tested are normal.
6. The method according to claim 1, before said controlling the initial port of the test loop chain to stop forwarding data according to the preset test time, further comprising:
and if the data forwarding amount of any port to be tested is monitored to be zero, judging that at least one port in the N ports to be tested has a cutoff fault.
7. The method according to any one of claims 1 to 6, wherein after said determining whether there is a failure in the N ports under test in the test ring chain according to the cumulative value of the number of data packets forwarded by the N ports under test, further comprising:
and sequentially acquiring the quantity accumulated value of the forwarded data packets of the N ports to be tested, and determining the port identification of the port with the fault according to the quantity accumulated value of the forwarded data packets of each port to be tested.
8. A switch port test system is characterized by comprising a switch to be tested and N loop devices;
the switch under test is specifically configured to perform the switch port testing method according to any one of claims 1 to 7;
the N loop devices are respectively installed on N ports to be tested of the switch to be tested and are specifically used for realizing self-circulation of data sending and data receiving of the ports to be tested.
9. An electronic device, comprising: at least one processor and memory;
the memory stores computer-executable instructions;
the at least one processor executing the memory-stored computer-executable instructions cause the at least one processor to perform the switch port testing method of any of claims 1 to 7.
10. A computer storage medium having computer executable instructions stored thereon which, when executed by a processor, implement the switch port testing method of any one of claims 1 to 7.
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| CN115426328B (en) * | 2022-07-29 | 2023-08-22 | 云尖信息技术有限公司 | Shunt switch, and test device, system and method of switch |
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