CN113671467A - Test system and method - Google Patents
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- CN113671467A CN113671467A CN202110760888.9A CN202110760888A CN113671467A CN 113671467 A CN113671467 A CN 113671467A CN 202110760888 A CN202110760888 A CN 202110760888A CN 113671467 A CN113671467 A CN 113671467A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
- G01S7/497—Means for monitoring or calibrating
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Abstract
The invention discloses a test system and a method, wherein the system comprises: the emitting device comprises a driving component and a VCSEL chip, wherein the driving component is used for inputting a driving signal to the VCSEL chip so that the VCSEL chip outputs nanosecond short pulse optical signals; the receiving device is used for receiving the nanosecond short pulse optical signal and performing photoelectric conversion on the nanosecond short pulse optical signal so as to output a pulse electrical signal corresponding to the nanosecond short pulse optical signal; and the display device is used for receiving the pulse electric signal from the receiving device and displaying the pulse electric signal so as to read the test parameters of the nanosecond short pulse optical signal. The system realizes the evaluation of the performance of the VCSEL chip working under the condition of short pulse and large current.
Description
Technical Field
The invention relates to the technical field of laser testing, in particular to a testing method and a testing system.
Background
At present, VCSEL (Vertical Cavity Surface Emitting Laser) products are widely used in optical ranging, face recognition, Laser radar and other scenes, and for realizing long-distance detection, nanosecond-level pulse signals need to be provided for VCSELs, and rectangular pulse signals emitted to the VCSELs need to have higher pulse peak power and shorter rise time to ensure accurate recognition when the pulse signals are transmitted back. When a VCSEL is used to realize a long-distance detection, the VCSEL needs to be tested to detect its relevant performance.
Currently, the test for the high-power VCSEL mostly stays in a pulse test stage of millisecond or sub-millisecond with a large duty ratio, main test parameters include L-I-V, NFT, FFT and the like, and the current test method or equipment cannot meet the current requirements.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. To this end, an object of the present invention is to provide a test system that enables evaluation of the performance of VCSEL chips operating under short pulse, high current conditions.
A second object of the invention is to propose a test method.
In order to achieve the above object, an embodiment of a first aspect of the present invention provides a test system, where the system includes: the transmitting device comprises a driving component and a VCSEL chip, wherein the driving component is used for inputting a driving signal to the VCSEL chip so that the VCSEL chip outputs nanosecond short pulse optical signals; receiving means for receiving the nanosecond short-pulse optical signal and performing photoelectric conversion on the nanosecond short-pulse optical signal to output a pulsed electrical signal corresponding to the nanosecond short-pulse optical signal;
and the display device is used for receiving the pulse electric signal from the receiving device and displaying the pulse electric signal so as to read the test parameters of the nanosecond short pulse optical signal.
According to the test system provided by the embodiment of the invention, the driving assembly is utilized to drive the VCSEL chip, so that the VCSEL chip outputs the nanosecond short pulse signal, the receiving device performs photoelectric conversion on the nanosecond short pulse signal, outputs the pulse electric signal corresponding to the nanosecond short pulse signal, and the display device is utilized to display the pulse electric signal so as to obtain the test parameters of the nanosecond short pulse signal, and the system realizes the evaluation on the performance of the VCSEL chip working under the conditions of short pulse and large current.
In addition, the test system proposed according to the above embodiment of the present invention may further have the following additional technical features:
according to one embodiment of the present invention, the driving assembly includes a driving board, a direct current power source, a signal generator, and a controller, wherein,
the direct current power supply and the signal generator are connected with the driving board, the driving board is connected with the VCSEL chip, and the controller is respectively connected with the driving board, the direct current power supply and the signal generator and is used for controlling the direct current power supply to supply power to the driving board and controlling the driving board to input the driving signal to the VCSEL chip.
According to one embodiment of the invention, the transmitter device further comprises a temperature control assembly comprising a test fixture and a temperature control module, wherein,
the test fixture is used for clamping the VCSEL chip, and the temperature control module is used for adjusting the temperature of the environment where the VCSEL chip is located.
According to one embodiment of the invention, the receiving means comprises an integrating sphere and a photodetector, wherein,
the integrating sphere is used for receiving the nanosecond short pulse optical signal and repeatedly reflecting the nanosecond short pulse optical signal, and the photoelectric detector is used for receiving the optical signal output by the integrating sphere and converting the optical signal into the pulse electrical signal.
According to an embodiment of the present invention, the photodetector is specifically configured to convert the optical signal into the pulsed electrical signal by using pre-calibrated parameters, where the pre-calibrated parameters include optical power and optical voltage values.
According to an embodiment of the present invention, the driving component is further connected to the display device for driving the display device to perform a display operation.
According to one embodiment of the invention, the VCSEL chip is packaged on an aluminum nitride ceramic substrate, wherein the test fixture holds the packaged VCSEL chip.
According to one embodiment of the invention, the temperature control module is used for enabling the environment of the VCSEL chip to be changed within the range of 20-110 ℃.
According to an embodiment of the invention, the driving signal comprises at least one of a current, a frequency, a duty cycle.
To achieve the above object, a second aspect of the present invention provides a testing method, which is used in the testing system as set forth in the first aspect of the present invention, and includes the following steps: inputting a driving signal to the VCSEL chip so that the VCSEL chip outputs nanosecond short pulse optical signals; converting the nanosecond short pulse optical signal into a corresponding pulse electrical signal; and receiving and displaying the pulse electrical signal so as to read the test parameters of the nanosecond pulse optical signal.
According to the testing method provided by the embodiment of the invention, the driving signal is input to the VCSEL chip, so that the VCSEL chip outputs the nanosecond short pulse optical signal, the nanosecond short pulse optical signal is subjected to photoelectric conversion, the nanosecond short pulse optical signal is converted into the corresponding pulse electrical signal, and the pulse electrical signal is received and displayed so as to read the testing parameter of the nanosecond short pulse optical signal.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
FIG. 1 is a schematic block diagram of a test system according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a test system according to an embodiment of the present invention;
FIG. 3 is a flow chart of a testing method of one embodiment of the present invention.
Description of reference numerals:
100. testing the system; 10. a transmitting device; 20. a receiving device; 30. a display device; 11. a drive assembly; 12. a VCSEL chip; 111. a drive plate; 112. a direct current power supply; 113. a signal generator; 114. a controller; 13. a temperature control assembly.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
The test system and method of the embodiments of the present invention will be described in detail with reference to the accompanying fig. 1-3 and the detailed description.
Fig. 1 is a schematic structural diagram of a test system according to an embodiment of the present invention. As shown in fig. 1, the test system 100 includes a transmitting device 10, a receiving device 20, and a display device 30.
The emitting device 10 includes a driving component 11 and a VCSEL chip 12, and the driving component 11 is configured to input a driving signal to the VCSEL chip 12 so that the VCSEL chip 12 outputs a nanosecond short pulse optical signal. The driving signal output by the driving component 11 includes at least one of current, frequency and duty ratio.
As a possible implementation manner, referring to fig. 2, the driving assembly 11 may include a driving board 111, a dc power supply 112, a signal generator 113, and a controller 114, wherein the dc power supply 112 and the signal generator 113 are both connected to the driving board 11, the driving board 111 is connected to the VCSEL chip 12, and the controller 114 is respectively connected to the driving board 11, the dc power supply 112, and the signal generator 113, and is configured to control the dc power supply 112 to supply power to the driving board 11 and control the driving board 11 to input a driving signal to the VCSEL chip 12.
Specifically, the driving assembly 11 is used to generate a constant current. The VCSEL chip 12 is driven by a constant current driving method, so that the VCSEL chip 12 outputs nanosecond short pulse optical signals, and the VCSEL chip 12 of the direct current device can work safely. The dc power supply 112 supplies dc power to the driving board 11, the signal generator 113 supplies a pulse modulation signal to the driving board 111 so that the driving board 111 outputs a constant current, and the controller 114 is connected to the driving board 11, the dc power supply 112, and the signal generator 113, respectively, to adjust the magnitude, frequency, duty ratio, etc. of the current output from the driving board 111.
In this embodiment, the driving board 111 is preferably a short pulse LD driving board, which supports a constant current mode. The signal generator 113 is preferably a nanosecond short pulse signal generator, and the controller 114 may be a computer, i.e., a computer may be used to adjust the magnitude, frequency, duty ratio, etc. of the current output from the driving board 111.
As a possible embodiment, referring to fig. 2, the emitting device 10 may further include a temperature control assembly 13, and the temperature control assembly 13 includes a test fixture and a temperature control module, wherein the test fixture is used for clamping the VCSEL chip 12, and the temperature control module is used for adjusting the temperature of the environment in which the VCSEL chip 12 is located. The VCSEL chip 12 can be packaged on an aluminum nitride ceramic substrate, wherein a test fixture holds the packaged VCSEL chip.
Specifically, when testing the VCSEL chip 12, the VCSEL chip 12 is placed on the temperature control assembly 13 taking into account the effect of temperature on the performance of the VCSEL chip 12, and when testing, the temperature control assembly 13 is adjusted to control the temperature of the environment in which the VCSEL chip 12 is located. Specifically, the VCSEL chip 12 can be first packaged on the aluminum nitride ceramic substrate, and then the packaged VCSEL chip 12 is clamped on the test fixture, and the temperature of the environment where the VCSEL chip 12 is located is adjusted through the temperature control module on the temperature control assembly 13. Wherein, the temperature control module can make the environment of the VCSEL chip 12 change within the range of 20-110 ℃.
The receiving device 20 receives the nanosecond short pulse optical signal and photoelectrically converts the nanosecond short pulse optical signal to output a pulsed electric signal corresponding to the nanosecond short pulse optical signal.
As one possible embodiment, referring to fig. 2, the receiving device 20 includes an integrating sphere 21 and a photodetector 22, wherein the integrating sphere 21 is configured to receive the nanosecond short-pulse optical signal and repeatedly reflect the nanosecond short-pulse optical signal, and the photodetector 22 is configured to receive the optical signal output by the integrating sphere 21 and convert the optical signal into a pulsed electrical signal. The photodetector 22 is specifically configured to convert the optical signal into a pulse electrical signal by using pre-calibrated parameters, where the pre-calibrated parameters include optical power and optical voltage values.
In this embodiment, integrating sphere 21 is a hollow sphere having a highly reflective inner surface, a highly efficient device for collecting light scattering or emission from a sample located inside or outside the sphere and near a window.
In this embodiment, the emitting device 10 may be placed inside the integrating sphere 21 or at a position on one side of a window on the integrating sphere 21, so that the integrating sphere 21 better receives the nanosecond short pulse optical signal output by the VCSEL chip 12, and repeatedly reflects the nanosecond short pulse optical signal, so as to reduce the loss of the nanosecond short pulse optical signal output by the VCSEL chip 12 and improve the accuracy of the test system.
The photodetector 22 receives the optical signal output by the integrating sphere 21, and under the action of the optical signal radiation, the conductivity of the photodetector 22 changes, so that the optical signal is converted into a pulse electrical signal.
Specifically, before testing the VCSEL chip 12, that is, before the photo detector 22 converts the optical signal into the pulse electrical signal, the standard VCSEL light source needs to be used to calibrate the optical power and the optical voltage of the photo detector 22, so as to improve the accuracy of the test system. The specific calibration process is as follows:
under certain PW/DC condition, such as current of 1000-4000 mA and interval of 500ms, the optical power of standard VCSEL chip sample is tested by calibrated thermopile optical power tester, and the tested optical power is converted into peak lightPower PP. Under the same test condition, the voltage pulse amplitude V input by the photodetector 22 is displayed by the display device 30PFitting the peak optical power PPAnd the voltage pulse amplitude VPAnd obtaining the linear coefficient k relation between the two.
When the photodetector 22 is in its linear operating region, the photocurrent I is proportional to the incident light intensity I, i.e., I ═ a × I, where a denotes the spectral sensitivity at the wavelength of use.
The output voltage V is proportional to I and the intensity I is proportional to the pulsed laser power P, i.e. P ═ k × V, where k denotes the proportionality coefficient.
Knowing that the pulse power is proportional to the output voltage, Pp＝k×VpWherein V isPRepresenting the peak voltage, PPRepresenting the peak optical power.
In this embodiment, the photodetector 22 is preferably an APD type photodetector.
The display device 30 receives the pulse electrical signal from the receiving device 20 and displays the pulse electrical signal so as to read the test parameters of the nanosecond short pulse optical signal. Optionally, the driving assembly 11 may also be connected to the display device 30 for driving the display device 30 to perform a display operation.
Specifically, the display device 30 can capture the nanosecond short pulse optical signal output by the VCSEL chip 12 and converted by the photodetector 22, and adjust the display device 30, so that the parameters such as the rise time and the peak power of the nanosecond short pulse optical signal can be read.
In this embodiment, the display device 30 is preferably an oscilloscope.
The testing system set up by the embodiment of the invention can provide a short-pulse and large-current working scene so as to test the rise time of the nanosecond short-pulse optical signal output by the VCSEL chip 12 under the working condition of the nanosecond short-pulse optical signal and the nanosecond large-current optical signal after the nanosecond short-pulse optical signal is transmitted in a short-distance free space. Meanwhile, the rising time of the optical pulse signals emitted by the VCSEL at different ambient temperatures can be considered.
According to the test system provided by the embodiment of the invention, the driving assembly 11 is used for driving the VCSEL chip 12, so that the VCSEL chip 12 outputs nanosecond short pulse signals, the receiving device 20 performs photoelectric conversion on the nanosecond short pulse signals, outputs pulse electric signals corresponding to the nanosecond short pulse signals, and displays the pulse electric signals by using the display device 30 so as to obtain test parameters of the nanosecond short pulse signals, and the system realizes evaluation on the performance of the VCSEL chip 12 working under the conditions of short pulses and large current.
The invention also provides a test method.
FIG. 3 is a flow chart of a testing method of one embodiment of the present invention. The test method provided by the invention is used for the test system, and as shown in fig. 3, the test method comprises the following steps:
s1, inputting a driving signal to the VCSEL chip to enable the VCSEL chip to output nanosecond short pulse optical signals;
s2, converting the nanosecond short pulse optical signal into a corresponding pulse electrical signal;
and S3, receiving and displaying the pulse electric signal so as to read the test parameters of the nanosecond pulse optical signal.
It should be noted that, for other specific implementations of the test method according to the embodiment of the present invention, reference may be made to the specific implementation of the test system according to the above embodiment of the present invention.
According to the test method provided by the embodiment of the invention, the driving signal is input to the VCSEL chip 12, so that the VCSEL chip 12 outputs the nanosecond short pulse optical signal, the nanosecond short pulse optical signal is subjected to photoelectric conversion, the nanosecond short pulse optical signal is converted into the corresponding pulse electrical signal, and the pulse electrical signal is received and displayed so as to read the test parameters of the nanosecond short pulse optical signal, and the evaluation on the performance of the VCSEL chip 12 working under the conditions of short pulse and large current is realized.
It should be noted that the logic and/or steps represented in the flowcharts or otherwise described herein, such as an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (10)
1. A test system, the system comprising:
the transmitting device comprises a driving component and a VCSEL chip, wherein the driving component is used for inputting a driving signal to the VCSEL chip so that the VCSEL chip outputs nanosecond short pulse optical signals;
receiving means for receiving the nanosecond short-pulse optical signal and performing photoelectric conversion on the nanosecond short-pulse optical signal to output a pulsed electrical signal corresponding to the nanosecond short-pulse optical signal;
and the display device is used for receiving the pulse electric signal from the receiving device and displaying the pulse electric signal so as to read the test parameters of the nanosecond short pulse optical signal.
2. The test system of claim 1, wherein the drive assembly comprises a drive board, a DC power supply, a signal generator, and a controller, wherein,
the direct current power supply and the signal generator are connected with the driving board, the driving board is connected with the VCSEL chip, and the controller is respectively connected with the driving board, the direct current power supply and the signal generator and is used for controlling the direct current power supply to supply power to the driving board and controlling the driving board to input the driving signal to the VCSEL chip.
3. The test system of claim 2, wherein the launch device further comprises a temperature control assembly comprising a test fixture and a temperature control module, wherein,
the test fixture is used for clamping the VCSEL chip, and the temperature control module is used for adjusting the temperature of the environment where the VCSEL chip is located.
4. The test system of claim 1, wherein the receiving device comprises an integrating sphere and a photodetector, wherein,
the integrating sphere is used for receiving the nanosecond short pulse optical signal and repeatedly reflecting the nanosecond short pulse optical signal, and the photoelectric detector is used for receiving the optical signal output by the integrating sphere and converting the optical signal into the pulse electrical signal.
5. The test system according to claim 4, wherein the photodetector is specifically configured to convert the optical signal into the pulsed electrical signal using pre-calibrated parameters, wherein the pre-calibrated parameters include optical power and optical voltage values.
6. The test system according to any one of claims 1 to 5, wherein the driving assembly is further connected to the display device for driving the display device to perform a display operation.
7. The test system of claim 3, wherein the VCSEL chip is packaged on an aluminum nitride ceramic substrate, wherein the test fixture holds the packaged VCSEL chip.
8. The test system of claim 3, wherein the temperature control module is configured to vary the environment in which the VCSEL chip is located within a range of 20-110 ℃.
9. The test system of claim 1, wherein the drive signal comprises at least one of a current, a frequency, and a duty cycle.
10. A method of testing for use in a test system according to any one of claims 1 to 9, the method comprising the steps of:
inputting a driving signal to the VCSEL chip so that the VCSEL chip outputs nanosecond short pulse optical signals;
converting the nanosecond short pulse optical signal into a corresponding pulse electrical signal;
and receiving and displaying the pulse electrical signal so as to read the test parameters of the nanosecond pulse optical signal.
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