CN113655358A - Test circuit and power protection chip of power tube - Google Patents
Test circuit and power protection chip of power tube Download PDFInfo
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- CN113655358A CN113655358A CN202110790128.2A CN202110790128A CN113655358A CN 113655358 A CN113655358 A CN 113655358A CN 202110790128 A CN202110790128 A CN 202110790128A CN 113655358 A CN113655358 A CN 113655358A
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- G01R31/2637—Circuits therefor for testing other individual devices
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Abstract
The application provides a test circuit of power tube, this circuit includes the power tube, control circuit and sampling pipe, the power tube includes N +1 unit pipe, wherein N +1 unit pipe includes first unit pipe and N unit pipe, under test mode, control circuit closes N unit pipe, only opens first unit pipe, with the output current who has reduced the power tube, thereby turn into the undercurrent that can test through the probe with the heavy current, and improve the stability of test.
Description
Technical Field
The application relates to the technical field of circuits, in particular to a test circuit of a power tube and a power protection chip.
Background
In the power protection chip, many power transistors are integrated. The power transistor is a transistor serving as a final-stage output in the amplifier circuit. The power tube can be based on the maximum dissipated power P of the collectorCMThe size of the power tube is divided into a high-power tube and a low-power tube. The power tube with the maximum collector power dissipation larger than 1 watt (W) can be a high-power tube, and the power tube with the maximum collector power dissipation smaller than 1W can be a low-power tube.
The power tubes can flow a large current in the ampere level when working normally. The large current easily generates a large voltage drop across the power tube, and the power tube may generate heat. If the test is carried out directly, the test result is unstable. And the probe for mass production test does not allow large current to be input.
At present, the mass production test of the power protection chip is still configured with a small current gear, the small current is detected, the large current is difficult to detect, and the test requirement is difficult to meet.
Disclosure of Invention
The application provides a test circuit of a power tube. This circuit includes power tube, control circuit and sampling pipe, and the power tube includes N +1 unit pipe, and N +1 unit pipe includes first unit pipe and N unit pipe, and under test mode, control circuit switches on first unit pipe, and N unit pipe closes, reduces the output current of power tube to turn into the undercurrent that can carry out the test through the probe with the heavy current, and improve the stability of test.
In a first aspect, the present application provides a test circuit for a power tube, where the circuit includes a power tube, a control circuit, and a sampling tube, the power tube includes N +1 unit tubes, the N +1 unit tubes include a first unit tube and N unit tubes, and N is greater than 1;
in the test mode, the control circuit switches on the first unit tube and switches off the N unit tubes to reduce the output current of the power tube.
In some possible implementation manners, the N +1 unit tubes are all N-type metal oxide semiconductor field effect transistors NMOS, the drain electrodes of the N +1 unit tubes are connected with the power supply input end, and the source electrodes of the N +1 unit tubes are connected with the output end;
the grid connection control circuit of N unit pipes, control circuit include first switch tube and second switch tube, and first switch tube is P type metal oxide semiconductor field effect transistor PMOS, and the second switch tube is NMOS, and first switch tube is in the off-state, and when the second switch tube was in the on-state, the grid and the source electrode short circuit of N unit pipe, and N unit pipe is turn-off, and first unit pipe switches on, and the output current of power tube reduces.
In some possible implementation manners, the control circuit further includes a first logic unit, a third switching tube, a fourth switching tube, a fifth switching tube, a first resistor, a first inverter, and a second inverter, where the third switching tube is an NMOS, and the fourth switching tube and the fifth switching tube are a PMOS; the grid electrode of the fourth switching tube is connected with the grid electrode of the fifth switching tube, the source electrodes of the fourth switching tube and the fifth switching tube are connected to the power supply input end, the drain electrode of the fourth switching tube is connected with the source electrode of the fourth switching tube and the drain electrode of the third switching tube respectively, the grid electrode of the third switching tube is connected with the first logic unit, the drain electrode of the fifth switching tube is connected with the input end of the first reverser and the first end of the first resistor respectively, the output end of the first reverser is connected with the input end of the second reverser, the output end of the second reverser is connected with the grid electrode of the second switching tube, and the second end of the first resistor is connected with the output end.
In some possible implementations, the first logic unit is configured to control a state of the third switching tube in combination with the test current, when the third switching tube is turned on, the fourth switching tube is turned on, and mirrors the bias current to the high-voltage port, and a pull-up current source is formed by a fifth switching tube, where the pull-up current of the fifth switching tube generates a voltage drop across the first resistor, the first inverter outputs a low level, the second inverter is configured to output a high level, and correspondingly, the first switching tube is turned off and the second switching tube is turned on.
In some possible implementation manners, the circuit further includes a current-limiting resistor, a first end of the current-limiting resistor is grounded, a second end of the current-limiting resistor is connected with the source electrode of the sampling tube through a sixth switching tube, and the sixth switching tube is a PMOS.
In some possible implementations, the circuit further includes a rail-to-rail operational amplifier, the source of the sampling tube and the source of the N +1 unit tubes are respectively connected to the input end of the rail-to-rail operational amplifier, and the output end of the rail-to-rail operational amplifier is connected to the gate of the sixth switching tube.
In some possible implementations, the circuit further includes a second logic unit and a charge pump, the second logic unit being a comparator;
one input end of the comparator is connected with the second end of the current-limiting resistor, the other input end of the comparator is connected with the reference voltage, the output end of the comparator is connected with the grid electrode of the sampling tube, the first end of the charge pump is connected with the grid electrode of the sampling tube, and the other end of the charge pump is connected with the source electrode of the first unit tube.
In some possible implementations, N +1 unit tubes are perfectly matched.
In some possible implementations, the number of unit tubes is determined based on a current limit threshold and a maximum measurement of the test probe.
In a second aspect, the present application provides a power protection chip, where the power protection chip includes the test circuit of the power transistor in the first aspect or any implementation manner of the first aspect.
The present application can further combine to provide more implementations on the basis of the implementations provided by the above aspects.
According to the technical scheme, the embodiment of the application has the following advantages:
the embodiment of the application provides a test circuit of power tube, this circuit includes power tube, control circuit and sampling pipe, wherein the power tube includes N +1 unit pipe, and N +1 unit pipe includes first unit pipe and N unit pipe, and under test mode, control circuit switches on first unit pipe, and N unit pipe closes to reduce the output current of power tube, so, can control the output current of power tube, make output current satisfy the test demand.
Further, the test circuit of the power tube in this embodiment includes two test modes, when the current flowing through the power tube meets the test requirement, the output current is unchanged, when the current flowing through the power tube is greater than the testable current, the current is subjected to current limiting sampling, and the output current is 1/N of the current flowing through the power tube, so that the output current meets the test requirement.
Drawings
In order to more clearly illustrate the technical method of the embodiments of the present application, the drawings needed to be used in the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without inventive labor.
Fig. 1 is a schematic diagram of a test circuit of a power transistor according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of a power protection chip according to an embodiment of the present application.
Detailed Description
The scheme in the embodiments provided in the present application will be described below with reference to the drawings in the present application.
The terms "first" and "second" in the embodiments of the present application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
Some technical terms referred to in the embodiments of the present application will be first described.
In the current test of the power tube, how to test the large current always belongs to the difficulty in the industry, and on one hand, the large current easily generates large voltage drop at two ends of the power tube, so that the power tube generates heat, the overheating protection is caused, and the stable test cannot be performed. On the other hand, mass-produced probes have a maximum current limit and cannot test large currents.
In view of this, the present application provides a test circuit for a power tube, the test circuit includes a power tube, a control circuit and a sampling tube, wherein the power tube includes a plurality of unit tubes, specifically includes a first unit tube and N unit tubes, and in a test mode, the control circuit turns on the first unit tube, and the N unit tubes are turned off, so as to reduce an output current of the power tube, so that the output current is always smaller than a testable current, thereby being capable of safely and stably testing a large current.
For the convenience of understanding, the test circuit of the power tube provided by the embodiment of the present application is described below with reference to the accompanying drawings.
Referring to a schematic diagram of a test circuit of a power tube shown in fig. 1, the test circuit includes a power tube, a control circuit and a sampling tube, wherein the power tube includes N +1 unit tubes, specifically includes a first unit tube and N unit tubes.
Specifically, the unit tube (mpass) is an N-type metal oxide semiconductor (NMOS), and the drain of the unit tube is connected to the power input terminal and the source thereof is connected to the output terminal.
The control circuit may include a first switch transistor and a second switch transistor, wherein the first switch transistor is a P-type metal oxide semiconductor (PMOS) transistor, and the second switch transistor is an NMOS transistor.
The source electrode of the first switch tube is connected with the grid electrode of the sampling tube and the grid electrode of the first unit tube, the drain electrode of the first switch tube is connected with the grid electrodes of the N unit tubes, and the grid electrode of the first switch tube is connected with the grid electrode of the second switch tube. The drain electrode of the second switch tube is connected with the grid electrodes of the N unit tubes, and the source electrode of the second unit tube is connected with the source electrodes of the N unit tubes and the power supply output.
When the first switch tube is in an off state and the second switch tube is in an on state, the source electrodes and the grid electrodes of the N unit tubes are disconnected, so that the N unit tubes are turned off, and the output current of the power tube is reduced. When the N unit tubes work normally, the output current I of the power tube is equal to N x I, wherein I is the current flowing through each unit tube in the N unit tubes, and N is the number of the unit tubes.
When the first switch tube is in a conducting state, the second switch tube is in a switching-off state, the grid electrodes of the N unit tubes are connected with the grid electrode of the first unit tube, output current is not sampled and is kept unchanged, and therefore testing accuracy under the condition of small current is guaranteed.
Specifically, the power tube includes N unit tubes, where N is greater than 1. N may be determined based on the current limit threshold and the maximum measurement of the test probe. In some embodiments, when the ratio of the current limit threshold to the maximum measurement of the test probe is an integer, N may take on the integer value. For example, the current limit threshold is 4 amperes (Ampere, a), and the maximum measurement value of the test probe is 1A, and N is 4A/1A is 4. Wherein N may also take on integer values greater than this ratio.
In some embodiments, when the ratio of the current limit threshold to the maximum measurement of the test probe is not an integer, N may be an integer value rounded up from the above ratio. For example, if the current limit threshold is 5A, and the maximum measurement value of the test probe is 2A, the ratio may be 5A/2A — 2.5, and at this time, N may be an integer value obtained by rounding up the ratio, that is, N may be 3. N may also be other integer values greater than the above ratio, for example, 4.
It should be noted that the unit tube included in the power tube may be different. In some embodiments, the cell tubes may be different in size, and the maximum current allowed to flow through each cell tube may be different. By taking the current limiting threshold value as 5A for illustration, the power tube may include three unit tubes, the maximum current value allowed to flow by two unit tubes may be 2A, and the maximum current value allowed to flow by another unit tube may be 1A.
In some possible implementations, the control circuit may further include a first logic unit, a third switching tube, a fourth switching tube, a fifth switching tube, a first resistor, a first inverter, and a second inverter.
The first logic unit is used for controlling the state of the third switching tube according to the test current. In some possible implementations, the first logic unit is a nor gate structure, and outputs a high level (logic 1) only when the inputs are all low level (logic 0). The first input of the first logic cell may reflect an operating mode of the circuit.
The first input of the first logic cell may be high when the circuit is in a normal operating condition and low when the circuit is in a test mode. When the circuit is in the test mode, the second input may reflect the magnitude of the current flowing through the power tube: the second input may be a low level when the current flowing through the power transistor is a large current, and may be a high level when the current flowing through the power transistor is a small current.
The third switch tube may be an NMOS, a source electrode of the third switch tube is connected to a fixed current source, optionally, the fixed current source is 0.5 μ a, a gate electrode of the third switch tube is connected to the output of the first logic unit, and a drain electrode of the third switch tube is connected to a drain electrode of the fourth switch tube, a gate electrode of the fourth switch tube, and a gate electrode of the fifth switch tube. The first logic unit controls the on-off of the third switching tube according to the input.
The fourth switching tube can be a PMOS, the source electrode of the fourth switching tube is connected with the power input, and the grid electrode of the fourth switching tube is connected with the drain electrode of the fourth switching tube and the grid electrode of the fifth switching tube and the drain electrode of the third switching tube.
The fifth switching tube may be a PMOS, a source of the fifth switching tube is connected to the power input, a gate of the fifth switching tube is connected to a gate of the fourth switching tube, a drain of the fourth switching tube and a drain of the third switching tube, and the drain of the fifth switching tube is connected to one end of the first resistor.
The first end of the first resistor is connected with the drain electrode of the fifth switching tube, and the other end of the first resistor is connected with the power output end.
The input end of the first inverter is connected with the drain electrode of the fifth switching tube and the first end of the first resistor, and the output end of the first inverter is connected with the input end of the second inverter.
The input end of the second phase inverter is connected with the output end of the first phase inverter, and the output end of the second phase inverter is connected with the grid electrode of the first switching tube and the grid electrode of the second switching tube.
In some possible implementations, the circuit may further include a diode, where the diode is connected in parallel with the first resistor, an anode of the diode is connected to the output, and a cathode of the diode is connected to the input of the first inverter and the drain of the fifth switching tube.
The first logic unit is used for controlling the state of the third switching tube: when the high-current test mode is adopted, the first input of the first logic unit is at a low level, the second input of the first logic unit is at a low level, and the output of the first logic unit is at a high level. Therefore, the third switching tube is conducted, the fourth switching tube is started, the bias current is mirrored to the high-voltage port, a pull-up current source is formed through the fifth switching tube, the pull-up current of the fifth switching tube generates voltage drop on the first resistor, the first inverter outputs low current, the second inverter outputs high current, the first switching tube is turned off, the second switching tube is conducted, the grid electrode and the source electrode of the N unit tube are short-circuited, the N unit tube is turned off, a high-current test mode is entered, and the output current is a current limit value of 1/N.
When the test circuit is in the low-current test mode, the first input of the first logic unit is at a low level, the second input of the first logic unit is at a high level, and the output of the first logic unit is at a low level. Therefore, the third switching tube is turned off, the fifth switching tube has no pull-up current, the first resistor connects the input end of the first phase inverter to the output end, the first phase inverter outputs high level, the second phase inverter outputs low level, the first switching tube is turned on, the second switching tube is turned off, the N unit tubes are connected with the grid electrode of the first unit tube, the output current is not sampled and is kept unchanged, and therefore the test precision of small current is guaranteed.
In some possible implementations, the circuit further includes a current limiting resistor (rlim), and the logic output of the second input terminal of the first logic unit may be determined by the current limiting resistor. The current limiting resistor can be an external current limiting threshold value configuration resistor, and the size of the current limiting resistor determines the size of current limiting of the circuit. In practice, the threshold current for switching the high and low levels of the second input terminal of the first logic unit may be set according to the range of the actual test machine.
The first end of the current-limiting resistor is grounded, the second end of the current-limiting resistor is connected with the source electrode of the sampling tube through a sixth switching tube, and the sixth switching tube is a PMOS.
In some possible implementations, the circuit further includes a rail-to-rail operational amplifier, a second logic unit, and a charge pump.
The drain electrode of the sixth switching tube is connected with the second end of the current-limiting resistor and the input end of the second logic unit, the grid electrode of the sixth switching tube is connected with the output end of the rail amplifier, and the source electrode of the sixth switching tube is connected with the inverting input end of the rail amplifier.
An operational amplifier (OPA) is an amplifying circuit capable of performing mathematical operations on a signal, and usually constitutes some kind of functional module in combination with a feedback network. If the voltage input by the non-inverting input end of the operational amplifier is higher than the voltage input by the inverting input end, the output end of the operational amplifier can output a voltage which is the same as the voltage of the positive power supply; if the voltage input by the inverting input terminal is higher than the voltage input by the non-inverting input terminal, the output terminal of the operational amplifier outputs a voltage equal to the negative power voltage. If the operational amplifier adopts a single power supply, if the voltage input by the inverting input end is higher than the voltage input by the non-inverting input end, the output voltage of the output end of the operational amplifier is equal to the voltage. In this embodiment, a single-power operational amplifier is used, and when the voltage input to the non-inverting input terminal of the operational amplifier is higher than the voltage input to the inverting input terminal, a high level is output, and when the voltage input to the inverting input terminal of the operational amplifier is higher than the voltage input to the non-inverting input terminal, a low level is output.
The non-inverting input end of the rail-to-rail (rail-to-rail) operational amplifier is connected with the power supply output, and is simultaneously connected with one end of the charge pump, the source electrode of the first unit tube, the other end of the first resistor, the source electrode of the second switch tube and the source electrode of the Nth unit tube, the inverting input end of the rail-to-rail operational amplifier is connected with the source electrode of the sixth switch tube and the source electrode of the sampling tube, and the output end of the rail-to-rail operational amplifier is connected with the grid electrode of the sixth switch tube.
The second logic unit may be a comparator, and optionally, an operational amplifier a may be used as the comparator. The positive phase input end of the operational amplifier A is a reference voltage (vref), the negative phase input end of the operational amplifier A is a second end of the current-limiting resistor and a drain electrode of the sixth switching tube, and the output end of the operational amplifier A is connected with one end of the charge pump, a grid electrode of the sampling tube and a grid electrode of the first unit tube.
A charge pump is an energy storage element that can vary the output voltage according to the input voltage. In this embodiment, the charge pump is respectively connected to the output of the second logic unit and the non-inverting input of the rail-to-rail operational amplifier for providing voltage to the current-limiting resistor.
When the output current of the power tube is close to the current limiting threshold value, the voltage drop of the current of the sampling tube on the current limiting resistor is close to the reference voltage, the voltage of the grid electrode and the source electrode of the power tube is reduced by the current limiting loop, and the current flowing through the power tube is limited. In some possible implementations, the resistance value of each current limiting resistor corresponds to a maximum output current.
During normal operation, the output current is not sampled, and only in the test mode, the sampling mode of the output current is determined according to the magnitude of the current limit. Alternatively, when the output current is a small current (e.g., less than the maximum measurement value of the test probe), the output current is constant, and when the output current is a large current, the output current is 1/N of the large current. Wherein the high current may be a current exceeding what the probe can test.
The first logic unit is used for determining the working mode of the circuit. The first logic unit is of a nor gate structure and outputs a high level (logic 1) only when all inputs are low level (logic 0). In the test mode, the first input terminal of the first logic unit is at a low level. The second input end of the first logic unit is a logic output for judging the magnitude of the current limit, when the output current is a small current, the second input end of the first logic unit is at a high level, and the output end of the first logic unit outputs a low level. When the output current is large current, the second input end of the first logic unit is at low level, the output end of the first logic unit outputs high level, and the output current is reduced to 1/N of the original output current.
In the high-current test mode, the first input end of the first logic unit is at a low level, the second input end of the first logic unit is at a low level, and the output end of the first logic unit is at a high level. The third switching tube is conducted, the fourth switching tube is started, the bias current is mirrored to the high-voltage port, a pull-up current source is formed through the fifth switching tube, the pull-up current of the fifth switching tube generates voltage drop on the first resistor, the first phase inverter outputs low current, the second phase inverter outputs high current, the first switching tube is turned off, the second switching tube is conducted, the grid electrode and the source electrode of the Nth unit tube are short-circuited, the Nth unit tube is turned off, and the output current is a current limiting value of 1/N.
In the low current test mode, the first input terminal of the first logic unit is at a low level, the second input terminal of the first logic unit is at a high level, and the output terminal of the first logic unit is at a low level. The third switching tube is turned off, the fourth switching tube is turned off, the fifth switching tube cannot form a pull-up current, the input of the first phase inverter is the power output end through the first resistor, therefore, the first phase inverter outputs a high level, the second phase inverter outputs a low level, the first switching tube is turned on, the second switching tube is turned off, the grid electrode of the N unit tube is connected with the grid electrode of the first unit tube, the output current is not sampled and is kept unchanged, and therefore the precision of the small current test is guaranteed.
The sampling proportion can be automatically switched between the large current test mode and the small current test mode, and the sampling proportion in the small current test mode is 1, so that the sampling precision is ensured. Under the heavy current test mode, the sampling proportion is determined according to the output current and the current limiting size, so that the current meets the requirement of the probe and can be stably tested.
Alternatively, the second input of the first logic unit may be determined by a current limiting resistor. The current-limiting resistor can be a configuration resistor externally connected with a current-limiting threshold, and the magnitude of the resistance value of the current-limiting resistor determines the magnitude of the current-limiting current. Specifically, the current-limiting threshold current for controlling the switching of the second input high and low levels of the first logic unit can be set according to the range of the test machine.
In some possible implementations, the test circuit of the power tube can also be used to detect the working state of the chip under a large current.
In summary, the test circuit of the power tube provided by the embodiment of the present application includes a power tube and a sampling tube, where the power tube includes a plurality of unit tubes, and the power tube is connected to the sampling tube. When the circuit is in a test mode, the sampling tube adjusts the states of a plurality of unit tubes in the power tube according to a preset current-limiting threshold value, and controls the output current of the power tube, so that the output current of the power tube accords with the preset current-limiting threshold value, and the circuit is enabled to be in a test mode.
Further, the circuit comprises a working mode and a test mode, wherein the test mode comprises a low current test mode in which the current passing through the power tube meets a preset current limiting threshold value and a high current test mode in which the current passing through the power tube is larger than the preset current limiting threshold value. And testing the current flowing through the power tube by adopting different loops according to the current passing through the power tube and the preset current-limiting threshold value.
Corresponding to the circuit embodiment, the present application further provides a power protection chip, as shown in fig. 2, including the test circuit of the power transistor.
As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that all or part of the steps in the above embodiment methods can be implemented by software plus a necessary general hardware platform. Based on such understanding, the technical solution of the present application may be essentially or partially implemented in the form of a software product, which may be stored in a storage medium, such as a ROM/RAM, a magnetic disk, an optical disk, etc., and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network communication device such as a media gateway, etc.) to execute the method according to the embodiments or some parts of the embodiments of the present application.
It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. The method disclosed by the embodiment corresponds to the system disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the system part for description.
It should also be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing description of the disclosed embodiments will enable those skilled in the art to make or use the invention in various modifications to these embodiments, which will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. The circuit for testing the power tube is characterized by comprising the power tube, a control circuit and a sampling tube, wherein the power tube comprises N +1 unit tubes, the N +1 unit tubes comprise a first unit tube and N unit tubes, and N is larger than 1;
in a test mode, the control circuit switches on the first unit tube and switches off the N unit tubes to reduce the output current of the power tube.
2. The circuit of claim 1, wherein the N +1 unit transistors are all N-type metal oxide semiconductor field effect transistors NMOS, the drains of the N +1 unit transistors are connected to the power input terminal, and the sources of the N +1 unit transistors are connected to the output terminal;
the grid connection of N unit pipe control circuit, control circuit includes first switch tube and second switch tube, first switch tube is P type metal oxide semiconductor field effect transistor PMOS, the second switch tube does the NMOS, first switch tube is in the off-state, just when the second switch tube is in the on-state, the grid and the source electrode short circuit of N unit pipe, N unit pipe is turn-off, first unit pipe switches on, the output current of power tube reduces.
3. The circuit of claim 2, wherein the control circuit further comprises a first logic unit, a third switch tube, a fourth switch tube, a fifth switch tube, a first resistor, a first inverter, and a second inverter, wherein the third switch tube is the NMOS, and the fourth switch tube and the fifth switch tube are the PMOS; the fourth switch tube is connected with the grid electrode of the fifth switch tube, the fourth switch tube is connected with the source electrode of the fifth switch tube, the drain electrode of the fourth switch tube is connected with the source electrode of the fourth switch tube and the drain electrode of the third switch tube respectively, the grid electrode of the third switch tube is connected with the first logic unit, the drain electrode of the fifth switch tube is connected with the input end of the first reverser and the first end of the first resistor respectively, the output end of the first reverser is connected with the input end of the second reverser, the output end of the second reverser is connected with the grid electrode of the second switch tube, and the second end of the first resistor is connected with the output end.
4. The circuit of claim 3, wherein the first logic unit is configured to control a state of the third switch tube in conjunction with a test current, when the third switch tube is turned on, the fourth switch tube is turned on and mirrors a bias current to the high-voltage port, and a pull-up current source is formed through the fifth switch tube, the pull-up current of the fifth switch tube generates a voltage drop across the first resistor, the first inverter outputs a low level, the second inverter outputs a high level, and correspondingly, the first switch tube is turned off and the second switch tube is turned on.
5. The circuit according to any one of claims 1 to 4, further comprising a current limiting resistor, wherein a first end of the current limiting resistor is grounded, a second end of the current limiting resistor is connected to the source electrode of the sampling tube through a sixth switching tube, and the sixth switching tube is the PMOS.
6. The circuit of claim 5, further comprising a rail-to-rail operational amplifier, wherein the source of the sampling pipe and the sources of the N +1 unit pipes are respectively connected to the input terminals of the rail-to-rail operational amplifier, and the output terminal of the rail-to-rail operational amplifier is connected to the gate of the sixth switching pipe.
7. The circuit of claim 5, further comprising a second logic unit and a charge pump, the second logic unit being a comparator;
one input end of the comparator is connected with the second end of the current-limiting resistor, the other input end of the comparator is connected with a reference voltage, the output end of the comparator is connected with the grid electrode of the sampling tube, the first end of the charge pump is connected with the grid electrode of the sampling tube, and the other end of the charge pump is connected with the source electrode of the first unit tube.
8. The circuit of any of claims 1 to 4, wherein the N +1 unit tubes are perfectly matched.
9. The circuit of claim 8, wherein the number of unit tubes is determined based on the current limit threshold and a maximum measurement of a test probe.
10. A power protection chip, characterized in that the power protection chip comprises a test circuit of the power tube according to any one of claims 1 to 9.
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| CN202110790128.2A CN113655358A (en) | 2021-07-13 | 2021-07-13 | Test circuit and power protection chip of power tube |
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