CN113644935B

CN113644935B - Signal redrive device, data storage system and mode control method

Info

Publication number: CN113644935B
Application number: CN202110908924.1A
Authority: CN
Inventors: 周柏融; 陈圣文; 陈重光
Original assignee: Phison Electronics Corp
Current assignee: Phison Electronics Corp
Priority date: 2021-08-09
Filing date: 2021-08-09
Publication date: 2024-04-12
Anticipated expiration: 2041-08-09
Also published as: CN113644935A

Abstract

The invention provides a signal redrive device, a data storage system and a mode control method. The method comprises the following steps: receiving a first signal through a receiving end circuit of the signal redrive device; detecting analog signal characteristics by the receiver circuit; entering a first mode based on the analog signal characteristic; in the first mode, modulating the first signal and outputting a second signal; transmitting the second signal through a transmitting end circuit of the signal redrive device; detecting digital signal characteristics through the receiving end circuit; and switching from the first mode to a second mode based on the digital signal characteristics. Thus, the signal redrive device can achieve balance between power saving and maintaining signal transmission quality.

Description

Signal redrive device, data storage system and mode control method

Technical Field

The present invention relates to a circuit control technology, and more particularly, to a signal redrive device, a data storage system, and a mode control method.

Background

The signal repeater (re-driver) is generally used to extend the transmission distance of the signal. While using signal repeaters to improve high speed signal quality, users also want to have standby/power saving modes to save power consumption. However, if the signal repeater is not properly switched from the standby/power saving mode to the normal transmission mode, signal loss may occur. Therefore, how to control the transition of the signal repeater between the standby/power saving mode and the normal transmission mode becomes an important issue.

Disclosure of Invention

The invention provides a signal redrive device, a data storage system and a mode control method, which can balance the signal redrive device between power saving and signal transmission quality maintenance.

An exemplary embodiment of the present invention provides a signal redrive device, which includes a receiving end circuit, a modulation circuit, a transmitting end circuit, and a mode control circuit. The modulation circuit is connected to the receiving end circuit. The transmitting end circuit is connected to the modulation circuit. The mode control circuit is connected to the receiving end circuit and the modulation circuit. The receiving end circuit is used for receiving a first signal. The mode control circuit is used for detecting the analog signal characteristic through the receiving end circuit and controlling the modulation circuit to enter a first mode according to the analog signal characteristic. In the first mode, the modulation circuit is used for modulating the first signal and outputting a second signal. The transmitting-end circuit is used for transmitting the second signal. The mode control circuit is further configured to detect a digital signal characteristic through the receiving end circuit and control the modulation circuit to switch from the first mode to the second mode according to the digital signal characteristic.

In an exemplary embodiment of the present invention, the mode control circuit includes a first detection circuit, a second detection circuit, and a switching circuit. The first detection circuit is connected to the receiving-end circuit. The second detection circuit is connected to the first detection circuit. The switching circuit is connected to the first detection circuit, the second detection circuit and the modulation circuit. The first detection circuit is used for providing a selection control signal to the switching circuit according to the analog signal characteristics. The second detection circuit is used for providing the second control signal to the switching circuit according to the digital signal characteristics. The switching circuit is used for outputting one of the first control signal and the second control signal to the modulation circuit according to the selection control signal.

In an exemplary embodiment of the invention, the switching circuit receives the first control signal through a first input terminal and the second control signal through a second input terminal. The switching circuit conducts a first signal transmission path according to the selection control signal to output the first control signal or conducts a second signal transmission path to output the second control signal.

In an exemplary embodiment of the invention, the digital signal characteristic comprises a count value, and the second detection circuit comprises a count circuit and a filter circuit. The counting circuit is used for updating the counting value according to the signal receiving state of the receiving end circuit. The filter circuit is connected to the counting circuit and is used for providing the second control signal to the switching circuit according to the counting value.

The exemplary embodiment of the invention also provides a data storage system, which comprises a processing device, a memory storage device and a signal redrive device. The signal redrive device is connected between the processing device and the memory storage device. The signal redrive device is used for receiving a first signal from the processing device through a receiving end circuit in the signal redrive device. The signal redrive device is further configured to detect an analog signal characteristic through the receiving end circuit and enter a first mode according to the analog signal characteristic. In the first mode, the signal redrive device is further configured to modulate the first signal and output a second signal. The signal redrive device is further configured to send the second signal to the memory storage device through a sending end circuit in the signal redrive device. The signal redrive device is further configured to detect a digital signal characteristic through the receiver circuit and switch from the first mode to the second mode according to the digital signal characteristic.

In an exemplary embodiment of the invention, the modulation circuit in the signal redrive device is disabled in the second mode.

In an exemplary embodiment of the present invention, the signal redrive device is further configured to: outputting a first control signal to a modulation circuit in the signal redrive device according to the analog signal characteristics, wherein the modulation circuit is used for modulating the first signal, and the first control signal is used for triggering the modulation circuit to enter the first mode; and outputting a second control signal to the modulation circuit according to the digital signal characteristics, wherein the second control signal is used for triggering the modulation circuit to switch to the second mode.

In an exemplary embodiment of the present invention, the signal redrive device is further configured to: providing a selection control signal to a switching circuit in the signal redrive device according to the analog signal characteristics; providing the second control signal to the switching circuit according to the digital signal characteristics; and outputting one of the first control signal and the second control signal to the modulation circuit through the switching circuit according to the selection control signal.

In an exemplary embodiment of the present invention, the operation of outputting the one of the first control signal and the second control signal to the modulation circuit through the switching circuit according to the selection control signal includes: receiving the first control signal through a first input end of the switching circuit; receiving the second control signal through a second input end of the switching circuit; and switching on a first signal transmission path of the switching circuit according to the selection control signal to output the first control signal or switching on a second signal transmission path of the switching circuit to output the second control signal.

In an exemplary embodiment of the present invention, the digital signal feature includes a count value, and the operation of outputting one of the first control signal and the second control signal to the modulation circuit through the switching circuit according to the selection control signal includes: updating the count value according to the signal receiving state of the receiving end circuit; and providing the second control signal to the switching circuit according to the count value.

In an exemplary embodiment of the present invention, the operation of providing the second control signal to the switching circuit according to the count value includes: and providing the second control signal to the switching circuit in response to the count value reaching a threshold value.

Exemplary embodiments of the present invention further provide a mode control method for a signal redrive device. The mode control method comprises the following steps: receiving a first signal through a receiving end circuit of the signal redrive device; detecting analog signal characteristics by the receiver circuit; entering a first mode based on the analog signal characteristic; in the first mode, modulating the first signal and outputting a second signal; transmitting the second signal through a transmitting end circuit of the signal redrive device; detecting digital signal characteristics through the receiving end circuit; and switching from the first mode to a second mode based on the digital signal characteristics.

In an exemplary embodiment of the present invention, the power consumption of the signal redrive device operating in the first mode is higher than the power consumption of the signal redrive device operating in the second mode.

In an exemplary embodiment of the present invention, the mode control method further includes: in the second mode, the modulation circuit in the signal redrive device is disabled.

In an exemplary embodiment of the invention, the analog signal characteristic reflects whether the first signal is present.

In an exemplary embodiment of the invention, the digital signal characteristic reflects a cumulative vanishing time of the first signal.

In an exemplary embodiment of the present invention, the mode control method further includes: outputting a first control signal to a modulation circuit in the signal redrive device according to the analog signal characteristics, wherein the modulation circuit is used for modulating the first signal, and the first control signal is used for triggering the modulation circuit to enter the first mode; and outputting a second control signal to the modulation circuit according to the digital signal characteristics, wherein the second control signal is used for triggering the modulation circuit to switch to the second mode.

In an exemplary embodiment of the present invention, the mode control method further includes: providing a selection control signal to a switching circuit in the signal redrive device according to the analog signal characteristics; providing the second control signal to the switching circuit according to the digital signal characteristics; and outputting one of the first control signal and the second control signal to the modulation circuit through the switching circuit according to the selection control signal.

In an exemplary embodiment of the present invention, the step of outputting the one of the first control signal and the second control signal to the modulation circuit through the switching circuit according to the selection control signal includes: receiving the first control signal through a first input end of the switching circuit; receiving the second control signal through a second input end of the switching circuit; and switching on a first signal transmission path of the switching circuit according to the selection control signal to output the first control signal or switching on a second signal transmission path of the switching circuit to output the second control signal.

In an exemplary embodiment of the present invention, the digital signal feature includes a count value, and the step of outputting the one of the first control signal and the second control signal to the modulation circuit through the switching circuit according to the selection control signal includes: updating the count value according to the signal receiving state of the receiving end circuit; and providing the second control signal to the switching circuit according to the count value.

In an exemplary embodiment of the present invention, the step of providing the second control signal to the switching circuit according to the count value includes: and providing the second control signal to the switching circuit in response to the count value reaching a threshold value.

Based on the above, after the receiving end circuit of the signal redrive device receives the first signal, the analog signal characteristic of the receiving end circuit can be detected and the signal redrive device can enter the first mode according to the analog signal characteristic. In the first mode, the signal redrive device may modulate the first signal and send the second signal through a transmit-side circuit of the signal redrive device. Thereafter, a digital signal characteristic of the receiver circuit may be detected, and the signal redrive device may switch from the first mode to the second mode based on the digital signal characteristic. Thus, the signal redrive device can achieve balance between power saving and maintaining signal transmission quality.

Drawings

FIG. 1 is a schematic diagram of a data storage system according to an exemplary embodiment of the present invention;

FIG. 2 is a schematic diagram of a signal redrive device according to an exemplary embodiment of the invention;

FIG. 3 is a schematic diagram of a signal redrive device according to an exemplary embodiment of the invention;

FIG. 4 is a signal timing diagram according to an exemplary embodiment of the present invention;

FIG. 5 is a schematic diagram of a host system, memory storage device, and input/output (I/O) device shown in accordance with an exemplary embodiment of the present invention;

FIG. 6 is a schematic diagram of a host system, memory storage device, and I/O device shown in accordance with an exemplary embodiment of the present invention;

FIG. 7 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the invention;

FIG. 8 is a schematic diagram of a memory storage device according to an exemplary embodiment of the invention;

fig. 9 is a flowchart illustrating a mode control method according to an exemplary embodiment of the present invention.

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

The following sets forth a number of exemplary embodiments to illustrate the invention, however the invention is not limited to the exemplary embodiments illustrated. And also between the exemplary embodiments, suitable combinations are allowed. The term "coupled" as used throughout this specification (including the claims) may refer to any direct or indirect means of coupling. For example, if a first device is described herein as being connected to a second device, it should be interpreted that the first device may be directly connected to the second device, or that the first device may be indirectly connected to the second device through other devices or some connection means. Further, the term "signal" may refer to at least one current, voltage, charge, temperature, data, or any other signal or signals.

FIG. 1 is a schematic diagram of a data storage system according to an exemplary embodiment of the present invention. Referring to fig. 1, a data storage system 10 includes a processing device 11, a memory storage device 12, and a signal redrive (re-driving) device 13. The processing means 11 may communicate with the memory storage means 12 via the signal redrive means 13. For example, the processing device 11 may send a signal to the memory storage device 12 through the signal redrive device 13 to access the memory storage device 12. For example, the processing device 11 may include a Central Processing Unit (CPU), or other programmable general purpose or special purpose microprocessor, digital signal processor (Digital Signal Processor, DSP), programmable controller, application specific integrated circuit (Application Specific Integrated Circuits, ASIC), programmable logic device (Programmable Logic Device, PLD), or other similar device or combination of devices.

The memory storage device 12 is used to store data in a nonvolatile manner. For example, the memory storage device 12 may include a USB flash drive, a memory card, a solid state drive (Solid State Drive, SSD), or an external storage device such as a wireless memory storage device. Alternatively, the memory storage device 12 may also include an embedded storage device such as an embedded multimedia card (embedded Multi Media Card, eMMC) or an embedded multi-chip package (embedded Multi Chip Package, eMCP) storage device.

The signal redrive device 13 is connected between the processing device 11 and the memory storage device 12. For example, the signal redrive device 13 may be disposed on a signal transfer path between the processing device 11 and the memory storage device 12. The signal redrive device 13 may be used to modulate signals passing between the processing device 11 and the memory storage device 12 to extend the transmission distance of the signals. For example, the signal redrive device 13 may include a signal repeater (Re-driver). For example, the signal redrive device 13 may perform high frequency compensation and/or low frequency compensation on the signal passed between the processing device 11 and the memory storage device 12 to improve the signal quality of this signal.

In an exemplary embodiment, the processing device 11, the memory storage device 12 and the signal redrive device 13 may be disposed on the motherboard 101 and communicate with each other through the motherboard 101. For example, the memory storage device 12 may be embedded on the motherboard 101 by an embedded mounting method. In an exemplary embodiment, the memory storage device 12 may be removably mounted on the motherboard 101 (i.e., electrically connected to the motherboard 101) via a high-speed peripheral component interconnect (Peripheral Component Interconnect Express, PCI Express) slot, a serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) slot, a universal serial bus (Universal Serial Bus, USB) slot, or a similar bus slot. In addition, in an exemplary embodiment, the memory storage device 12 may also be electrically connected to the motherboard 101 in an external manner and communicate with the signal redrive device 13 (and the processing device 11) through the motherboard 101.

It should be noted that in an exemplary embodiment, the signal redrive device 13 may also be used to modulate signals transferred between other types of electronic devices (or electronic circuits), and is not limited to application to the data storage system 10 of FIG. 1. Furthermore, in an exemplary embodiment, the signal redrive device 13 may also be included in the processing device 11 (or the memory storage device 12) of fig. 1, or other types of electronic devices (or electronic circuits).

Fig. 2 is a schematic diagram of a signal redrive device according to an exemplary embodiment of the invention. Referring to fig. 2, the signal redrive device 13 includes a receiving end circuit 21, a modulation circuit 22, a transmitting end circuit 23 and a mode control circuit 24. The receiving-side circuit 21 is connected to the signal input terminal IN. The transmitting-end circuit 23 is connected to the signal output end OUT. The modulation circuit 22 is connected between the receiving-side circuit 21 and the transmitting-side circuit 23. The mode control circuit 24 is connected to the receiving-side circuit 21 and the modulation circuit 22. It should be noted that the following description of the respective circuit blocks in the signal redrive device 13 is equivalent to the description of the functions that can be provided by the signal redrive device 13 as a whole.

The receiving-end circuit 21 may receive the signal S1 from the signal input terminal IN. The mode control circuit 24 detects an analog signal characteristic through the receiving end circuit 21 and controls the modulation circuit 22 to enter a specific mode (also referred to as a first mode) according to the analog signal characteristic. For example, the analog signal characteristic may reflect the signal reception state of the receiving-side circuit 21 based on the form of analog (or analog signal). In the first mode, the modulation circuit 22 modulates the signal S1 and outputs a signal (also referred to as a second signal) S2. For example, in the first mode, the modulation circuit 22 may modulate the signal S1 and output the signal S2 according to the modulation result of the signal S1. For example, modulation performed on signal S1 by modulation circuit 22 may include high frequency compensation and/or low frequency compensation of signal S1. The signal S2 may reflect the result of the compensation of the signal S1 by the modulation circuit 22. For example, the signal quality of signal S2 may be higher than the signal quality of signal S1. The transmitting-side circuit 23 may be configured to transmit the signal S2. In addition, the mode control circuit 24 can detect a digital signal characteristic through the receiving end circuit 21 and control the modulation circuit 22 to switch from the first mode to another mode (also referred to as a second mode) according to the digital signal characteristic. For example, the digital signal characteristic may reflect the signal reception state of the receiving-side circuit 21 based on a form of digital (or digital signal).

In an exemplary embodiment, the power consumption of the modulation circuit 22 operating in the first mode is higher than the power consumption of the modulation circuit 22 operating in the second mode. Similarly, the power consumption of the signal redrive device 13 operating in the first mode is higher than the power consumption of the signal redrive device 13 operating in the second mode.

In an exemplary embodiment, the first mode is also referred to as a normal operation mode. In the first mode, the modulation circuit 22 can normally operate to modulate the signal S1. In an exemplary embodiment, the second mode is also referred to as a power saving mode or a standby mode. In the second mode, the modulation circuit 22 may be in a power saving or standby state without modulating any signal.

In an exemplary embodiment, mode control circuit 24 may send a signal (also referred to as a control signal) CS to modulation circuit 22. The signal CS can be used to control the mode of operation of the modulation circuit 22. For example, when the signal CS includes a certain signal (also referred to as a first control signal), the modulation circuit 22 may operate in the first mode according to the first control signal. Alternatively, when the signal CS includes another signal (also referred to as a second control signal), the modulation circuit 22 may operate or switch to the second mode according to this second control signal.

In an exemplary embodiment, in the second mode (i.e., power saving mode or standby mode), the mode control circuit 24 may detect the analog signal characteristic through the receiving side circuit 21. For example, the analog signal characteristic may reflect in analog form whether signal S1 is present. In response to the analog signal characteristic meeting a particular condition (also referred to as a first condition), mode control circuit 24 may control modulation circuit 22 to switch from the second mode to the first mode (i.e., normal operating mode) via signal CS. For example, the first condition reflects that the signal S1 is present (i.e., the receiving-side circuit 21 has the received signal S1). In the first mode (or upon entering the first mode), the modulation circuit 22 may be enabled (e.g., awake) to modulate the signal S1 and output the signal S2. Furthermore, if the analog signal characteristic does not meet the first condition (indicating that the receiving end circuit 21 does not receive the signal S1), the mode control circuit 24 may control the modulation circuit 22 to maintain in the second mode.

In an exemplary embodiment, in the first mode (i.e., normal operation mode), the mode control circuit 24 may detect the digital signal characteristics through the receiver circuit 21. For example, the digital signal characteristic may reflect the cumulative vanishing time of the signal S1 in digital form. For example, the cumulative vanishing time of the signal S1 may be reflected in that the signal S1 is not received again by the receiving-side circuit 21 after a certain time elapses after the signal S1 vanishes from the receiving-side circuit 21. For example, the digital signal characteristic may reflect a length of time of the particular time. In response to the digital signal characteristic meeting a particular condition (also referred to as a second condition), mode control circuit 24 may control modulation circuit 22 to switch from the first mode to the second mode (i.e., a power saving mode or a standby mode) via signal CS. For example, the second condition reflects that the cumulative vanishing time of the signal S1 reaches a threshold value. In the second mode (or upon entering the second mode), the modulation circuit 22 may be disabled and wait to wake up again. In addition, if the digital signal characteristic does not meet the second condition (indicating that the cumulative vanishing time of the signal S1 does not reach the threshold value), the mode control circuit 24 may control the modulation circuit 22 to maintain in the first mode.

From another perspective, the mode control circuit 24 can continuously detect the analog signal characteristic through the receiving end circuit 21 while the modulation circuit 22 is in the power saving mode or the standby mode. The analog signal characteristic may reflect whether the receiving side circuit 21 currently receives a new signal S1. At a certain point in time, if the receiving end circuit 21 receives a new signal S1, the mode control circuit 24 may determine that the analog signal characteristic meets the first condition. In response to the analog signal characteristic meeting the first condition, mode control circuit 24 may wake up modulation circuit 22 and control modulation circuit 22 to enter a normal operating mode. In the normal operation mode, the modulation circuit 22 may continuously modulate the signal S1 until the receiving end circuit 21 does not receive the signal S1 any more.

In other words, according to the analog signal characteristic, the mode control circuit 24 can wake up the modulation circuit 22 to process the signal S1 once the receiving end circuit 21 receives the new signal S1. Therefore, the wake-up efficiency of the modulation circuit 22 can be effectively improved, and the specific information carried in the signal S1 is prevented from being missed due to the fact that the modulation circuit 22 is awakened too late.

On the other hand, when the modulation circuit 22 is in the normal operation mode, the mode control circuit 24 may continuously detect the digital signal characteristics through the receiving end circuit 21. The digital signal characteristic may reflect that the receiving-side circuit 21 has not received a new signal S1 for a certain time. At a certain point in time, if the specific time (i.e. the cumulative vanishing time of the signal S1) reaches a threshold value, the mode control circuit 24 may determine that the digital signal characteristic meets the second condition. In response to the digital signal characteristic meeting the second condition, the mode control circuit 24 may control the modulation circuit 22 to enter a power saving mode or a standby mode to save power consumption of the modulation circuit 22 (or the signal redrive device 13).

That is, depending on the digital signal characteristics, the mode control circuit 24 may allow the modulation circuit 22 to enter the power saving mode or the standby mode (only) after the receiving-side circuit 21 does not receive the new signal S1 for a certain period of time. Therefore, the modulation circuit 22 can enter the energy-saving mode or the standby mode at the correct timing point as far as possible, and the probability that the modulation circuit 22 is repeatedly switched between waking up and sleeping in a short time is reduced.

Fig. 3 is a schematic diagram of a signal redrive device according to an exemplary embodiment of the invention. Referring to fig. 3, the signal redrive device 30 includes a receiving end circuit 31, a modulation circuit 32, a transmitting end circuit 33 and a mode control circuit 34. It should be noted that the receiving end circuit 31, the modulation circuit 32, the transmitting end circuit 33 and the mode control circuit 34 may be the same as or similar to the receiving end circuit 21, the modulation circuit 22, the transmitting end circuit 23 and the mode control circuit 24 in fig. 2, respectively.

The receiving-end circuit 31 may include receiving terminals rx_p and rx_n. The receiving terminals rx_p and rx_n can be used to receive the signal S1 with quadrature signals. The impedance elements R1 and R2 may provide termination (termination) impedance to the receive terminals rx_p and rx_n.

The modulation circuit 32 includes modulation elements 321 to 323. The modulation elements 321 to 323 are used for modulating the signal S1 and outputting the signal S2. For example, the modulation elements 321-323 may include a continuous time linear equalizer (Continuous Time Linear Equalization, CTLE), a variable gain amplifier (Variable Gain Amplifier, VGA), and/or a modulation driver (modulation drive). It should be noted that the invention is not limited to the total number and types of the modulation elements 321-323.

The transmit-side circuit 33 may include transmit terminals tx_p and tx_n. The transmit terminals tx_p and tx_n may be used to transmit the signal S2 with quadrature signals. The impedance elements R3 and R4 may provide termination impedance to the transmit terminals tx_p and tx_n.

The mode control circuit 34 is connected to the receiver circuit 31 and the modulation circuit 32. The mode control circuit 34 may detect the analog signal characteristic and/or the digital signal characteristic through the receiving end circuit 31 and adjust the waveform of the signal CS according to the detection result to output the signal CS. The output signal CS may be used to control the modulation circuit 32 to enter the first mode (i.e., normal operation mode) or the second mode (i.e., power saving mode or standby mode). For example, in an exemplary embodiment, the signal CS (i.e., the first control signal) for triggering the modulation circuit 32 to enter the first mode may be at logic high, and the signal CS (i.e., the second control signal) for triggering the modulation circuit 32 to enter the second mode may be at logic low, but the invention is not limited thereto.

In an exemplary embodiment, mode control circuit 34 may output signal CS including a first control signal to modulation circuit 32 based on the analog signal characteristic to trigger or control modulation circuit 32 to enter the first mode. After the modulation circuit 32 enters the first mode, the mode control circuit 34 may adjust the waveform of the control signal CS according to the digital signal characteristics and output a signal CS including a second control signal to the modulation circuit 32 to trigger or control the modulation circuit 32 to switch to the second mode.

In an exemplary embodiment, the mode control circuit 34 may include a detection circuit (also referred to as a first detection circuit) 341, a detection circuit (also referred to as a second detection circuit) 342, and a switching circuit 343. The detection circuit 341 is connected to the receiving-end circuit 31. The detection circuit 342 is connected to the detection circuit 341. The switching circuit 343 is connected to the detecting circuit 341, the detecting circuit 342, and the modulating circuit 32.

The detection circuit 341 may be configured to detect the analog signal characteristic through the receiving-side circuit 31. The detection circuit 341 may provide a signal (also referred to as a selection control signal) CS (0) to the switching circuit 343 according to the analog signal characteristics. For example, signal CS (0) may reflect whether the analog signal characteristic meets the first condition. For example, signal CS (0) may be at logic high in response to the analog signal characteristic meeting the first condition (e.g., receiving end circuit 31 has received signal S1). Alternatively, signal CS (0) may be at logic low in response to the analog signal characteristic not meeting the first condition (e.g., signal S1 is not received by receiver circuit 31). For example, the detection circuit 341 may include an Analog Squelch (Analog Squelch) 3411. In an exemplary embodiment, the detection circuit 341 is also referred to as an analog detector or an analog feature detector.

The detection circuit 342 may be configured to detect the digital signal characteristics through the receiver circuit 31 (and the detection circuit 341). The detection circuit 342 may provide the signal CS (2) to the switching circuit 343 according to the digital signal characteristics. For example, signal CS (2) may reflect whether the digital signal characteristic meets the second condition. For example, signal CS (2) may be at logic low in response to the digital signal characteristic meeting the second condition (e.g., the cumulative vanishing time of signal S1 reaching a threshold value). At this point, the signal CS (2) at logic low may be considered as an entrainment second control signal. Alternatively, signal CS (2) may be at logic high in response to the digital signal characteristic not meeting the second condition (e.g., the cumulative vanishing time of signal S1 does not reach a threshold value). At this time, the signal CS (2) at logic high may be regarded as the second control signal is not entrained. In an exemplary embodiment, the detection circuit 342 is also referred to as a digital detector or a digital feature detector.

In an exemplary embodiment, the detection circuit 342 may include a low-speed oscillator 3421, a counting circuit 3422, and a filtering circuit 3423. The low-speed oscillator 3421 is used for generating the clock signal CK. The frequency of the clock signal CK may be lower than the frequency of the signal S1. In other words, in an exemplary embodiment, assuming that the signal S1 is a high-speed signal, the clock signal CK may be a low-speed clock signal.

The counter circuit 3422 is connected to the detection circuit 341 and the low-speed oscillator 3421. The counting circuit 3422 may update a count value CNT according to the signal receiving state of the receiving-side circuit 31. For example, the output of the detection circuit 341 may reflect the signal reception state of the receiving-end circuit 31. The counter circuit 3422 may sample the output of the detection circuit 341 using the clock signal CK. The counting circuit 3422 may update the count value CNT according to the sampling result. The count value CNT may reflect the cumulative vanishing time of the signal S1.

The filter circuit 3423 is connected to the detection circuit 341, the counter circuit 3422, and the switching circuit 343. The filter circuit 3423 may provide the signal CS (2) with or without the second control signal to the switching circuit 343 according to the count value CNT. For example, in response to the count value CNT not reaching a threshold, the filter circuit 3423 may provide the signal CS (2) without the second control signal to the switching circuit 343. Alternatively, in response to the count value CNT reaching the threshold value, the filter circuit 3423 may provide the signal CS (2) with the second control signal to the switching circuit 343.

The switching circuit 343 is configured to receive the signals CS (0), CS (1), and CS (2) and output the signal CS. For example, the switching circuit 343 may receive the signal CS (1) through one input (also referred to as a first input) and the signal CS (2) through the other input (also referred to as a second input). Wherein the signal CS (1) may entrain the first control signal and the signal CS (2) may entrain or not entrain the second control signal. For example, the signal CS (1) may be used to continuously provide the first control signal to the switching circuit 343, while the signal CS (2) may be used to provide the second control signal to the switching circuit 343 at a specific point in time (e.g., when the digital signal characteristics meet the second condition). In addition, the switching circuit 343 can output a signal CS including one of the signals CS (1) and CS (2) to the modulation circuit 32 according to the signal CS (0). For example, the signal CS (0) can be used to control the signal transmission path of the switching circuit 343.

In an exemplary embodiment, the switching circuit 343 may turn on a signal transmission path (also referred to as a first signal transmission path) between the first input terminal and the output terminal of the switching circuit 343 according to the signal CS (0) to output the signal CS (1) to the modulation circuit 32. Alternatively, in an exemplary embodiment, the switching circuit 343 may turn on another signal transmission path (also referred to as a second signal transmission path) between the second input terminal and the output terminal of the switching circuit 343 according to the signal CS (0) to output the signal CS (2) to the modulation circuit 32. For example, the switching circuit 343 may include a multiplexer 3431.

In an exemplary embodiment, the detection circuit 342 (or the counting circuit 3422) to detect the digital signal feature may sample a signal (e.g., the signal S1 or the output of the detection circuit 341) according to the clock signal CK. For example, the detection circuit 342 (or the counting circuit 3422) may perform double sampling of the signal according to the rising edge and the falling edge of the clock signal CK. However, the detection circuit 341 for detecting the analog signal features does not sample any signal (including the signal S1) according to the clock signal CK, and does not perform the double sampling according to the rising edge and the falling edge of the clock signal CK.

In an exemplary embodiment, when the receiving-side circuit 31 receives the signal S1, the detecting circuit 341 may detect that the analog signal characteristic meets the first condition. In response to the analog signal characteristic meeting the first condition, the detection circuit 341 may output a signal CS (0) at logic high. The signal CS (0) at logic high may be used to turn on the first signal transfer path of the switching circuit 343. The switching circuit 343 may turn on the first signal transfer path according to the signal CS (0) at logic high and output the signal CS (1) entraining the first control signal as the signal CS to the modulation circuit 32. The modulation circuit 32 may enter the first mode in response to the signal CS, i.e., the signal CS (1) carrying the first control signal. The modulation circuit 32 may modulate the signal S1 and output the signal S2 in the first mode.

In an exemplary embodiment, when the receiving-side circuit 31 does not receive the signal S1, the detecting circuit 341 may detect that the analog signal characteristic does not meet the first condition. In response to the analog signal characteristic not meeting the first condition, the detection circuit 341 may change the waveform of the signal CS (0), e.g., output the signal CS (0) at a logic low. The signal CS (0) at logic low may be used to turn on the second signal transfer path of the switching circuit 343. The switching circuit 343 may turn on the second signal transfer path according to the signal CS (0) at logic low and output the signal CS (2) as the signal CS to the modulation circuit 32.

In an exemplary embodiment, the cumulative vanishing time of the signal S1 is short at the initial stage when the signal S1 is not received by the receiving-side circuit 31. Therefore, at an early stage when the receiving-end circuit 31 does not receive the signal S1, the detecting circuit 342 may detect that the digital signal characteristic does not meet the second condition (e.g. the count value CNT does not reach the threshold value). In response to the digital signal characteristic not meeting the second condition, the detection circuit 342 may output a signal CS (2) that does not entrain the second control signal. In this case (i.e., the signal CS (2) is not entrained with the second control signal), the modulation circuit 32 is continuously operated in the first mode even if the switching circuit 343 outputs the signal CS (2) to the modulation circuit 32.

In an exemplary embodiment, when the receiving-side circuit 31 does not receive the signal S1 after a period of time, the detecting circuit 342 may detect that the digital signal feature meets the second condition (e.g. the count value CNT reaches the threshold value) if the detecting circuit 341 continuously detects that the analog signal feature does not meet the first condition. In response to the digital signal characteristic meeting the second condition, the detection circuit 342 may output a signal CS (2) entraining a second control signal to the modulation circuit 32. In this case (i.e. the signal CS (2) is entrained with the second control signal and the switching circuit 343 continuously outputs the signal CS (2) to the modulation circuit 32), the modulation circuit 32 can switch to the second mode.

Fig. 4 is a signal timing diagram according to an exemplary embodiment of the present invention. Referring to fig. 3 and 4, it is assumed that the modulation circuit 32 is in the second mode (i.e. the power saving mode or the standby mode) before the time point T (0). At time T (0), the receiving-side circuit 31 receives the signal S1. Therefore, after the time point T (0), the modulation circuit 32 is switched to the first mode (i.e. the normal operation mode) to modulate the signal S1, and the output circuit 33 continuously outputs the signal S2 generated by modulating the signal S1.

Between the time points T (1) to T (2), the receiving-side circuit 31 does not receive the signal S1. However, between the time points T (1) to T (2), the count value CNT that is continuously increased does not reach the threshold value THR. Therefore, between the time points T (1) to T (2), the modulation circuit 32 is maintained in the first mode (i.e. the normal operation mode) even if the receiving end circuit 31 does not receive the signal S1. Further, at the time point T (2), the count value CNT may be reset (reset).

Between the time points T (2) and T (3), the receiving-end circuit 31 continuously receives the signal S1. Meanwhile, the modulation circuit 32 continuously modulates the signal S1 in the first mode (i.e. the normal operation mode), and the output terminal circuit 33 continuously outputs the signal S2.

Between the time points T (3) to T (4), the receiving-side circuit 31 does not receive the signal S1. After the time point T (3), the count value CNT continuously increases as the cumulative vanishing time of the signal S1 increases. In particular, at the time point T (4), the count value CNT that is continuously increased reaches the threshold value. Thus, after the time point T (4), the modulation circuit 32 is switched back to the second mode (i.e., the power saving mode or the standby mode) to wait to be awakened the next time the signal S1 is received. Further, after the time point T (4), the count value CNT may be reset.

In other words, according to the exemplary embodiments of fig. 1 to 4, the signal redrive device (or modulation circuit) may enter the first mode (i.e., the normal operation mode) according to the analog signal characteristics, and the analog signal characteristics reflect whether the signal S1 to be processed is received in an analog form. Therefore, the wake-up efficiency of the signal redrive device (or the modulation circuit) is effectively improved.

Furthermore, according to the exemplary embodiments of fig. 1-4, the signal redrive device (or modulation circuit) may switch from the first mode to the second mode (i.e., the power saving mode or the standby mode) according to the digital signal characteristics, and the digital signal characteristics reflect the cumulative vanishing time of the signal S1 in digital form (e.g., the count value CNT of fig. 3 and 4). Thus, the signal redrive device (or the modulation circuit) can enter the energy-saving mode or the standby mode at the correct timing point as far as possible (for example, delay the time point of entering the energy-saving mode or the standby mode).

FIG. 5 is a schematic diagram of a host system, memory storage device, and input/output (I/O) device, according to an exemplary embodiment of the invention. FIG. 6 is a schematic diagram of a host system, memory storage device, and I/O device according to an exemplary embodiment of the invention.

Referring to fig. 5 and 6, the host system 51 generally includes a processor 511, a random access memory (random access memory, RAM) 512, a Read Only Memory (ROM) 513, and a data transmission interface 514. The processor 511, the random access memory 512, the read only memory 513, and the data transmission interface 514 are all connected to a system bus 510.

In the present exemplary embodiment, host system 51 is coupled to memory storage device 50 via data transfer interface 514. For example, host system 51 may store data to memory storage device 50 or read data from memory storage device 50 through data transfer interface 514. Further, the host system 51 is connected to the I/O device 52 via a system bus 510. For example, host system 51 may transmit output signals to I/O device 52 or receive input signals from I/O device 52 via system bus 510.

In an exemplary embodiment, the processor 511, the random access memory 512, the read only memory 513, and the data transfer interface 514 may be disposed on the motherboard 60 of the host system 51. The number of data transfer interfaces 514 may be one or more. The motherboard 60 may be connected to the memory storage device 50 by a wired or wireless means through the data transfer interface 514. The memory storage 50 may be, for example, a USB flash disk 601, a memory card 602, a Solid State Disk (SSD) 603, or a wireless memory storage 604. The wireless memory storage 604 may be, for example, a near field communication (Near Field Communication, NFC) memory storage, a wireless fidelity (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (such as iBeacon) or the like based on a wide variety of wireless communication technologies. In addition, the motherboard 60 may also be connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 605, a network interface card 606, a wireless transmission device 607, a keyboard 608, a screen 609, and a speaker 610 through a system bus 510. For example, in an exemplary embodiment, the motherboard 60 may access the wireless memory storage device 604 via the wireless transmission device 607.

In an exemplary embodiment, the host system referred to is any system that can cooperate with substantially memory storage devices to store data. Although the host system is described in the exemplary embodiment, fig. 7 is a schematic diagram of the host system and the memory storage device according to an exemplary embodiment of the invention. Referring to fig. 7, in another exemplary embodiment, the host system 71 may be a system such as a Digital camera, a video camera, a communication device, an audio player, a video player or a tablet computer, and the memory storage device 70 may be a Secure Digital (SD) card 72, a Compact Flash (CF) card 73 or an embedded memory storage device 74. The embedded memory device 74 includes embedded memory devices of various types such as embedded multimedia card (embedded Multi Media Card, eMMC) 741 and/or embedded multi-chip package (embedded Multi Chip Package, eMMC) memory device 742 that directly connect the memory module to a substrate of the host system.

Fig. 8 is a schematic diagram of a memory storage device according to an exemplary embodiment of the invention. Referring to fig. 8, the memory storage device 80 includes a connection interface unit 801, a memory control circuit unit 802, and a rewritable nonvolatile memory module 803.

The connection interface unit 801 is used to connect the memory storage device 80 to a host system. In the present exemplary embodiment, the connection interface unit 801 is compatible with SATA standards. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 801 may be a Memory Stick (MS) interface standard, an MCP interface standard, an MMC interface standard, an eMMC interface standard, a universal flash Memory (Universal Flash Storage, UFS) interface standard, an eMCP interface standard, a CF interface standard, an integrated drive electronics interface (Integrated Device Electronics, IDE) standard, or other suitable standard, which conform to the parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard, the institute of electrical and electronics engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 standard, the PCI Express standard, the USB standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the universal flash Memory (Universal Flash Storage, UFS) interface standard, the emc interface standard, the CF interface standard, the integrated drive electronics interface (Integrated Device Electronics, IDE) standard, or other suitable standard. The connection interface unit 801 may be packaged in one chip with the memory control circuit unit 802, or the connection interface unit 801 may be disposed outside a chip including the memory control circuit unit 802.

The memory control circuit unit 802 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 803 according to instructions of the host system.

The rewritable nonvolatile memory module 803 is connected to the memory control circuit unit 802 and is used to store data written by the host system. The rewritable nonvolatile memory module 803 may be a single-Level memory Cell (Single Level Cell, SLC) NAND type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a dual-Level memory Cell (MLC) NAND type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a third-Level memory Cell (Triple Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad-Level memory Cell (QLC) NAND type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.

Each memory cell in the rewritable nonvolatile memory module 803 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, there is a charge trapping layer between the control gate (control gate) and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. By applying the read voltage, it can be determined which memory state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In the present exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 803 form a plurality of physical program units, and the physical program units form a plurality of physical erase units. Specifically, memory cells on the same word line constitute one or more physical programming units. If each memory cell can store more than 2 bits, the physical programming units on the same word line can be classified into at least a lower physical programming unit and an upper physical programming unit. For example, the least significant bit (Least Significant Bit, LSB) of a memory cell is the lower physical program cell and the most significant bit (Most Significant Bit, MSB) of a memory cell is the upper physical program cell. In general, in MLC NAND-type flash memory, the writing speed of the lower physical programming unit is greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than the reliability of the upper physical programming unit.

In the present exemplary embodiment, the physical programming unit is the minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. For example, the physical programming unit is a physical page (page) or a physical sector (sector). If the physical programming units are physical pages, the physical programming units typically include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region is used for storing system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit region may also include 8, 16 or a greater or lesser number of physical sectors, and the size of each physical sector may also be greater or lesser. On the other hand, a physical erase unit is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased together. For example, the physical erased cells are physical blocks (blocks).

Fig. 9 is a flowchart illustrating a mode control method according to an exemplary embodiment of the present invention. Referring to fig. 9, in step S901, a first signal is received by a receiving end circuit of a signal redrive device. In step S902, analog signal characteristics are detected by the receiver circuit. In step S903, a first mode is entered based on the analog signal characteristic. In step S904, in the first mode, the first signal is modulated and a second signal is output. In step S905, the second signal is transmitted through a transmitting-side circuit of the signal redrive device. In step S906, a digital signal characteristic is detected by the receiving-end circuit. In step S907, switching from the first mode to a second mode according to the digital signal characteristics.

However, the steps in fig. 9 are described in detail above, and will not be described again here. It should be noted that each step in fig. 9 may be implemented as a plurality of program codes or circuits, which is not limited by the present invention. In addition, the method of fig. 9 may be used with the above exemplary embodiment, or may be used alone, and the present invention is not limited thereto.

In summary, in the exemplary embodiment of the invention, the signal re-driving device (or the modulation circuit) is awakened according to the analog signal detection mode, and the signal re-driving device (or the modulation circuit) is re-entered into the power saving mode or the standby mode in combination with the digital signal detection mode. Therefore, the signal redrive device can achieve better balance between power saving and signal transmission quality maintenance.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A signal redrive device, comprising:

a receiving-side circuit;

a modulation circuit connected to the receiving end circuit;

a transmitting-side circuit connected to the modulation circuit; and

a mode control circuit connected to the receiving end circuit and the modulation circuit,

wherein the receiving end circuit is used for receiving a first signal,

the mode control circuit is used for detecting the analog signal characteristic through the receiving end circuit and controlling the modulation circuit to enter a first mode according to the analog signal characteristic, wherein the analog signal characteristic reflects whether the first signal exists,

in the first mode, the modulation circuit is used for modulating the first signal and outputting a second signal,

the transmitting end circuit is used for transmitting the second signal and

the mode control circuit is further configured to detect a digital signal characteristic through the receiving end circuit and control the modulation circuit to switch from the first mode to the second mode according to the digital signal characteristic,

wherein the digital signal characteristic reflects an accumulated vanishing time of the first signal, and the second mode is a power saving mode or a standby mode,

Wherein controlling the operation of the modulation circuit to enter the first mode according to the analog signal characteristic comprises:

outputting a first control signal to the modulation circuit according to the analog signal characteristics, wherein the first control signal is used for triggering the modulation circuit to enter the first mode, and

controlling the modulation circuit to switch from the first mode to the second mode according to the digital signal characteristic comprises:

and outputting a second control signal to the modulation circuit according to the digital signal characteristics, wherein the second control signal is used for triggering the modulation circuit to switch to the second mode.

2. The signal redrive device of claim 1, wherein the power consumption of the modulation circuit operating in the first mode is higher than the power consumption of the modulation circuit operating in the second mode.

3. The signal redrive device of claim 1, wherein the modulation circuit is disabled in the second mode.

4. The signal redrive device of claim 1, wherein the mode control circuit comprises:

a first detection circuit connected to the receiving-side circuit;

a second detection circuit connected to the first detection circuit; and

A switching circuit connected to the first detection circuit, the second detection circuit and the modulation circuit,

wherein the first detection circuit is used for providing a selection control signal to the switching circuit according to the analog signal characteristic,

the second detection circuit is used for providing the second control signal to the switching circuit according to the digital signal characteristics, and

the switching circuit is used for outputting one of the first control signal and the second control signal to the modulation circuit according to the selection control signal.

5. The signal redrive device of claim 4, wherein the switching circuit receives the first control signal through a first input and the second control signal through a second input, and

the switching circuit conducts a first signal transmission path according to the selection control signal to output the first control signal or conducts a second signal transmission path to output the second control signal.

6. The signal redrive device of claim 4, wherein the digital signal characteristics comprise count values, and the second detection circuit comprises:

the counting circuit is used for updating the count value according to the signal receiving state of the receiving end circuit; and

And the filter circuit is connected to the counting circuit and is used for providing the second control signal to the switching circuit according to the counting value.

7. The signal redrive device of claim 6, wherein the operation of providing the second control signal to the switching circuit according to the count value comprises:

and providing the second control signal to the switching circuit in response to the count value reaching a threshold value.

8. A data storage system, comprising:

a processing device;

a memory storage device; and

a signal redrive device connected between the processing device and the memory storage device,

wherein the signal redrive device is configured to receive a first signal from the processing device through a receiver circuit in the signal redrive device,

the signal redrive device is further configured to detect an analog signal characteristic through the receiver circuit and enter a first mode according to the analog signal characteristic, wherein the analog signal characteristic reflects whether the first signal is present,

in the first mode, the signal redrive device is further configured to modulate the first signal and output a second signal,

The signal redrive device is further configured to send the second signal to the memory storage device through a transmitting end circuit in the signal redrive device, an

The signal redrive device is further configured to detect a digital signal characteristic via the receiver circuit and switch from the first mode to the second mode based on the digital signal characteristic,

wherein the signal redrive device is further configured to:

outputting a first control signal to a modulation circuit in the signal redrive device according to the analog signal characteristics, wherein the modulation circuit is used for modulating the first signal, and the first control signal is used for triggering the modulation circuit to enter the first mode; and

9. The data storage system of claim 8, wherein the power consumption of the signal redrive device operating in the first mode is higher than the power consumption of the signal redrive device operating in the second mode.

10. The data storage system of claim 8, wherein the modulation circuitry in the signal redrive device is disabled in the second mode.

11. The data storage system of claim 8, wherein the signal redrive device is further to:

providing a selection control signal to a switching circuit in the signal redrive device according to the analog signal characteristics;

providing the second control signal to the switching circuit according to the digital signal characteristics; and

and outputting one of the first control signal and the second control signal to the modulation circuit through the switching circuit according to the selection control signal.

12. The data storage system of claim 11, wherein outputting the one of the first control signal and the second control signal to the modulation circuit through the switching circuit according to the selection control signal comprises:

receiving the first control signal through a first input end of the switching circuit;

receiving the second control signal through a second input end of the switching circuit; and

and switching on a first signal transmission path of the switching circuit according to the selection control signal to output the first control signal or switching on a second signal transmission path of the switching circuit to output the second control signal.

13. The data storage system of claim 11, wherein the digital signal characteristic comprises a count value, and outputting one of the first control signal and the second control signal to the modulation circuit through the switching circuit according to the select control signal comprises:

updating the count value according to the signal receiving state of the receiving end circuit; and

and providing the second control signal to the switching circuit according to the count value.

14. The data storage system of claim 13, wherein providing the second control signal to the switching circuit in accordance with the count value comprises:

15. A mode control method for a signal redrive device, the mode control method comprising:

receiving a first signal through a receiving end circuit of the signal redrive device;

detecting analog signal characteristics by the receiver circuit;

entering a first mode according to the analog signal characteristic, wherein the analog signal characteristic reflects whether the first signal is present;

In the first mode, modulating the first signal and outputting a second signal;

transmitting the second signal through a transmitting end circuit of the signal redrive device;

detecting digital signal characteristics through the receiving end circuit; and

switching from the first mode to a second mode based on the digital signal characteristics,

wherein the digital signal characteristic reflects an accumulated vanishing time of the first signal and the second mode is an energy saving mode or a standby mode;

16. The mode control method of claim 15, wherein the power consumption of the signal redrive device operating in the first mode is higher than the power consumption of the signal redrive device operating in the second mode.

17. The mode control method according to claim 15, further comprising:

in the second mode, the modulation circuit in the signal redrive device is disabled.

18. The mode control method according to claim 15, further comprising:

19. The mode control method according to claim 18, wherein the operation of outputting the one of the first control signal and the second control signal to the modulation circuit through the switching circuit according to the selection control signal includes:

20. The mode control method of claim 18, wherein the digital signal characteristic includes a count value, and the step of outputting the one of the first control signal and the second control signal to the modulation circuit through the switching circuit according to the selection control signal includes:

21. The mode control method according to claim 20, wherein the step of providing the second control signal to the switching circuit according to the count value includes: