CN113644907B - D-latch built with common-gate complementary field effect transistors - Google Patents
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- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
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Abstract
The invention provides a D latch constructed by common gate complementary field effect transistors, which comprises a first complementary field effect transistor, a second complementary field effect transistor, a third complementary field effect transistor, a fourth complementary field effect transistor and a fifth complementary field effect transistor, thereby increasing the circuit integration level of the D latch.
Description
Technical Field
The invention relates to the technical field of latches, in particular to a D latch constructed by common-gate complementary field effect transistors.
Background
Complementary field-Effect transistors (CFETs) are three-dimensional electronic devices formed by vertically stacking field-Effect transistors (FieldEffectTransistor, FET) of complementary polarity. A CFET device is provided with an N-type field effect transistor (NFET) and a P-type field effect transistor (PFET) in the longitudinal direction, and the circuit is built by utilizing the CFET, so that the circuit integration level can be greatly increased, and the possibility is provided for realizing further miniaturization of an integrated circuit.
A D latch (datalatch) is a memory cell circuit that is sensitive to a pulse circuit and can change a memory state under a specific input pulse level. D-latches are widely used in integrated circuits, and are often used as storage elements of sequential circuits in digital circuits, which are an important component of various types of D-flip-flops, and latches are sometimes used as data registers in some arithmetic circuits.
The gate metal of the FET inside the CFET is vertically stacked, and it is easier to realize that the NFET and PFET share the same gate metal, and the NFET and PFET are controlled simultaneously by one gate, forming a common gate structure. Whereas in the vertical direction, the gate metals of NFETs and PFETs are physically isolated, which is difficult to process and design, so the CFET structure is preferred over the common gate structure. However, due to the nature of the sequential circuit, the gates of a set of NFETs and PFETs must be connected to opposite sequential control signals, resulting in the set of NFETs and PFETs not forming a common gate.
Accordingly, there is a need to provide a novel D latch constructed of common-gate complementary field effect transistors to solve the above-described problems in the prior art.
Disclosure of Invention
The invention aims to provide a D latch constructed by common-gate complementary field effect transistors, which increases the circuit integration level of the D latch.
To achieve the above object, the D latch of the present invention constructed of a common-gate complementary field effect transistor includes:
the first complementary field effect transistor is characterized by comprising a CG end, a PS end and a NS end, wherein the CG end of the first complementary field effect transistor is used for receiving external input data, the PS end of the first complementary field effect transistor is connected with a high potential, and the NS end of the first complementary field effect transistor is connected with a low potential;
the CG end of the second complementary field effect transistor is used for receiving a low potential signal cn or a high potential signal c controlled by time sequence, and the NS end of the second complementary field effect transistor is connected with the ND end of the first complementary field effect transistor;
the CG end of the third complementary field effect transistor is used for receiving a high potential signal c or a low potential signal cn controlled by time sequence, the PS end of the third complementary field effect transistor is connected with the PD end of the first complementary field effect transistor, and the PD end and the ND end of the third complementary field effect transistor are connected with the PD end and the ND end of the second complementary field effect transistor;
a fourth complementary field effect transistor, wherein the PS end of the fourth complementary field effect transistor is connected with a high potential, the PD end of the fourth complementary field effect transistor is connected with the PS end of the second complementary field effect transistor, the ND end of the fourth complementary field effect transistor is connected with the NS end of the third complementary field effect transistor, and the NS end of the fourth complementary field effect transistor is connected with a low potential; and
and the CG end of the fifth complementary field effect transistor is connected with the ND end of the third complementary field effect transistor, the PD end and the ND end of the fifth complementary field effect transistor are both connected with the CG end of the fourth complementary field effect transistor, the PS end of the fifth complementary field effect transistor is connected with a high potential, and the NS end of the fifth complementary field effect transistor is connected with a low potential.
The invention has the beneficial effects that: the D latch constructed by the common gate complementary field effect transistor comprises a first complementary field effect transistor, a second complementary field effect transistor, a third complementary field effect transistor, a fourth complementary field effect transistor and a fifth complementary field effect transistor, so that the circuit integration level of the D latch is increased.
Preferably, the first complementary field effect transistor is identical to the second complementary field effect transistor, the third complementary field effect transistor, the fourth complementary field effect transistor and the fifth complementary field effect transistor in structure.
Further preferably, the first complementary field effect transistor is a five-port device, the five ports of the first complementary field effect transistor are the CG terminal, the PS terminal, the PD terminal, the ND terminal and the NS terminal, the first complementary field effect transistor is internally integrated with a PFET and an NFET, the gate of the PFET and the gate of the NFET are connected to form the CG terminal of the first complementary field effect transistor together, the source of the PFET is the PS terminal of the first complementary field effect transistor, the drain of the PFET is the PD terminal of the first complementary field effect transistor, the drain of the NFET is the ND terminal of the first complementary field effect transistor, and the source of the NFET is the NS terminal of the first complementary field effect transistor.
Drawings
FIG. 1 is a circuit diagram of a D-latch constructed of common-gate complementary field effect transistors in accordance with the present invention;
FIG. 2 is an equivalent circuit diagram of a first complementary field effect transistor;
FIG. 3 is a circuit diagram of a first D-latch of the prior art;
FIG. 4 is a circuit diagram of a CMOS transistor of the first D-latch of FIG. 3;
fig. 5 is a circuit diagram of an equivalent CMOS transistor of fig. 1.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. Unless otherwise defined, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and the like means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof without precluding other elements or items.
In response to the problems with the prior art, embodiments of the present invention provide a D latch constructed from common-gate complementary field effect transistors. Referring to fig. 1, the D latch 100 constructed of common-gate complementary field effect transistors includes:
a first complementary field effect transistor 101, wherein a CG terminal of the first complementary field effect transistor 101 is used for receiving data, a PS terminal of the first complementary field effect transistor 101 is connected to a high potential, and a NS terminal of the first complementary field effect transistor 101 is connected to a low potential;
a second complementary field effect transistor 102, wherein a CG terminal of the second complementary field effect transistor 102 is configured to receive a low potential signal cn or a high potential signal c of a timing control, and an NS terminal of the second complementary field effect transistor 102 is connected to an ND terminal of the first complementary field effect transistor 101;
a third complementary field effect transistor 103, wherein a CG terminal of the third complementary field effect transistor 103 is configured to receive a high potential signal c or a low potential signal cn that is controlled by timing, a PS terminal of the third complementary field effect transistor 103 is connected to a PD terminal of the first complementary field effect transistor 101, and both a PD terminal and a ND terminal of the third complementary field effect transistor 103 are connected to a PD terminal and a ND terminal of the second complementary field effect transistor 102;
a fourth complementary field effect transistor 104, wherein a PS terminal of the fourth complementary field effect transistor 104 is connected to a high potential, a PD terminal of the fourth complementary field effect transistor 104 is connected to a PS terminal of the second complementary field effect transistor 102, a ND terminal of the fourth complementary field effect transistor 104 is connected to a NS terminal of the third complementary field effect transistor 103, and a NS terminal of the fourth complementary field effect transistor 104 is connected to a low potential; and
and a fifth complementary field effect transistor 105, wherein a CG terminal of the fifth complementary field effect transistor 105 is connected to an ND terminal of the third complementary field effect transistor 103, a PD terminal and an ND terminal of the fifth complementary field effect transistor 105 are both connected to a CG terminal of the fourth complementary field effect transistor 104, a PS terminal of the fifth complementary field effect transistor 105 is connected to a high potential, and a NS terminal of the fifth complementary field effect transistor 105 is connected to a low potential.
In some embodiments, when the CG of the second complementary field effect transistor 102 receives a low potential signal cn that is time-controlled, the CG of the third complementary field effect transistor 103 receives a high potential signal c that is time-controlled; when the CG of the second complementary field effect transistor 102 receives the high potential signal c controlled by the time-series control, the CG of the third complementary field effect transistor 103 receives the low potential signal cn controlled by the time-series control.
Referring to fig. 1, the CG terminal of the first complementary field effect transistor 101 is an external data input terminal of the D latch 100 constructed by the common-gate complementary field effect transistor, the ND terminal of the third complementary field effect transistor 103 is connected to one terminal of the first transmission line 1031, the PD terminal of the third complementary field effect transistor 103 is connected to one terminal of the second transmission line 1032, the other terminal of the second transmission line 1032 is connected to the first transmission line 1031 by the first sub-node 1033, the CG terminal of the fifth complementary field effect transistor 105 is connected to one terminal of the third transmission line 1051, the other terminal of the third transmission line 1051 is connected to the first transmission line 1031 by the second sub-node 1034, the second sub-node 1034 is located between the first sub-node 3 and the ND terminal of the third complementary field effect transistor 103, the third sub-node 1035 is disposed on the third transmission line 1051, and the third sub-node 1035 is used as the output terminal of the D latch 100 constructed by the common-gate complementary field effect transistor. Specifically, the first transmission line 1031 and the second transmission line 1032 may be different transmission lines or the same transmission line, and the first sub-node 1033 and the second sub-node 1034 may be different nodes or the same node, and only the PD end and ND end of the second complementary field effect transistor 102 and the PD end and ND end of the third complementary field effect transistor 103 need to be connected together, and the other end of the third transmission line 1051 may be connected to the PD end and ND end of the second complementary field effect transistor 102 and the PD end and ND end of the third complementary field effect transistor 103.
Referring to fig. 1, the ND terminal of the fifth complementary field effect transistor 105 is connected to one terminal of a fourth transmission line 1052, the PD terminal of the fifth complementary field effect transistor 105 is connected to one terminal of a fifth transmission line 1053, the CG terminal of the fourth complementary field effect transistor 104 is connected to one terminal of a sixth transmission line 1054, the other terminal of the fifth transmission line 1053 and the sixth transmission line 1054 are connected to a fourth sub-node 10531, the other terminal of the sixth transmission line 1054 and the fourth transmission line 1052 are connected to a fifth sub-node 10532, and the other terminal of the fourth transmission line 1052 serves as the Q output terminal of the D latch 100 constructed by the common gate complementary field effect transistor.
Specifically, the first complementary field Effect Transistor and the second complementary field Effect Transistor, the third complementary field Effect Transistor, the fourth complementary field Effect Transistor and the fifth complementary field Effect Transistor have the same structure, and are all Complementary Field Effect Transistors (CFET).
Referring to fig. 2, the first complementary field effect transistor has integrated therein a PFET 1011 and an NFET 1012, the gate of the PFET 1011 and the gate of the NFET 1012 are connected together to form a CG terminal (common gate) of the first complementary field effect transistor, the source of the PFET 1011 is a PS terminal (PFETSource) of the first complementary field effect transistor, the drain of the PFET 1011 is a PD terminal (PFETDrain) of the first complementary field effect transistor, the drain of the NFET 1012 is a ND terminal (NFETDrain) of the first complementary field effect transistor, and the source of the NFET 1012 is a NS terminal (NFETSource) of the first complementary field effect transistor, wherein the CG terminal of the first complementary field effect transistor is the common gate terminal of the PFET 1011 and the NFET 1012.
Fig. 3 is a circuit diagram of a first D latch of the prior art. Referring to fig. 3, the first D-latch 200 comprises a first tri-state inverter 201, an inverter 202 and a second tri-state inverter 203, wherein a first input end of the first tri-state inverter 201 is used as a D input end of the first D-latch for receiving data, a second input end of the first tri-state inverter 201 is used for receiving a low potential signal cn, a third input end of the first tri-state inverter 201 is used for receiving a high potential signal c, an output end of the first tri-state inverter 201 is connected with a first input end of the inverter 202 through a first wire 204, an output end of the inverter 202 is connected with one end of a second wire 205, the other end of the second wire 205 is used as a Q output end of the first D-latch, a first node 2051 is arranged on the second wire 205, the first node 2051 is connected with a first input end of the second tri-state inverter 203 through a third wire 206, a second input end of the second tri-state inverter 203 is used for receiving a high potential signal c, an output end of the third tri-state inverter 203 is connected with a fourth wire 207, a third input end of the third tri-state inverter 203 is connected with a fourth wire 207 as a fourth wire 207, and a third node 207 is arranged on the other end of the third wire 207 is connected with the third node 207.
In some embodiments, referring to fig. 3, the second input terminal of the first tri-state inverter 201 receives the low potential signal cn, the third input terminal of the first tri-state inverter 201 receives the high potential signal c, the second input terminal of the second tri-state inverter 203 receives the high potential signal c, the third input terminal of the second tri-state inverter 203 receives the low potential signal cn, or the second input terminal of the first tri-state inverter 201 receives the high potential signal c, the third input terminal of the first tri-state inverter 201 receives the low potential signal cn, the second input terminal of the second tri-state inverter 203 receives the high potential signal c, the Q output terminal and QN output terminal of the first D latch are unchanged when the first input terminal of the first tri-state inverter does not receive data, and the stored data content of the D latch remains unchanged.
In some embodiments, referring to fig. 3, the second input terminal of the first tri-state inverter 201 receives the low-level signal cn, the third input terminal of the first tri-state inverter 201 receives the high-level signal c, the second input terminal of the second tri-state inverter 203 receives the high-level signal c, the third input terminal of the second tri-state inverter 203 receives the low-level signal cn, when the first input terminal of the first tri-state inverter receives the low-level signal, the Q output terminal of the first D latch outputs the low-level signal, the QN output terminal of the first D latch outputs the high-level signal, and the function of the first D latch is to be set to a low level.
In some embodiments, referring to fig. 3, the second input terminal of the first tri-state inverter 201 receives the low-level signal cn, the third input terminal of the first tri-state inverter 201 receives the high-level signal c, the second input terminal of the second tri-state inverter 203 receives the high-level signal c, the third input terminal of the second tri-state inverter 203 receives the low-level signal cn, when the first input terminal of the first tri-state inverter receives the high-level signal, the Q output terminal of the first D latch outputs the high-level signal, the QN output terminal of the first D latch outputs the low-level signal, and the function of the first D latch is to be set high.
In some embodiments, the second D latch includes a first tri-state inverter, an inverter, and a second tri-state inverter, where a first input end of the first tri-state inverter is used as a D input end of the first D latch and is used to receive data, a second input end of the first tri-state inverter is used to receive a high potential signal cn, a third input end of the first tri-state inverter is used to receive a low potential signal cn, an output end of the first tri-state inverter is connected to a first input end of the inverter through a first line, an output end of the inverter is connected to one end of a second line, the other end of the second line is used as a Q output end of the first D latch, a first node is disposed on the second line, the first node is connected to a first input end of the second tri-state inverter through a third line, a second input end of the second tri-state inverter is used to receive the low potential signal cn, a third input end of the second tri-state inverter is used to receive the high potential signal cn, an output end of the first tri-state inverter is connected to one end of the second line, an output end of the second tri-state inverter is connected to a fourth line is disposed on the second line, a fourth line is disposed on the second line is connected to the other end of the second line, and the fourth line is disposed as a third node.
In some embodiments, the second input terminal of the first tri-state inverter receives the high potential signal c, the third input terminal of the first tri-state inverter receives the low potential signal cn, the second input terminal of the second tri-state inverter receives the low potential signal cn, the third input terminal of the second tri-state inverter receives the high potential signal c, when the first input terminal of the first tri-state inverter receives the low potential signal, the Q output terminal of the first D latch outputs the low potential signal, the QN output terminal of the first D latch outputs the high potential signal, and the first D latch functions as a low potential.
In some embodiments, the second input terminal of the first tri-state inverter receives the high potential signal c, the third input terminal of the first tri-state inverter receives the low potential signal cn, the second input terminal of the second tri-state inverter receives the low potential signal cn, the third input terminal of the second tri-state inverter receives the high potential signal c, when the first input terminal of the first tri-state inverter is connected to the high potential signal, the Q output terminal of the first D latch outputs the high potential signal, the QN output terminal of the first D latch outputs the low potential signal, and the first D latch functions as a high potential.
Fig. 4 is a circuit diagram of a CMOS transistor of the first D latch of fig. 3. Referring to fig. 4, the CMOS transistor circuit of the first D latch 200 includes a first tri-state inverter 201, an inverter 202, and a second tri-state inverter 203.
Referring to fig. 3, the first inverter 201 includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, and a second NMOS transistor N2, where a source of the first PMOS transistor P1 is connected to a high potential VDD, a gate of the first PMOS transistor P1 is connected to a gate of the first NMOS transistor N1 together as a D input terminal, a drain of the first PMOS transistor P1 is connected to a source of the second PMOS transistor P2, a gate of the second PMOS transistor P2 is configured to receive a low potential signal cn or a high potential signal c, a drain of the second PMOS transistor P2 is connected to a source of the second NMOS transistor N2 through a first connection line, a gate of the second NMOS transistor N2 is configured to receive the high potential signal c or the low potential signal cn, a drain of the second NMOS transistor N2 is connected to a source of the first NMOS transistor N1, and a drain of the first NMOS transistor N1 is connected to a low potential VSS.
Referring to fig. 4, the third inverter 203 includes a third PMOS transistor P3, a fourth PMOS transistor P4, a third NMOS transistor N3, and a fourth NMOS transistor N4, where a source of the third PMOS transistor P3 is connected to the high potential VDD, a drain of the third PMOS transistor P3 is connected to a source of the fourth PMOS transistor P4, a gate of the fourth PMOS transistor P4 is configured to receive the high potential signal c or the low potential signal cn, a drain of the fourth PMOS transistor P4 is connected to the source of the fourth NMOS transistor N4 through a second connection line, a first node on the first connection line and a second node on the second connection line are connected through a third connection line, a gate of the fourth NMOS transistor N4 is configured to receive the low potential signal cn or the high potential signal c, a drain of the fourth NMOS transistor N4 is connected to the source of the third NMOS transistor N3, and a drain of the third NMOS transistor N3 is connected to the ground voltage terminal voltage VSS.
Referring to fig. 4, the second inverter 202 includes a fifth PMOS transistor P5 and a fifth NMOS transistor N5, where a source of the fifth PMOS transistor P5 is connected to the high potential VDD, the fifth PMOS transistor P5 is connected to a source of the fifth NMOS transistor N5 through a fourth connection line, a third node is disposed on the fourth connection line, the third node is connected to one end of the fifth connection line, the other end of the fifth connection line is a Q output end, a fourth node is disposed on the fifth connection line, the fourth node is connected to a gate of the third PMOS transistor P3 and a gate of the third NMOS transistor N3, a fifth node is disposed on the third connection line, a gate of the fifth PMOS transistor P5 and a gate of the fifth NMOS transistor N5 are connected to the fifth node, and the fifth node is a QN output end.
Fig. 5 is an equivalent CMOS circuit diagram of fig. 1. Comparing fig. 5 with fig. 4, it can be seen that the present application realizes a D latch through the common gate CFET, and solves the problem that the PMOS transistor and the NMOS transistor in fig. 4 do not have a common gate.
While embodiments of the present invention have been described in detail hereinabove, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. It is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (3)
1. A D-latch constructed from common-gate complementary field effect transistors, comprising:
the first complementary field effect transistor is characterized by comprising a CG end, a PS end and a NS end, wherein the CG end of the first complementary field effect transistor is used for receiving external input data, the PS end of the first complementary field effect transistor is connected with a high potential, and the NS end of the first complementary field effect transistor is connected with a low potential;
the CG end of the second complementary field effect transistor is used for receiving a low potential signal cn or a high potential signal c controlled by time sequence, and the NS end of the second complementary field effect transistor is connected with the ND end of the first complementary field effect transistor;
the CG end of the third complementary field effect transistor is used for receiving a high potential signal c or a low potential signal cn controlled by time sequence, the PS end of the third complementary field effect transistor is connected with the PD end of the first complementary field effect transistor, and the PD end and the ND end of the third complementary field effect transistor are connected with the PD end and the ND end of the second complementary field effect transistor;
a fourth complementary field effect transistor, wherein the PS end of the fourth complementary field effect transistor is connected with a high potential, the PD end of the fourth complementary field effect transistor is connected with the PS end of the second complementary field effect transistor, the ND end of the fourth complementary field effect transistor is connected with the NS end of the third complementary field effect transistor, and the NS end of the fourth complementary field effect transistor is connected with a low potential; and
and the CG end of the fifth complementary field effect transistor is connected with the ND end of the third complementary field effect transistor, the PD end and the ND end of the fifth complementary field effect transistor are both connected with the CG end of the fourth complementary field effect transistor, the PS end of the fifth complementary field effect transistor is connected with a high potential, and the NS end of the fifth complementary field effect transistor is connected with a low potential.
2. The D-latch constructed of common-gate complementary field effect transistors according to claim 1, wherein the first complementary field effect transistor is identical to the second complementary field effect transistor, the third complementary field effect transistor, the fourth complementary field effect transistor and the fifth complementary field effect transistor in structure.
3. The D latch of claim 2, wherein the first complementary field effect transistor is a five-port device, the five ports of the first complementary field effect transistor are the CG terminal, the PS terminal, the PD terminal, the ND terminal, and the NS terminal, respectively, the first complementary field effect transistor has integrated therein a PFET and an NFET transistor, a gate of the PFET transistor is connected to a gate of the NFET transistor to form a CG terminal of the first complementary field effect transistor, a source of the PFET transistor is a PS terminal of the first complementary field effect transistor, a drain of the PFET transistor is a PD terminal of the first complementary field effect transistor, a drain of the NFET transistor is a ND terminal of the first complementary field effect transistor, and a source of the NFET transistor is a NS terminal of the first complementary field effect transistor.
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