CN113644046B - Edge packaging process and structure of NAND flash memory chip - Google Patents
Edge packaging process and structure of NAND flash memory chip Download PDFInfo
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- 238000012858 packaging process Methods 0.000 title claims abstract description 11
- 239000010410 layer Substances 0.000 claims abstract description 326
- 238000003860 storage Methods 0.000 claims abstract description 126
- 239000000758 substrate Substances 0.000 claims abstract description 79
- 239000002346 layers by function Substances 0.000 claims abstract description 48
- 239000012044 organic layer Substances 0.000 claims abstract description 47
- 238000004806 packaging method and process Methods 0.000 claims abstract description 40
- 239000010409 thin film Substances 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 230000007423 decrease Effects 0.000 claims description 16
- 230000003247 decreasing effect Effects 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 6
- 238000005538 encapsulation Methods 0.000 claims 1
- 239000000463 material Substances 0.000 abstract description 20
- 238000007641 inkjet printing Methods 0.000 abstract description 9
- 239000012530 fluid Substances 0.000 description 15
- 238000010586 diagram Methods 0.000 description 5
- 239000002131 composite material Substances 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000004793 Polystyrene Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000003682 fluorination reaction Methods 0.000 description 1
- 238000001027 hydrothermal synthesis Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000009545 invasion Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000002114 nanocomposite Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 229920002223 polystyrene Polymers 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
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Abstract
The invention discloses an edge packaging process and a structure of a NAND flash memory chip, which comprises a storage area and an edge area surrounding the storage area; the edge zone functional layer comprises the buffer insulating layer, the first dielectric layer and the second dielectric layer which cover the edge zone, wherein the thickness of at least one layer in the edge zone functional layer along the direction deviating from the storage zone in the direction vertical to the substrate is gradually reduced and then gradually increased; the volume for accommodating the organic layer is increased, and the organic layer material can be effectively prevented from diffusing outwards and overflowing. Meanwhile, the included angle between the upper surface of the edge region functional layer and the retaining wall is configured to be a larger angle, so that when an organic layer is formed in an ink-jet printing mode, the included angle can be completely infiltrated by organic layer materials, air gaps are prevented from being generated, and the packaging reliability is greatly improved.
Description
Technical Field
The invention relates to the technical field of NAND flash memory chips, in particular to an edge packaging process and structure of a NAND flash memory chip.
Background
NAND flash is a better storage device than hard disk drives and performs particularly well in low capacity applications not exceeding 4 GB. NAND has proven to be very attractive as people continue to pursue products with lower power consumption, lighter weight, and better performance. NAND flash memory is a non-volatile storage technology that retains data after power is removed. Packaging technology is essential and critical to NAND flash memory chips. Since the NAND flash memory chip must be isolated from the outside to prevent the electrical performance from being degraded due to the corrosion of the chip circuit by impurities in the air. On the other hand, the packaged NAND flash memory chip is more convenient to install and transport. The quality of the packaging technology is also of great importance since it directly affects the performance of the chip itself and the design and manufacture of the PCB (printed circuit board) to which it is connected.
In the prior art, a thin film packaging method is often used to ensure that materials and electrodes in the NAND flash memory chip are not corroded by water vapor and oxygen in the external environment, and an organic/inorganic overlapped film structure is often used as a thin film packaging material. Because the organic layer material has fluidity, when the organic layer is formed by adopting an ink-jet printing mode, the organic layer material is easy to diffuse and overflow outwards, so that the packaging effect is poor. In the prior art, the thickness of some functional film layers in the edge area is gradually reduced, the volume for accommodating the organic layer is increased, and the organic layer material can be effectively prevented from diffusing outwards and overflowing. However, the thinned edge region can reduce the included angle of the remaining edge retaining walls, so that when an organic layer is formed by adopting an ink-jet printing mode, the included angle cannot be completely infiltrated by organic layer materials, an air gap is generated, and finally the packaging reliability is failed.
Therefore, it is necessary to provide an edge packaging process of a NAND flash memory chip and a structure thereof, so as to prevent the organic layer material from being diffused and overflowing, and to have higher packaging reliability.
Disclosure of Invention
The invention solves the problem of providing an edge packaging process and a structure of a NAND flash memory chip, and can effectively prevent organic layer materials from diffusing and overflowing outwards by designing a functional layer in an edge area to be reduced in thickness and then increased in thickness, and have higher packaging reliability.
In order to solve the above problems, the present invention provides an edge package structure of a NAND flash memory chip, including a storage area and an edge area surrounding the storage area; the packaging structure further comprises a substrate base plate; the buffer insulating layer is positioned on one side surface of the substrate, covers the storage area and extends to cover the edge area; the circuit wiring layer is positioned on the surface of one side, away from the substrate, of the buffer insulating layer and comprises a first dielectric layer, a metal layer and a second dielectric layer; the first dielectric layer is positioned on one side surface of the buffer insulating layer, which is far away from the substrate base plate, covers the storage area and extends to cover the edge area; the second dielectric layer is positioned on one side surface of the first dielectric layer, which is far away from the buffer insulating layer, covers the storage region and extends to cover the edge region; the metal layer is positioned between the first dielectric layer and the second dielectric layer, and the metal layer is only positioned in the storage region and does not extend to the edge region; the edge zone functional layer comprises the buffer insulating layer, the first dielectric layer and the second dielectric layer which cover the edge zone, wherein the thickness of at least one layer in the edge zone functional layer along the direction deviating from the storage zone in the direction vertical to the substrate is gradually reduced and then gradually increased; the NAND flash memory chip is positioned on the surface of one side, away from the buffer insulating layer, of the circuit wiring layer, and is only positioned in the storage area and does not extend to the edge area; the thin film packaging layer comprises an organic layer and an inorganic layer which are stacked, the thin film packaging layer is positioned above the NAND flash memory chip and the circuit wiring layer, and the thin film packaging layer covers the storage region and extends to cover the marginal region.
Optionally, the thicknesses of the buffer insulating layer and the first dielectric layer in the edge region functional layer are configured to be uniform, and the thickness of the second dielectric layer in a direction away from the storage region and perpendicular to the substrate direction gradually decreases and then gradually increases.
Optionally, the thickness of the buffer insulating layer in the edge functional layer is configured to be uniform, the thickness of the first dielectric layer along a direction away from the storage region and in a direction perpendicular to the substrate gradually decreases and then gradually increases, and the second dielectric layer is configured to be conformally disposed on the surface of the first dielectric layer.
Optionally, the thickness of the buffer insulating layer in the edge functional layer in the direction away from the storage region and perpendicular to the substrate direction gradually decreases and then gradually increases, the first dielectric layer is configured to be conformally disposed on a side surface of the buffer insulating layer away from the substrate, and the second dielectric layer is configured to be conformally disposed on a side surface of the first dielectric layer away from the buffer insulating layer.
Optionally, the storage device further comprises a retaining wall structure located in the edge region and surrounding the storage region, and the cross-sectional shape of the retaining wall structure is configured as a regular trapezoid.
Optionally, the second dielectric layer forms a first included angle with the horizontal direction along a direction away from the storage region, where a surface of the second dielectric layer, which is gradually reduced in thickness in a direction perpendicular to the substrate base plate, and the size of the first included angle is configured to be 13 ° to 24 °; the second dielectric layer forms a second included angle with the horizontal direction along the direction departing from the storage region, wherein the surface of the second dielectric layer with the thickness gradually increasing in the direction perpendicular to the substrate base plate is configured to be 13-24 degrees; and the second dielectric layer forms a third included angle with the sidewall surface of the retaining wall facing the storage region direction along the direction deviating from the storage region, wherein the thickness of the second dielectric layer in the direction perpendicular to the substrate is gradually increased, and the third included angle is configured to be 133-148 degrees.
The invention provides an edge packaging process of a NAND flash memory chip, which comprises the steps of providing a packaging structure, wherein the packaging structure comprises a storage area and an edge area surrounding the storage area; the packaging structure further comprises a substrate base plate; providing a buffer insulating layer, wherein the buffer insulating layer is formed on one side surface of the substrate base plate, and the buffer insulating layer covers the storage area and extends to cover the edge area; providing a circuit wiring layer, wherein the circuit wiring layer is formed on the surface of one side, away from the substrate, of the buffer insulating layer, and comprises a first dielectric layer, a metal layer and a second dielectric layer; the first dielectric layer is positioned on one side surface of the buffer insulating layer, which is far away from the substrate base plate, covers the storage area and extends to cover the edge area; the second dielectric layer is positioned on one side surface of the first dielectric layer, which is far away from the buffer insulating layer, covers the storage region and extends to cover the edge region; the metal layer is positioned between the first dielectric layer and the second dielectric layer, and the metal layer is only positioned in the storage region and does not extend to the edge region; providing an edge region functional layer, wherein the edge region functional layer comprises the buffer insulating layer, the first dielectric layer and the second dielectric layer which cover the edge region, and the thickness of at least one layer of the edge region functional layer along the direction departing from the storage region and in the direction vertical to the substrate gradually decreases and then gradually increases; providing a NAND flash memory chip, wherein the NAND flash memory chip is formed on the surface of one side, away from the buffer insulating layer, of the circuit wiring layer, and the NAND flash memory chip is only positioned in the storage area and does not extend to the edge area; and providing a thin film packaging layer, wherein the thin film packaging layer comprises an organic layer and an inorganic layer which are arranged in a stacking mode, the thin film packaging layer is formed above the NAND flash memory chip and the circuit wiring layer, and the thin film packaging layer covers the storage region and extends to cover the marginal region.
Optionally, the thicknesses of the buffer insulating layer and the first dielectric layer in the edge region functional layer are configured to be uniform, and the thickness of the second dielectric layer in a direction away from the storage region and perpendicular to the substrate direction gradually decreases and then gradually increases.
Optionally, the thickness of the buffer insulating layer in the edge region functional layer is configured to be uniform, the thickness of the first dielectric layer along a direction away from the storage region in a direction perpendicular to the substrate gradually decreases and then gradually increases, and the second dielectric layer is configured to be conformally disposed on a surface of the first dielectric layer.
Optionally, the thickness of the buffer insulating layer in the edge region functional layer along a direction away from the storage region and in a direction perpendicular to the substrate is gradually decreased and then gradually increased, the first dielectric layer is configured to be conformally disposed on a side surface of the buffer insulating layer away from the substrate, and the second dielectric layer is configured to be conformally disposed on a side surface of the first dielectric layer away from the buffer insulating layer.
Optionally, the storage device further comprises a retaining wall structure located in the edge region and surrounding the storage region, and the cross-sectional shape of the retaining wall structure is configured as a regular trapezoid.
Optionally, the second dielectric layer forms a first included angle with the horizontal direction along a direction away from the storage region, where a surface of the second dielectric layer, which has a gradually decreasing thickness in a direction perpendicular to the substrate, and the size of the first included angle is configured to be 13 ° to 24 °; the second dielectric layer forms a second included angle with the horizontal direction along the direction departing from the storage region, wherein the surface of the second dielectric layer with the thickness gradually increasing in the direction perpendicular to the substrate base plate is configured to be 13-24 degrees; and the second dielectric layer forms a third included angle with the surface of the side wall of the retaining wall facing the storage region direction along the direction deviating from the storage region, wherein the thickness of the second dielectric layer in the direction perpendicular to the substrate is gradually increased, and the third included angle is 133-148 degrees.
Compared with the prior art, the technical scheme of the invention has the following advantages: at least one layer in the marginal zone functional layer is arranged to be gradually reduced and then gradually increased along the direction deviating from the storage region and perpendicular to the thickness of the substrate in the direction, so that the volume for accommodating the organic layer is increased, and the organic layer material can be effectively prevented from being diffused outwards and overflowing. Meanwhile, the included angle between the upper surface of the edge functional layer and the retaining wall is configured to be a larger angle, so that when an organic layer is formed in an ink-jet printing mode, the included angle can be completely infiltrated by an organic layer material, air gaps are prevented from being generated, and the packaging reliability is greatly improved.
Drawings
Fig. 1 is a schematic diagram of an edge package structure of a NAND flash memory chip in the prior art.
FIG. 2 is a top view of an edge package structure of a NAND flash memory chip in the prior art.
Fig. 3-5 are schematic diagrams of edge package structures of a NAND flash memory chip according to the present application.
Detailed Description
Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended to limit the disclosure, its application, or uses. The present disclosure may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that: the relative arrangement of parts and steps, the composition of materials and values set forth in these embodiments are to be construed as illustrative only and not as limiting unless otherwise specifically stated.
The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element preceding the word comprises the element listed after the word, and does not exclude the possibility that other elements may also be included.
All terms (including technical or scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs unless specifically defined otherwise. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
Embodiments of the present disclosure will be described with reference to the accompanying drawings. Hereinafter, mutually corresponding portions in the drawings will be denoted by the same reference numerals.
Fig. 1 is a schematic diagram of an edge package structure of a NAND flash memory chip in the prior art, and fig. 2 is a schematic diagram of a top view of an edge package structure of a NAND flash memory chip in the prior art, including a storage area AA and an edge area BB surrounding the storage area; the package structure further includes a substrate base 100; a buffer insulating layer 200, wherein the buffer insulating layer 200 is located on one side surface of the substrate, and the buffer insulating layer 200 covers the storage area AA and extends to cover the edge area BB; a circuit wiring layer 300 on a surface of the buffer insulating layer 200 on a side away from the substrate 100, the circuit wiring layer 300 including a first dielectric layer 301, a metal layer (not shown in the drawings), and a second dielectric layer 302; the first dielectric layer 301 is located on a side surface of the buffer insulating layer 200 facing away from the substrate 100, and the first dielectric layer 301 covers the storage area AA and extends to cover the edge area BB; the second dielectric layer 302 is located on a surface of the first dielectric layer 301 facing away from the buffer insulating layer 200, and the second dielectric layer 302 covers the storage area AA and extends to the edge area BB; the metal layer is located between the first dielectric layer 301 and the second dielectric layer 302, and the metal layer is located only in the storage region AA and does not extend to the edge region BB; the edge zone functional layer comprises the buffer insulating layer 200 covering the edge zone BB, the first dielectric layer 301 and the second dielectric layer 302, wherein at least one layer of the edge zone functional layer has a thickness decreasing in a direction away from the storage zone AA and perpendicular to the substrate 100; the NAND flash memory chip 400 is located on a surface of the circuit wiring layer 300, which is away from the buffer insulating layer 200, and the NAND flash memory chip 400 is only located in the storage area AA and does not extend to the edge area BB; the thin film packaging layer comprises an organic layer 500 and an inorganic layer 600 which are stacked, the thin film packaging layer is positioned above the NAND flash memory chip and the circuit wiring layer, and the thin film packaging layer covers the storage area AA and extends to cover the marginal area BB.
Compared with the storage area AA, the thickness of at least one of the functional layers in the marginal area BB is gradually reduced, when the organic layer in the thin film packaging layer is formed in an ink-jet printing mode, the volume for accommodating the organic layer is increased, a part of the volume in the organic layer can be located in the thinned area, even if a part of the volume in the organic layer is lost in the thinned area, the organic layer is cut off in advance, and the organic layer material in the thin film packaging is prevented from diffusing outwards and overflowing beyond the retaining wall 700; meanwhile, the flow speed of the organic layer material is accelerated, so that the time for the organic layer to cut off in advance is reduced.
However, since the thickness of at least one of the functional layers in the edge area BB is gradually reduced, the included angle formed between the functional layer and the retaining wall 700 is reduced, as shown in the partial view of fig. 1, which forms an imaginary scalene triangle. In the study of the force applied to the fluid flowing through the triangular anisotropic structure, it was found that the resistance to the fluid flowing through the surface satisfied the formula:
. Wherein f is the resistance, k is the length of the three phase line of the fluid and the structure,
in order to be the surface tension of the fluid,
and
respectively, the receding angle and the advancing angle of the fluid. When fluid flows along different directions of anisotropy, the actual advancing angle and the actual retreating angle of the fluid are different due to different shapes of the two sides of the structure, so that the resistance force applied to the fluid flowing along different directions of the structure is different, namely the fluid gradient phenomenon. When the organic layer is formed by adopting an ink-jet printing mode, the organic layer material cannot completely soak the included angle, air gaps are generated, and the invasion of water vapor and oxygen cannot be blockedEventually leading to package reliability failures.
Fig. 3 is a schematic diagram of an edge package structure of a NAND flash memory chip provided in the present invention, which includes a storage area AA and an edge area BB surrounding the storage area; the package structure further includes a substrate base 100; a buffer insulating layer 200, wherein the buffer insulating layer 200 is located on one side surface of the substrate 100, and the buffer insulating layer 200 covers the storage area AA and extends to cover the edge area BB; a circuit wiring layer 300, wherein the circuit wiring layer is positioned on one side surface of the buffer insulating layer 200, which is far away from the substrate 100, and the circuit wiring layer 300 comprises a first dielectric layer 301, a metal layer and a second dielectric layer 302; the first dielectric layer 301 is located on a side surface of the buffer insulating layer 200 facing away from the substrate 100, and the first dielectric layer 301 covers the storage area AA and extends to cover the edge area BB; the second dielectric layer 302 is located on a side surface of the first dielectric layer 301 facing away from the buffer insulating layer 200, and the second dielectric layer 302 covers the storage area AA and extends to cover the edge area BB; the metal layer (not shown in the drawings) is located between the first dielectric layer 301 and the second dielectric layer 302, and the metal layer is located only in the storage area AA and does not extend to the edge area BB; the edge zone functional layer comprises the buffer insulating layer 200, the first dielectric layer 301 and the second dielectric layer 302 covering the edge zone BB, wherein at least one layer of the edge zone functional layer has a thickness in a direction away from the storage area AA and perpendicular to the substrate 100, which gradually decreases and then gradually increases; the NAND flash memory chip 400 is located on a surface of one side of the circuit wiring 300 layer, which is away from the buffer insulating layer 200, and the NAND flash memory chip 400 is only located in the storage area AA and does not extend to the edge area BB; the thin film packaging layer comprises an organic layer 500 and an inorganic layer 600 which are stacked, is positioned above the NAND flash memory chip 400 and the circuit wiring layer 300, and covers the storage area AA and extends to cover the edge area BB; the inorganic layer 600 may be a single or multi-layered structure of silicon oxide, silicon nitride, silicon oxynitride, or amorphous silicon, and the organic layer 500 may be one or more of acrylic, polycarbonate, and polystyrene to prevent the intrusion of external moisture and oxygen.
Compared with the storage area AA, the thickness of at least one layer of the functional layers in the marginal area BB is gradually reduced and then gradually increased, so that a containing space which is concave downwards is formed on the surface of the marginal area functional layer, when the organic layer in the thin film packaging layer is formed in an ink-jet printing mode, the volume for containing the organic layer is increased, a part of the volume of the organic layer can be located in the area of the containing space, even if a part of the volume of the organic layer is lost in the area of the containing space, the organic layer is cut off in advance, and the organic layer material in the thin film packaging is prevented from diffusing outwards and overflowing beyond the retaining wall 700; meanwhile, the flow speed of the organic layer material is accelerated, so that the time for the organic layer to cut off in advance is reduced.
Optionally, referring to fig. 3, thicknesses of the buffer insulating layer and the first dielectric layer in the edge functional layer are configured to be uniform, and a thickness of the second dielectric layer along a direction away from the storage region and perpendicular to the substrate direction gradually decreases and then gradually increases.
Optionally, referring to fig. 4, the thickness of the buffer insulating layer in the edge functional layer is configured to be uniform, the thickness of the first dielectric layer along a direction away from the storage region and perpendicular to the substrate direction gradually decreases and then gradually increases, and the second dielectric layer is configured to be conformally disposed on the surface of the first dielectric layer.
Optionally, referring to fig. 5, the thickness of the buffer insulating layer in the edge functional layer along a direction away from the storage region and perpendicular to the substrate direction gradually decreases and then gradually increases, the first dielectric layer is configured to be conformally disposed on a side surface of the buffer insulating layer away from the substrate, and the second dielectric layer is configured to be conformally disposed on a side surface of the first dielectric layer away from the buffer insulating layer.
Optionally, the storage device further includes a retaining wall structure 700 located in the edge region and surrounding the storage region, and the cross-sectional shape of the retaining wall structure is configured as a regular trapezoid.
Optionally, the second dielectric layer forms a first included angle with the horizontal direction along a direction away from the storage region, where a surface of the second dielectric layer, which has a gradually decreasing thickness in a direction perpendicular to the substrate, and the size of the first included angle is configured to be 13 ° to 24 °; the second dielectric layer forms a second included angle with the horizontal direction along the direction departing from the storage region, wherein the surface of the second dielectric layer with the thickness gradually increasing in the direction perpendicular to the substrate base plate is configured to be 13-24 degrees; and the second dielectric layer forms a third included angle with the sidewall surface of the retaining wall facing the storage region direction along the direction deviating from the storage region, wherein the thickness of the second dielectric layer in the direction perpendicular to the substrate is gradually increased, and the third included angle is configured to be 133-148 degrees. The thickness of at least one layer of the functional layers in the marginal zone BB is gradually increased at the position close to the retaining wall to form the third included angle, so that the included angle formed by the third included angle and the retaining wall 700 can be effectively increased, when fluid flows along different anisotropic directions, the actual advancing angle and the actual retreating angle of the fluid tend to be the same, so that the resistance borne by the fluid also tends to be the same, the fluid gradient phenomenon is reduced, when an organic layer is formed in an ink-jet printing mode, the included angle can be completely soaked by the organic layer material, air gaps are prevented from being generated, and the packaging reliability is not high.
Furthermore, the surface of the single structure lacks special fluid wettability, fluid also lacks power when moving on the surface of the structure, and a micron-scale hill-shaped structure is formed on the surface of the edge functional layer, which is in contact with the organic layer, through an acid cleaning method, wherein solutions adopted by the acid cleaning method are nitric acid and hydrofluoric acid. And preparing a layer of titanium dioxide nano-scale convex structure on the micron-scale hill-shaped structure by a hydrothermal method to form a composite structure. The surface with the composite structure can greatly improve the wettability of several layers of materials by carrying out the affinity and hydrophobicity test on the surface with the composite structure. Furthermore, the surface energy can be effectively reduced and the wettability of the surface of the composite structure can be regulated by performing fluorination treatment on the micro-nano composite structure, so that when an organic layer is formed by adopting an ink-jet printing mode, the wettability is further increased, the organic layer material can completely wet an included angle formed by the surface of the second medium layer and the surface of the retaining wall, and air gaps are prevented from being generated.
The invention also provides an edge packaging process of the NAND flash memory chip, and provides a packaging structure which comprises a storage area and an edge area surrounding the storage area; the packaging structure further comprises a substrate base plate; providing a buffer insulating layer, wherein the buffer insulating layer is formed on one side surface of the substrate base plate, and the buffer insulating layer covers the storage area and extends to cover the edge area; providing a circuit wiring layer, wherein the circuit wiring layer is formed on the surface of one side, away from the substrate, of the buffer insulating layer, and comprises a first dielectric layer, a metal layer and a second dielectric layer; the first dielectric layer is positioned on one side surface of the buffer insulating layer, which is far away from the substrate, covers the storage area and extends to the edge area; the second dielectric layer is positioned on one side surface of the first dielectric layer, which is far away from the buffer insulating layer, covers the storage region and extends to cover the edge region; the metal layer is positioned between the first dielectric layer and the second dielectric layer, and the metal layer is only positioned in the storage region and does not extend to the edge region; providing an edge region functional layer, wherein the edge region functional layer comprises the buffer insulating layer, the first dielectric layer and the second dielectric layer which cover the edge region, and the thickness of at least one layer of the edge region functional layer along the direction departing from the storage region in the direction vertical to the substrate is gradually reduced and then gradually increased; providing a NAND flash memory chip, wherein the NAND flash memory chip is formed on the surface of one side of the circuit wiring layer, which is far away from the buffer insulating layer, and the NAND flash memory chip is only positioned in the storage area and does not extend to the edge area; and providing a film packaging layer, wherein the film packaging layer is formed above the NAND flash memory chip and the circuit wiring layer, and covers the storage area and extends to the edge area.
Optionally, the thicknesses of the buffer insulating layer and the first dielectric layer in the edge region functional layer are configured to be uniform, and the thickness of the second dielectric layer in a direction away from the storage region and perpendicular to the substrate direction gradually decreases and then gradually increases.
Optionally, the thickness of the buffer insulating layer in the edge region functional layer is configured to be uniform, the thickness of the first dielectric layer along a direction away from the storage region in a direction perpendicular to the substrate gradually decreases and then gradually increases, and the second dielectric layer is configured to be conformally disposed on a surface of the first dielectric layer.
Optionally, the thickness of the buffer insulating layer in the edge region functional layer along a direction away from the storage region and in a direction perpendicular to the substrate is gradually decreased and then gradually increased, the first dielectric layer is configured to be conformally disposed on a side surface of the buffer insulating layer away from the substrate, and the second dielectric layer is configured to be conformally disposed on a side surface of the first dielectric layer away from the buffer insulating layer.
Optionally, the storage area is provided with a plurality of storage areas, and the storage areas are arranged in the edge area.
Optionally, the second dielectric layer forms a first included angle with the horizontal direction along a direction away from the storage region, where a surface of the second dielectric layer, which has a gradually decreasing thickness in a direction perpendicular to the substrate, and the size of the first included angle is configured to be 13 ° to 24 °; the second dielectric layer forms a second included angle with the horizontal direction along the direction departing from the storage region, wherein the surface of the second dielectric layer with the thickness gradually increasing in the direction perpendicular to the substrate base plate is configured to be 13-24 degrees; and the second dielectric layer forms a third included angle with the surface of the side wall of the retaining wall facing the storage region direction along the direction deviating from the storage region, wherein the thickness of the second dielectric layer in the direction perpendicular to the substrate is gradually increased, and the third included angle is 133-148 degrees.
So far, embodiments of the present disclosure have been described in detail. Some details well known in the art have not been described in order to avoid obscuring the concepts of the present disclosure. Those skilled in the art can now fully appreciate how to implement the teachings disclosed herein, in view of the foregoing description.
While the disclosure has been described with reference to embodiments thereof, it is to be understood that the disclosure is not limited to the embodiments and constructions. The disclosure is intended to cover various modifications and equivalent arrangements. Moreover, other combinations and configurations, including more, less or only a single element, in addition to the various combinations and configurations described, are also within the spirit and scope of the disclosure.
Claims (8)
1. The edge packaging structure of the NAND flash memory chip is characterized by comprising a storage area and an edge area surrounding the storage area;
the package structure further includes: a substrate base plate;
the buffer insulating layer is positioned on one side surface of the substrate, covers the storage area and extends to cover the edge area;
the circuit wiring layer is positioned on the surface of one side, away from the substrate, of the buffer insulating layer and comprises a first dielectric layer, a metal layer and a second dielectric layer; the first dielectric layer is positioned on one side surface of the buffer insulating layer, which is far away from the substrate base plate, covers the storage area and extends to cover the edge area; the second dielectric layer is positioned on one side surface of the first dielectric layer, which is far away from the buffer insulating layer, covers the storage region and extends to cover the edge region; the metal layer is positioned between the first dielectric layer and the second dielectric layer, and the metal layer is only positioned in the storage region and does not extend to the edge region;
the edge zone functional layer comprises the buffer insulating layer, the first dielectric layer and the second dielectric layer which cover the edge zone, wherein the thickness of at least one layer in the edge zone functional layer along the direction deviating from the storage zone in the direction vertical to the substrate is gradually reduced and then gradually increased;
the NAND flash memory chip is positioned on the surface of one side, away from the buffer insulating layer, of the circuit wiring layer, and is only positioned in the storage area and does not extend to the edge area;
the thin film packaging layer comprises an organic layer and an inorganic layer which are arranged in a stacked mode, is positioned above the NAND flash memory chip and the circuit wiring layer and covers the storage area and extends to the edge area;
the storage area is arranged in the edge area and surrounds the storage area, and the cross section of the retaining wall structure is in a regular trapezoid shape; the second dielectric layer forms a first included angle with the horizontal direction along the direction departing from the storage region, wherein the surface of the second dielectric layer, with the thickness gradually reduced, is vertical to the substrate direction, and the size of the first included angle is configured to be 13-24 degrees; the second dielectric layer forms a second included angle with the horizontal direction along the direction departing from the storage region, wherein the surface of the second dielectric layer with the thickness gradually increasing in the direction perpendicular to the substrate base plate is configured to be 13-24 degrees; and the second dielectric layer forms a third included angle with the sidewall surface of the retaining wall facing the storage region direction along the direction deviating from the storage region, wherein the thickness of the second dielectric layer in the direction perpendicular to the substrate is gradually increased, and the third included angle is configured to be 133-148 degrees.
2. The package structure according to claim 1, wherein the thicknesses of the buffer insulating layer and the first dielectric layer in the edge-region functional layer are configured to be uniform, and the thickness of the second dielectric layer in a direction away from the storage region and perpendicular to the substrate is gradually decreased and then gradually increased.
3. The package structure according to claim 1, wherein the thickness of the buffer insulating layer in the edge functional layer is configured to be uniform, the thickness of the first dielectric layer along a direction away from the storage region and perpendicular to the substrate gradually decreases and then gradually increases, and the second dielectric layer is configured to be conformally disposed on a surface of the first dielectric layer.
4. The package structure according to claim 1, wherein the thickness of the buffer insulating layer in the edge functional layer in a direction away from the storage region and perpendicular to the substrate gradually decreases and then gradually increases, the first dielectric layer is configured to be conformally disposed on a side surface of the buffer insulating layer away from the substrate, and the second dielectric layer is configured to be conformally disposed on a side surface of the first dielectric layer away from the buffer insulating layer.
5. The edge packaging process of the NAND flash memory chip is characterized by providing a packaging structure, wherein the packaging structure comprises a storage area and an edge area surrounding the storage area;
the packaging structure further comprises a substrate base plate;
providing a buffer insulating layer, wherein the buffer insulating layer is formed on one side surface of the substrate base plate, and the buffer insulating layer covers the storage area and extends to cover the edge area;
providing a circuit wiring layer, wherein the circuit wiring layer is formed on the surface of one side, away from the substrate, of the buffer insulating layer, and comprises a first dielectric layer, a metal layer and a second dielectric layer; the first dielectric layer is positioned on one side surface of the buffer insulating layer, which is far away from the substrate base plate, covers the storage area and extends to cover the edge area; the second dielectric layer is positioned on one side surface of the first dielectric layer, which is far away from the buffer insulating layer, covers the storage region and extends to cover the edge region; the metal layer is positioned between the first dielectric layer and the second dielectric layer, and the metal layer is only positioned in the storage region and does not extend to the edge region;
providing an edge region functional layer, wherein the edge region functional layer comprises the buffer insulating layer, the first dielectric layer and the second dielectric layer which cover the edge region, and the thickness of at least one layer of the edge region functional layer along the direction departing from the storage region and in the direction vertical to the substrate gradually decreases and then gradually increases;
providing a NAND flash memory chip, wherein the NAND flash memory chip is formed on the surface of one side of the circuit wiring layer, which is far away from the buffer insulating layer, and the NAND flash memory chip is only positioned in the storage area and does not extend to the edge area;
providing a thin film packaging layer, wherein the thin film packaging layer comprises an organic layer and an inorganic layer which are arranged in a stacking mode, the thin film packaging layer is formed above the NAND flash memory chip and the circuit wiring layer, and the thin film packaging layer covers the storage region and extends to cover the edge region;
the storage area is arranged in the edge area, and the storage area is arranged in the edge area; the second dielectric layer forms a first included angle with the horizontal direction along the direction departing from the storage region, wherein the surface of the second dielectric layer, the thickness of which is gradually reduced in the direction perpendicular to the substrate, is configured to be 13-24 degrees; the second dielectric layer forms a second included angle with the horizontal direction along the direction departing from the storage region, wherein the surface of the second dielectric layer with the thickness gradually increasing in the direction perpendicular to the substrate base plate is configured to be 13-24 degrees; and the second dielectric layer forms a third included angle with the sidewall surface of the retaining wall facing the storage region direction along the direction deviating from the storage region, wherein the thickness of the second dielectric layer in the direction perpendicular to the substrate is gradually increased, and the third included angle is configured to be 133-148 degrees.
6. The encapsulation process according to claim 5, wherein the thicknesses of the buffer insulating layer and the first dielectric layer in the edge zone functional layer are configured to be uniform, and the thickness of the second dielectric layer in a direction away from the storage zone and perpendicular to the substrate is gradually reduced and then gradually increased.
7. The packaging process according to claim 5, wherein the thickness of the buffer insulating layer in the edge-region functional layer is configured to be uniform, the thickness of the first dielectric layer in a direction away from the storage region and perpendicular to the substrate is gradually decreased and then gradually increased, and the second dielectric layer is configured to be conformally disposed on the surface of the first dielectric layer.
8. The packaging process according to claim 5, wherein the thickness of the buffer insulating layer in the edge-region functional layer in a direction away from the storage region and perpendicular to the substrate gradually decreases and then gradually increases, the first dielectric layer is configured to be conformally disposed on a side surface of the buffer insulating layer away from the substrate, and the second dielectric layer is configured to be conformally disposed on a side surface of the first dielectric layer away from the buffer insulating layer.
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| CN101996975A (en) * | 2009-08-19 | 2011-03-30 | 瑞萨电子株式会社 | Interposer chip and manufacturing method thereof |
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| CN109494240A (en) * | 2017-09-12 | 2019-03-19 | 三星显示有限公司 | Display device |
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| US11295998B2 (en) * | 2018-04-04 | 2022-04-05 | Intel Corporation | Stiffener and package substrate for a semiconductor package |
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| CN101996975A (en) * | 2009-08-19 | 2011-03-30 | 瑞萨电子株式会社 | Interposer chip and manufacturing method thereof |
| CN105244289A (en) * | 2014-07-08 | 2016-01-13 | 台湾积体电路制造股份有限公司 | Methods of packaging semiconductor devices and packaged semiconductor devices |
| CN109494240A (en) * | 2017-09-12 | 2019-03-19 | 三星显示有限公司 | Display device |
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