CN113641214A - Clock calibration circuit, clock calibration method and related equipment - Google Patents
Clock calibration circuit, clock calibration method and related equipment Download PDFInfo
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- 230000010355 oscillation Effects 0.000 claims abstract description 73
- 238000004891 communication Methods 0.000 claims abstract description 64
- 238000000605 extraction Methods 0.000 claims abstract description 38
- 239000003990 capacitor Substances 0.000 claims description 9
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
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Abstract
The application discloses a clock calibration circuit, a clock calibration method and related equipment, wherein the clock calibration circuit comprises a real-time clock module, an oscillation module, a clock extraction module, a communication module and a control module, wherein the first end of the clock extraction module is electrically connected with the communication module, the control module is respectively electrically connected with the second end of the clock extraction module, the oscillation module and the real-time clock module, and the oscillation module is also electrically connected with the real-time clock module; the clock extraction module is configured to obtain a first clock signal of the communication module, calibrate, by the control module, the second clock signal based on the first clock signal when an error between a clock frequency of the first clock signal and a clock frequency of a second clock signal corresponding to the oscillation module exceeds a preset range, and update the real-time clock module based on the calibrated second clock signal.
Description
Technical Field
The present application belongs to the field of communication technologies, and in particular, to a clock calibration circuit, a clock calibration method, and a related device.
Background
Under the condition that the terminal is shut down, a real-time clock module of the terminal has the requirements of high clock precision and extremely low power consumption. The clock required for shutdown can be generated by integrating the oscillation module on the clock chip where the real-time clock module is located, so that the purpose of extremely low power consumption is achieved; and integrating a special clock source on a clock chip where the real-time clock module is located so as to calibrate the system clock through the special clock source and achieve the purpose of improving the clock precision of the real-time clock module. However, integrating a dedicated clock source on a clock chip increases the design cost of the clock chip.
Therefore, in the related art, the clock chip has a problem of high design cost.
Disclosure of Invention
The application aims to provide a clock calibration circuit, a clock calibration method and related equipment, and can solve the problem that in the related art, a clock chip is high in design cost.
In order to solve the technical problem, the present application is implemented as follows:
in a first aspect, an embodiment of the present application provides a clock calibration circuit, including a real-time clock module, an oscillation module, a clock extraction module, a communication module, and a control module, where a first end of the clock extraction module is electrically connected to the communication module, the control module is electrically connected to a second end of the clock extraction module, the oscillation module, and the real-time clock module, and the oscillation module is further electrically connected to the real-time clock module;
the clock extraction module is configured to obtain a first clock signal of the communication module, calibrate, by the control module, the second clock signal based on the first clock signal when an error between a clock frequency of the first clock signal and a clock frequency of a second clock signal corresponding to the oscillation module exceeds a preset range, and update the real-time clock module based on the calibrated second clock signal.
In a second aspect, an embodiment of the present application provides a clock calibration method, which is applied to the clock calibration circuit according to the first aspect, where the clock calibration circuit includes a real-time clock module, an oscillation module, a clock extraction module, and a communication module, and the method includes:
acquiring a first clock signal of the communication module through the clock extraction module;
calibrating a second clock signal corresponding to the oscillation module based on the first clock signal when the error between the clock frequency of the first clock signal and the clock frequency of the second clock signal exceeds a preset range;
updating the real-time clock module based on the calibrated second clock signal.
In a third aspect, an embodiment of the present application provides a clock calibration apparatus, where the apparatus includes the clock calibration circuit according to the first aspect, where the clock calibration circuit includes a real-time clock module, an oscillation module, a clock extraction module, and a communication module, and the apparatus further includes:
the first acquisition module is used for acquiring a first clock signal of the communication module through the clock extraction module;
the calibration module is used for calibrating the second clock signal based on the first clock signal under the condition that the error between the clock frequency of the first clock signal and the clock frequency of the second clock signal corresponding to the oscillation module exceeds a preset range;
and the updating module is used for updating the real-time clock module based on the calibrated second clock signal.
In a fourth aspect, the present application provides an electronic device, which includes a processor, a memory, and a program or instructions stored on the memory and executable on the processor, and when executed by the processor, the program or instructions implement the steps of the method according to the second aspect.
In a fifth aspect, the present application provides a computer-readable storage medium, on which a program or instructions are stored, which when executed by a processor implement the steps of the method according to the second aspect.
In a sixth aspect, the present application provides a chip, where the chip includes a processor and a communication interface, where the communication interface is coupled to the processor, and the processor is configured to execute a program or instructions to implement the method according to the second aspect.
In the embodiment of the application, the first clock signal of the communication module is acquired through the clock extraction module, and the acquired first clock signal is used as the clock reference signal, so that the first clock signal is used as the reference clock signal to calibrate the second clock signal corresponding to the oscillation module under the condition that the error between the clock frequency of the acquired first clock signal and the clock frequency of the second clock signal corresponding to the oscillation module exceeds the preset range, so as to avoid adding an additional calibration clock source in the clock calibration circuit, i.e., without using a clock chip, and further achieve the purpose of reducing the design cost of the clock calibration circuit.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The above and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a block diagram of a clock calibration circuit according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of clock calibration provided by an embodiment of the present application;
FIG. 3 is a flowchart of a clock calibration method provided in an embodiment of the present application;
fig. 4 is a structural diagram of a clock calibration apparatus according to an embodiment of the present application;
FIG. 5 is a block diagram of an electronic device according to an embodiment of the present disclosure;
fig. 6 is a second structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that embodiments of the application may be practiced in sequences other than those illustrated or described herein, and that the terms "first," "second," and the like are generally used herein in a generic sense and do not limit the number of terms, e.g., the first term can be one or more than one. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.
The clock calibration scheme provided by the embodiments of the present application is described in detail below with reference to the accompanying drawings through specific embodiments and application scenarios thereof.
As shown in fig. 1, an embodiment of the present invention provides a clock calibration circuit, which may be applied to electronic devices such as a Mobile phone, a Tablet Personal Computer (Tablet Personal Computer), a Laptop Computer (Laptop Computer), a Personal Digital Assistant (PDA), a Mobile Internet Device (MID), or a Wearable Device (Wearable Device), and the clock calibration circuit includes a real-time clock module 10, an oscillation module 20, a clock extraction module 30, a communication module 40, and a control module 50, wherein a first end of the clock extraction module 30 is electrically connected to the communication module 40, the control module 50 is electrically connected to a second end of the clock extraction module 30, the oscillation module 20, and the real-time clock module 10, and the oscillation module 20 is further electrically connected to the real-time clock module 10;
the clock extraction module 30 is configured to obtain a first clock signal of the communication module 40, calibrate the second clock signal based on the first clock signal by the control module 50 when an error between a clock frequency of the first clock signal and a clock frequency of a second clock signal corresponding to the oscillation module 20 exceeds a preset range, and update the real-time clock module 10 based on the calibrated second clock signal.
It will be appreciated that the clock calibration circuit may also include other functional blocks, such as driver circuits, counters, etc.
In this embodiment, the clock information included in the communication module 40 needs to be used for modulation and mediation of transmission information at the transmitting end and the receiving end, that is, the clock information included in the communication module 40 needs to have higher precision; therefore, the first clock signal of the communication module 40 may be obtained through the clock extraction module 30, and the obtained first clock signal is used as a clock reference signal, so that the second clock signal corresponding to the oscillation module 20 is calibrated by using the first clock signal as the reference clock signal under the condition that the error between the clock frequency of the obtained first clock signal and the clock frequency of the second clock signal corresponding to the oscillation module 20 exceeds the preset range, so as to avoid adding an additional calibration clock source in the clock calibration circuit, thereby achieving the purpose of reducing the design cost of the clock calibration circuit, and achieving the purpose of reducing the design cost of the clock chip.
Thus, based on the clock calibration circuit provided by the application, the real-time clock module 10 can also be designed by separating from a system clock source, thereby achieving the purpose of simplifying the clock calibration circuit; moreover, the clock extraction module 30 obtains the first clock signal of the communication module 40, and uses the obtained first clock signal as a clock reference signal, which can also reduce the calibration link of the clock precision required by the clock calibration circuit when the clock calibration circuit leaves the factory, thereby achieving the purpose of further reducing the design cost of the clock calibration circuit.
A clock chip may be understood as a chip comprising a clock calibration circuit and a calibrated clock source may be understood as a clock source generating a reference clock signal.
It can be understood that the calibration principle of the clock calibration circuit provided in the embodiment of the present application is to utilize the clock information included in the communication module 40, that is, utilize the clock information with higher precision as the reference clock signal for calibrating the oscillation module 20, so as to avoid designing a calibration clock source in the clock calibration circuit separately, that is, without separately setting a clock chip, and further achieve the purpose of simplifying the design cost of the clock calibration circuit.
The clock information included in the communication module 40 may be from a system clock source of the electronic device, that is, the clock information included in the communication module 40 has higher precision, so that the first clock signal acquired from the communication module 40 can meet the calibration requirement for the second clock signal corresponding to the oscillation module 20.
As shown in fig. 2, the time precision corresponding to the real-time clock module 10 may be improved by obtaining the first clock signal of the communication module 40 and obtaining the second clock signal corresponding to the oscillation module 20, comparing the clock frequency of the first clock signal of the communication module 40 with the clock frequency of the second clock signal corresponding to the oscillation module 20 to determine whether an error between the clock frequency of the first clock signal and the clock frequency of the second clock signal satisfies a preset range, calibrating the second clock signal using the first clock signal as a reference clock signal when the clock frequency error between the first clock signal and the second clock signal exceeds the preset range, and updating the real-time clock module 10 based on the calibrated second clock signal.
For example, the clock frequency of the second clock signal corresponding to the oscillation module 20 is set to be about 1Hz, a fluctuation tolerance of 0.6Hz to 2Hz exists due to manufacturing process reasons, and a known clock signal (for example, the first clock signal) of 10Hz (corresponding to a signal period of 100 milliseconds) is used as a reference clock signal; assuming that the calibrated clock frequency is 2Hz (the corresponding period is 600 ms), two rising and falling edges of the 10Hz reference signal are used as counters, that is, one period (100 ms) is counted twice, the 2Hz signal (the period is 600 ms) is counted 10 times, and the comparison with the target 1Hz counted 20 times is smaller, that is, the current clock frequency is too fast, and it is necessary to adjust the capacitance, resistance and other devices of the oscillation module 20 to adjust the clock frequency of the second clock signal, and then the comparison and judgment are performed until the difference between the period count value of the calibrated clock frequency and the target is smaller than the set value, so as to calibrate the clock frequency of the second clock signal. Wherein, the set value can be 2, and the set value can be adjusted based on the requirement of calibration speed and precision.
Further, the clock signal in the present application may be a clock signal having a fixed period and a fixed duty cycle, and the calibrated clock may be counted using a high frequency reference clock for comparison with a set target value. Wherein, to improve the calibration accuracy, two edges of the reference clock may be counted to improve the calibration accuracy to 1/2 reference clock cycles.
Optionally, the communication module 40 includes any one of a system power management interface, a serial peripheral interface, a first integrated circuit, and a second integrated circuit.
It can be understood that, because the communication modules such as the system power management interface, the serial peripheral interface, the first integrated circuit, and the second integrated circuit may need to perform information interaction with other modules, and because the information needs to be modulated and mediated at the transmitting end and the receiving end in the interaction process, the communication module for information interaction needs to contain clock information with higher precision.
Moreover, in order to ensure the interaction quality of information, i.e. to ensure the precision requirement of clock information included in communication modules such as the system power management interface, the serial peripheral interface, the first integrated circuit, and the second integrated circuit, a clock signal provided by a system clock source is generally used as a clock signal of the communication modules such as the system power management interface, the serial peripheral interface, the first integrated circuit, and the second integrated circuit, i.e. the communication modules such as the system power management interface, the serial peripheral interface, the first integrated circuit, and the second integrated circuit can share a clock signal provided by the system clock source, thereby meeting the information interaction requirement of the communication modules.
The first Integrated Circuit may be understood as an Inter Integrated Circuit (IIC), and the second Integrated Circuit may be understood as an advanced Inter Integrated Circuit (IIIC).
Moreover, the communication module 40 may also be another communication interface or communication circuit on the electronic device, as long as the precision of the clock information included in the communication module 40 can meet the calibration requirement of the second clock signal corresponding to the oscillation module 20.
It should be noted that the clock frequency of the oscillating module 20 generating the second clock signal may be unknown (within the tolerance range) due to chip manufacturing process tolerances; therefore, manufacturing tolerances are taken into consideration when designing the oscillation module 20, i.e., the calibration of the clock frequency corresponding to the oscillation module 20 can be achieved by adjusting the resistance and capacitance of the oscillation module 20.
In one example, the clock frequency of the first clock signal and the clock frequency of the calibrated second clock signal may be integer multiples.
Specifically, in the process of adjusting the clock accuracy of the electronic device including the clock calibration circuit of the present application, in the process of first starting the electronic device, the clock extraction module 30 may obtain a first clock signal of the communication module 40, and use the obtained first clock signal as a clock reference signal; and when the error between the obtained first clock signal and the second clock signal corresponding to the oscillation module 20 exceeds the preset range, calibrating the second clock signal corresponding to the oscillation module 20 by using the first clock signal as a reference clock signal, and locking the calibrated second clock signal, so that the locked calibrated second clock signal is used as an update parameter of the real-time clock module, thereby realizing the adjustment of the clock precision.
As shown in fig. 3, an embodiment of the present application further provides a clock calibration method, which may be applied to the clock calibration circuit in the foregoing embodiment or an electronic device including the clock calibration circuit in the foregoing embodiment, where the clock calibration circuit includes a real-time clock module, an oscillation module, a clock extraction module, and a communication module, and the clock calibration method includes the following steps:
In this step, the clock information included in the communication module has higher precision, that is, the clock information included in the communication module can be used as a reference clock signal to calibrate the clock frequency corresponding to the oscillation module; therefore, the first clock signal of the communication module can be acquired through the clock extraction module, so that the acquired first clock signal is used as a reference clock signal, an additional calibration clock source is prevented from being added in the clock calibration circuit, and the purpose of reducing the design cost of the clock calibration circuit is achieved.
In this step, an error between the clock frequency of the first clock signal and the clock frequency of the second clock signal corresponding to the oscillation module, which exceeds a preset range, may be interpreted as a problem that the time generated based on the second clock signal has poor precision, that is, the time generated by the real-time clock module has poor precision.
Therefore, when the error between the clock frequency of the first clock signal and the clock frequency of the second clock signal exceeds the preset range, the first clock signal corresponding to the communication module can be used as a clock reference signal to calibrate the second clock signal, and the calibrated second clock signal is locked, so that the locked calibrated second clock signal can be used as an update parameter of the real-time clock module, and the purpose of reducing the design cost of the clock calibration circuit is achieved.
When the error between the clock frequency of the first clock signal and the clock frequency of the second clock signal corresponding to the oscillation module satisfies the preset range, the second clock signal corresponding to the oscillation module may be locked and used as an update parameter for implementing the clock module.
Therefore, the first clock signal corresponding to the communication module is used as the clock reference signal to calibrate the second clock signal, so that the additional calibration clock source added in the clock calibration circuit can be avoided, and the purpose of reducing the design cost of the clock calibration circuit is achieved.
Optionally, after the first clock signal of the communication interface is obtained by the clock extraction module, before the second clock signal is calibrated based on the first clock signal when an error between a clock frequency of the first clock signal and a clock frequency of a second clock signal corresponding to the oscillation module exceeds a preset range, the method further includes:
acquiring a clock period of the second clock signal;
and determining the clock frequency of the second clock signal based on the clock period of the second clock signal, and comparing the clock frequency of the second clock signal with the clock frequency of the first clock signal.
In this embodiment, the clock period of the second clock signal may be measured to determine the clock frequency of the second clock signal, and then determine whether the error between the clock frequency of the first clock signal and the clock frequency of the second clock signal corresponding to the oscillation module satisfies the preset range, so as to implement the comparison between the clock frequency of the second clock signal and the clock frequency of the first clock signal.
For a specific comparison process, reference may be made to the foregoing embodiments, which are not described herein again.
Optionally, the calibrating the second clock signal based on the first clock signal includes:
adjusting a target component in the oscillating module based on the first clock signal to calibrate the clock frequency, the target component including at least one of a capacitance, a resistance, and an inductance.
In this embodiment, the target component in the oscillation module may be adjusted to adjust the second clock signal corresponding to the oscillation module, so that an error between the adjusted second clock signal and the first clock signal satisfies a preset range, thereby adjusting the clock precision.
It can be understood that the adjustment of the oscillation module may be understood as an adjustment of a target component in the oscillation module, thereby implementing an adjustment of the clock frequency of the second clock signal.
In one example, the oscillation module comprises a capacitor and a resistor, which can be understood as that the oscillation module comprises a capacitor array and a resistor array; the adjustment of the target component in the oscillation module can be understood as adjusting the capacitor array and the resistor array in the oscillation module, so as to adjust the clock frequency of the second clock signal corresponding to the oscillation module.
In another example, the oscillating module comprises an inductor, which may be understood as the oscillating module comprises an array of inductors; the adjustment of the target component in the oscillation module can be understood as adjusting the inductance array in the oscillation module, so as to adjust the clock frequency of the second clock signal corresponding to the oscillation module.
In addition, the capacitor, the resistor, the inductor and other devices in the oscillation module can be set into a variable capacitor, a variable resistor and a variable inductor, so that the adjustment of the oscillation module can be realized by adjusting the capacitance value of the variable capacitor, the resistance value of the variable resistor and the inductance value of the variable inductor, and the aim of simplifying the circuit structure of the oscillation module is fulfilled.
According to the clock calibration method provided by the embodiment of the application, the first clock signal of the communication module is obtained through the clock extraction module; calibrating a second clock signal corresponding to the oscillation module based on the first clock signal when the error between the clock frequency of the first clock signal and the clock frequency of the second clock signal exceeds a preset range; updating the real-time clock module based on the calibrated second clock signal. Therefore, the first clock signal corresponding to the communication module is used as the clock reference signal to calibrate the second clock signal, so that the addition of an additional calibration clock source in the clock calibration circuit can be avoided, the aim of reducing the design cost of the clock calibration circuit is fulfilled, and the aim of reducing the design cost of the clock chip is fulfilled.
It should be noted that, in the clock calibration method provided in the embodiment of the present application, the execution subject may be a clock calibration device, or a control module in the clock calibration device for executing the clock calibration method. In the embodiments of the present application, a clock calibration method performed by a clock calibration device is taken as an example to describe the clock calibration device provided in the embodiments of the present application.
As shown in fig. 4, an embodiment of the present application further provides a clock calibration apparatus, where the apparatus 400 includes the clock calibration circuit in the foregoing embodiment, the clock calibration circuit includes a real-time clock module, an oscillation module, a clock extraction module, and a communication module, and the apparatus 400 further includes:
a first obtaining module 401, configured to obtain a first clock signal of the communication module through the clock extraction module;
a calibration module 402, configured to calibrate a second clock signal corresponding to the oscillation module based on the first clock signal when an error between a clock frequency of the first clock signal and a clock frequency of the second clock signal exceeds a preset range;
an updating module 403, configured to update the real-time clock module based on the calibrated second clock signal.
Optionally, the apparatus 400 further comprises:
the second acquisition module is used for acquiring the clock period corresponding to the oscillation module;
and the comparison module is used for determining the clock frequency of the second clock signal based on the clock period of the second clock signal and comparing the clock frequency of the second clock signal with the clock frequency of the first clock signal.
Optionally, the calibration module 402 adjusts a target component in the oscillation module based on the first clock signal to calibrate the clock frequency, where the target component includes at least one of a capacitor, a resistor, and an inductor.
The clock calibration apparatus in the embodiment of the present application may be an apparatus, and may also be a component, an integrated circuit, or a chip in an electronic device. The device can be mobile electronic equipment or non-mobile electronic equipment.
The clock calibration apparatus in the embodiment of the present application may be an apparatus having an operating system. The operating system may be an Android (Android) operating system, an ios operating system, or other possible operating systems, and embodiments of the present application are not limited specifically.
The clock calibration device provided in the embodiment of the present application can implement each process implemented in the method embodiment of fig. 3, and is not described here again to avoid repetition.
Optionally, as shown in fig. 5, an electronic device 500 is further provided in this embodiment of the present application, and includes a processor 502, a memory 501, and a program or an instruction stored in the memory 501 and executable on the processor 502, where the program or the instruction is executed by the processor 502 to implement each process of the above-mentioned embodiment of the clock calibration method, and can achieve the same technical effect, and no further description is provided here to avoid repetition.
It should be noted that the electronic device in the embodiment of the present application includes the mobile electronic device and the non-mobile electronic device described above.
Fig. 6 is a schematic diagram of a hardware structure of an electronic device implementing an embodiment of the present application.
The electronic device 600 includes, but is not limited to: a radio frequency unit 601, a network module 602, an audio output unit 603, an input unit 604, a sensor 605, a display unit 606, a user input unit 607, an interface unit 608, a memory 609, a processor 610, and the like.
Those skilled in the art will appreciate that the electronic device 600 may further comprise a power source (e.g., a battery) for supplying power to the various components, and the power source may be logically connected to the processor 610 through a power management system, so as to implement functions of managing charging, discharging, and power consumption through the power management system. The electronic device structure shown in fig. 6 does not constitute a limitation of the electronic device, and the electronic device may include more or less components than those shown, or combine some components, or arrange different components, and thus, the description is omitted here.
The processor 610 is configured to obtain a first clock signal of the communication module through the clock extraction module; calibrating a second clock signal corresponding to the oscillation module based on the first clock signal when the error between the clock frequency of the first clock signal and the clock frequency of the second clock signal exceeds a preset range; updating the real-time clock module based on the calibrated second clock signal.
Optionally, the processor 610 is configured to obtain a clock period of the second clock signal; and determining the clock frequency of the second clock signal based on the clock period of the second clock signal, and comparing the clock frequency of the second clock signal with the clock frequency of the first clock signal.
Optionally, the processor 610 is configured to adjust a target component in the oscillating module based on the first clock signal to calibrate the clock frequency, where the target component includes at least one of a capacitor, a resistor, and an inductor.
It is to be understood that, in the embodiment of the present application, the input Unit 604 may include a Graphics Processing Unit (GPU) 6041 and a microphone 6042, and the Graphics Processing Unit 6041 processes image data of a still picture or a video obtained by an image capturing apparatus (such as a camera) in a video capturing mode or an image capturing mode. The display unit 606 may include a display panel 6061, and the display panel 6061 may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit 607 includes a touch panel 6071 and other input devices 6072. A touch panel 6071, also referred to as a touch screen. The touch panel 6071 may include two parts of a touch detection device and a touch controller. Other input devices 6072 may include, but are not limited to, a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which are not described in detail herein. The memory 609 may be used to store software programs as well as various data including, but not limited to, application programs and an operating system. The processor 610 may integrate an application processor, which primarily handles operating systems, user interfaces, applications, etc., and a modem processor, which primarily handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 610.
The embodiments of the present application further provide a readable storage medium, where a program or an instruction is stored on the readable storage medium, and when the program or the instruction is executed by a processor, the process of the embodiment of the clock calibration method is implemented, and the same technical effect can be achieved, and in order to avoid repetition, details are not repeated here.
The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and so on.
The embodiment of the present application further provides a chip, where the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is configured to run a program or an instruction to implement each process of the above clock calibration method embodiment, and can achieve the same technical effect, and the details are not repeated here to avoid repetition.
It should be understood that the chips mentioned in the embodiments of the present application may also be referred to as system-on-chip, system-on-chip or system-on-chip, etc.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Further, it should be noted that the scope of the methods and apparatus of the embodiments of the present application is not limited to performing the functions in the order illustrated or discussed, but may include performing the functions in a substantially simultaneous manner or in a reverse order based on the functions involved, e.g., the methods described may be performed in an order different than that described, and various steps may be added, omitted, or combined. In addition, features described with reference to certain examples may be combined in other examples.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling an electronic device (such as a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present application.
Claims (10)
1. A clock calibration circuit is characterized by comprising a real-time clock module, an oscillation module, a clock extraction module, a communication module and a control module, wherein the first end of the clock extraction module is electrically connected with the communication module, the control module is respectively electrically connected with the second end of the clock extraction module, the oscillation module and the real-time clock module, and the oscillation module is also electrically connected with the real-time clock module;
the clock extraction module is configured to obtain a first clock signal of the communication module, calibrate, by the control module, the second clock signal based on the first clock signal when an error between a clock frequency of the first clock signal and a clock frequency of a second clock signal corresponding to the oscillation module exceeds a preset range, and update the real-time clock module based on the calibrated second clock signal.
2. The clock calibration circuit of claim 1, wherein the communication module comprises any one of a system power management interface, a serial peripheral interface, a first integrated circuit, a second integrated circuit;
the clock extraction module may obtain the first clock signal through any one of the power management interface, the serial peripheral interface, the first integrated circuit, and the second integrated circuit.
3. A clock calibration method applied to the clock calibration circuit according to claim 1 or 2, wherein the clock calibration circuit comprises a real-time clock module, an oscillation module, a clock extraction module and a communication module, and the method comprises:
acquiring a first clock signal of the communication module through the clock extraction module;
calibrating a second clock signal based on the first clock signal when the error between the clock frequency of the first clock signal and the clock frequency of the second clock signal corresponding to the oscillation module exceeds a preset range;
updating the real-time clock module based on the calibrated second clock signal.
4. The method according to claim 3, wherein after the obtaining of the first clock signal of the communication interface by the clock extraction module, before calibrating the second clock signal based on the first clock signal when an error between a clock frequency of the first clock signal and a clock frequency of the second clock signal corresponding to the oscillation module exceeds a preset range, the method further comprises:
acquiring a clock period of the second clock signal;
and determining the clock frequency of the second clock signal based on the clock period of the second clock signal, and comparing the clock frequency of the second clock signal with the clock frequency of the first clock signal.
5. The method of claim 3 or 4, wherein calibrating the second clock signal based on the first clock signal comprises:
adjusting a target component in the oscillating module based on the first clock signal to calibrate the clock frequency, the target component including at least one of a capacitance, a resistance, and an inductance.
6. A clock calibration apparatus, comprising the clock calibration circuit of claim 1 or 2, the clock calibration circuit comprising a real-time clock module, an oscillation module, a clock extraction module, and a communication module, the apparatus further comprising:
the first acquisition module is used for acquiring a first clock signal of the communication module through the clock extraction module;
the calibration module is used for calibrating the second clock signal based on the first clock signal under the condition that the error between the clock frequency of the first clock signal and the clock frequency of the second clock signal corresponding to the oscillation module exceeds a preset range;
and the updating module is used for updating the real-time clock module based on the calibrated second clock signal.
7. The apparatus of claim 6, further comprising:
the second acquisition module is used for acquiring the clock period corresponding to the oscillation module;
and the comparison module is used for determining the clock frequency of the second clock signal based on the clock period of the second clock signal and comparing the clock frequency of the second clock signal with the clock frequency of the first clock signal.
8. The apparatus according to claim 6 or 7, wherein the calibration module is configured to adjust a target component in the oscillation module based on the first clock signal to calibrate the clock frequency, the target component comprising at least one of a capacitor, a resistor, and an inductor.
9. An electronic device comprising a processor, a memory, and a program or instructions stored on the memory and executable on the processor, the program or instructions when executed by the processor implementing the steps of the clock calibration method according to any one of claims 3 to 5.
10. A readable storage medium, on which a program or instructions are stored, which when executed by a processor implement the steps of the clock calibration method according to any one of claims 3 to 5.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114567351A (en) * | 2022-02-28 | 2022-05-31 | 易兆微电子(杭州)股份有限公司 | Bluetooth module and clock generation method thereof |
| CN116090388A (en) * | 2022-12-21 | 2023-05-09 | 海光信息技术股份有限公司 | Method for generating prediction model of internal voltage of chip, prediction method and related device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104702278A (en) * | 2013-12-10 | 2015-06-10 | 炬芯（珠海）科技有限公司 | Methods and device for calibrating frequencies |
| CN106130547A (en) * | 2016-06-20 | 2016-11-16 | 大唐微电子技术有限公司 | A kind of clock frequency calibration steps and device |
| CN107579723A (en) * | 2017-08-04 | 2018-01-12 | 大唐微电子技术有限公司 | A kind of method and apparatus of calibrating clock frequency |
| JP2018085563A (en) * | 2016-11-21 | 2018-05-31 | ソニーセミコンダクタソリューションズ株式会社 | Oscillator and oscillation method |
| CN110109643A (en) * | 2019-03-14 | 2019-08-09 | 恒玄科技（上海）有限公司 | A kind of the usb audio terminal system on chip and synchronous clock calibrating method of no crystal oscillator |
| CN111934678A (en) * | 2020-09-28 | 2020-11-13 | 深圳英集芯科技有限公司 | Method for automatically calibrating clock frequency in chip and related product |
| CN112506266A (en) * | 2020-12-01 | 2021-03-16 | 珠海格力电器股份有限公司 | Timing calibration method and device of chip clock source and chip with clock source |
-
2021
- 2021-08-24 CN CN202110974293.3A patent/CN113641214A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104702278A (en) * | 2013-12-10 | 2015-06-10 | 炬芯（珠海）科技有限公司 | Methods and device for calibrating frequencies |
| WO2015085825A1 (en) * | 2013-12-10 | 2015-06-18 | 炬芯（珠海）科技有限公司 | Frequency calibration methods and apparatus |
| CN106130547A (en) * | 2016-06-20 | 2016-11-16 | 大唐微电子技术有限公司 | A kind of clock frequency calibration steps and device |
| JP2018085563A (en) * | 2016-11-21 | 2018-05-31 | ソニーセミコンダクタソリューションズ株式会社 | Oscillator and oscillation method |
| CN107579723A (en) * | 2017-08-04 | 2018-01-12 | 大唐微电子技术有限公司 | A kind of method and apparatus of calibrating clock frequency |
| CN110109643A (en) * | 2019-03-14 | 2019-08-09 | 恒玄科技（上海）有限公司 | A kind of the usb audio terminal system on chip and synchronous clock calibrating method of no crystal oscillator |
| CN111934678A (en) * | 2020-09-28 | 2020-11-13 | 深圳英集芯科技有限公司 | Method for automatically calibrating clock frequency in chip and related product |
| CN112506266A (en) * | 2020-12-01 | 2021-03-16 | 珠海格力电器股份有限公司 | Timing calibration method and device of chip clock source and chip with clock source |
Non-Patent Citations (2)
| Title |
|---|
| 刘明雍;张兵宇;张立川;: "多AUV协作时钟同步控制算法设计与实现", 西北工业大学学报, no. 06, 15 December 2013 (2013-12-15), pages 16 - 20 * |
| 张琦;: "一种高精度时钟产生电路的设计", 现代导航, no. 02, 15 April 2020 (2020-04-15), pages 42 - 46 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114567351A (en) * | 2022-02-28 | 2022-05-31 | 易兆微电子(杭州)股份有限公司 | Bluetooth module and clock generation method thereof |
| CN114567351B (en) * | 2022-02-28 | 2023-04-07 | 易兆微电子(杭州)股份有限公司 | Bluetooth module and clock generation method thereof |
| CN116090388A (en) * | 2022-12-21 | 2023-05-09 | 海光信息技术股份有限公司 | Method for generating prediction model of internal voltage of chip, prediction method and related device |
| CN116090388B (en) * | 2022-12-21 | 2024-05-17 | 海光信息技术股份有限公司 | Method for generating prediction model of internal voltage of chip, prediction method and related device |
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