CN113630561B - Television splice box circuit with intelligent control system - Google Patents

Television splice box circuit with intelligent control system Download PDF

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Publication number
CN113630561B
CN113630561B CN202110926118.7A CN202110926118A CN113630561B CN 113630561 B CN113630561 B CN 113630561B CN 202110926118 A CN202110926118 A CN 202110926118A CN 113630561 B CN113630561 B CN 113630561B
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pin
chip
pins
resistor
series
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CN113630561A (en
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胡腾飞
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Shenzhen Shengxian Technology Co ltd
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Shenzhen Shengxian Technology Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/222—Studio circuitry; Studio devices; Studio equipment
    • H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/2624—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects for obtaining an image which is composed of whole input images, e.g. splitscreen
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/222—Studio circuitry; Studio devices; Studio equipment
    • H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/268—Signal distribution or switching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/765—Interface circuits between an apparatus for recording and another apparatus
    • H04N5/775—Interface circuits between an apparatus for recording and another apparatus between a recording apparatus and a television receiver

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Direct Current Feeding And Distribution (AREA)

Abstract

The invention discloses a television splice box circuit with an intelligent control system, which comprises a power supply circuit, a control circuit, an HDMI interface switching circuit, an HDMI interface data processing circuit, an audio processing circuit, a display control circuit, a projection light processing circuit and a projection lens interface circuit, wherein the two paths of HDMI video sources can be switched by the one projection unit circuit, the mobile phone APP is provided for being connected with the television splice box circuit in a wireless mode to switch the video sources, four projection pictures can be spliced by the television splice box circuit, four pictures can be watched at the same time, one projection unit circuit is arranged in a circuit drawing, the other three projection unit circuits are the same as the first unit circuit, and the splicing mode of the pictures has larger projection area and the multi-channel video pictures can be watched and switched at the same time, so that the television splice box circuit has a certain application value.

Description

Television splice box circuit with intelligent control system
Technical Field
The invention relates to the field of video playing equipment, in particular to a television splice box circuit with an intelligent control system.
Background
The video pictures are played on the equipment to be watched, so that the video pictures become necessary products in life and work, such as watching television programs, playing propaganda videos and monitoring live pictures in partial industries, large-size videos with different channels are spliced and displayed for watching at the same time for certain specific industries due to the requirements of use environments, and the video sources of multiple channels can be flexibly switched, but some video playing equipment is difficult to meet the requirements.
Disclosure of Invention
In order to solve the problems, the circuit of the invention is matched with a projection lens to simultaneously throw four pictures to be displayed on a screen, the size of the pictures can be adjusted at will, the circuit can realize the self correction of the four pictures to ensure that the four pictures are spliced together without overlapping and gaps, the circuit drawing is a circuit of one projection unit, the other three projection unit circuits are the same as the circuit of the first unit, the control system is a multi-channel spliced projection picture formed by arranging the four projection unit circuits together, each projection unit circuit can be connected with two channels of HDMI video signals, and the channel switching can be carried out by keys in the circuit through connecting a wireless network and carrying out the channel switching through the wireless operation of a mobile phone APP.
The invention adopts the following technical scheme that the television splice box circuit with the intelligent control system comprises a power supply circuit, a control circuit, an HDMI interface switching circuit, an HDMI interface data processing circuit, an audio processing circuit, a display control circuit, a projection light processing circuit and a projection lens interface circuit, wherein the power supply circuit adjusts the power supply voltage in a corresponding range to supply power for each unit circuit, the control circuit can adjust the volume, channel selection and picture geometric correction, the HDMI interface switching circuit is responsible for switching the video of an HDMI interface, the HDMI interface data processing circuit is responsible for converting HDMI interface data into video decoding data, the audio processing circuit is responsible for converting digital audio coding data into analog audio signals, the display control circuit is responsible for converting video data into optical signals to be output to the projection lens interface circuit, the projection light processing circuit is responsible for providing red, green and blue light sources, and the projection lens interface circuit is responsible for realizing connection with a projection lens.
The 1 st pin of the J13 interface in the power supply circuit is connected with an external 5V power supply, an R114 resistor is connected to the anode of a D12 light-emitting diode in series after the power supply is grounded through a C166 capacitor and a C167 capacitor, the cathode of the power supply is grounded, the 1 st pin of the J13 interface is connected with the 4 th pin of a U20 voltage stabilizing block under the power supply is grounded through a C168 capacitor, the model of the U20 voltage stabilizing block is TPS71501DCK, the 2 nd pin of the U20 voltage stabilizing block is connected with the power supply ground, the 5 th pin of the U20 voltage stabilizing block is connected with the 1 st pin of an R116 resistor under the power supply is grounded through a C169 capacitor, the 1 st pin of the U20 voltage stabilizing block is connected with the R119 resistor to the power supply ground in series, and the 1 st pin of the U20 voltage stabilizing block is connected with the R118 resistor to the 5 th pin of the U20 voltage stabilizing block; the 2 nd pin of the J13 interface is grounded; the 1 st pin of the J13 interface is connected with the 1 st pin of a U21 voltage stabilizing block under C170 capacitance filtering, the 2 nd pin of the U21 voltage stabilizing block is connected with power ground, the 3 rd pin of the U21 voltage stabilizing block is connected with the 1 st pin of an R120 resistor, the 2 nd pin of the U21 voltage stabilizing block is connected with the 1 st pin of the J13 interface, the 5 th pin of the U21 voltage stabilizing block is connected with the 1 st pin of an L7 inductor, the 2 nd pin of the U21 voltage stabilizing block outputs 1.8V power under C171 capacitance filtering, the 4 th pin of the U21 voltage stabilizing block is connected with an R122 resistor to power ground in series, the 4 th pin of the U21 voltage stabilizing block is connected with the R123 resistor to the 2 nd pin of the L7 inductor in series, and the model of the U21 voltage stabilizing block is TPS62260DDCT; the 1 st pin of the J13 interface is connected with the 1 st pin of a U22 voltage stabilizing block after C172 capacitance filtering, the 2 nd pin of the U22 voltage stabilizing block is connected with power ground, the 3 rd pin of the U22 voltage stabilizing block is connected with the 1 st pin of an R120 resistor, the 5 th pin of the U22 voltage stabilizing block is connected with the 1 st pin of an L8 inductor, the 2 nd pin outputs a 1.2V power supply under C173 capacitance filtering, the 4 th pin of the U22 voltage stabilizing block is connected with an R124 resistor in series to power ground, the 4 th pin of the U22 voltage stabilizing block is connected with the 2 nd pin of the L8 inductor in series with an R125 resistor, and the model of the U22 voltage stabilizing block is TPS62260DDCT; the 1 st pin of the J13 interface is connected with the 1 st pin of a U23 voltage stabilizing block after C174 capacitance filtering, the 2 nd pin of the U23 voltage stabilizing block is connected with power ground, the 3 rd pin of the U23 voltage stabilizing block is connected with the 1 st pin of an R120 resistor, the 5 th pin of the U23 voltage stabilizing block is connected with the 1 st pin of an L9 inductor, the 2 nd pin outputs a 3.3V power supply under C175 capacitance filtering, the 4 th pin of the U23 voltage stabilizing block is connected with an R126 resistor to power ground in series, the 4 th pin of the U23 voltage stabilizing block is connected with the 2 nd pin of the L9 inductor in series, and the model of the U23 voltage stabilizing block is TPS62260DDCT; the 1 st pin of J13 interface connects the 1 st pin of U24 steady voltage piece after the electric capacity filtering of C176, the 2 nd pin of U24 steady voltage piece connects power ground, the 1 st pin of R120 resistance is connected to the 3 rd pin of U24 steady voltage piece, the 1 st pin of L10 inductance is connected to the 5 th pin of U24 steady voltage piece, and the 1 st pin of C177 electric capacity is connected to its 2 nd pin, the 4 th pin of U24 steady voltage piece is in series with R128 resistance to power ground, the 4 th pin of U24 steady voltage piece is in series with R129 resistance to the 2 nd pin of L10 inductance, the 1 st pin of R121 resistance is connected to the 1 st pin of R120 resistance, the model of U24 steady voltage piece is TPS62260DDCT.
The core device of the control circuit is an MSP430F2274IDAR chip U13, pins 2 and 16 of the U13 are connected with an R77 resistor in series to a pin 2 of an R116 resistor in the power circuit under the capacitance filtering of C117 and C118, pins 4 and 15 of the U13 are connected with power ground, pin 3 of the U13 is connected with a pin 2 of a U6 chip, pin 6 of the U13 is connected with a pin 2 of a U9 chip, pin 7 of the U13 is connected with a pin 2 of an R75 resistor to an R77 resistor in series, pin 7 of the U13 is connected with a pin C128 capacitor to power ground, pin 14 of the U13 is connected with a pin 1 of a SW1 switch, pin 3 and pin 6 of the SW1 switch are connected with a pin 2 of the R116 resistor in the power circuit in series, pin 1 and pin 4 of the SW1 switch are connected with an R96 resistor to power ground, pin 2C 141 of the SW1 switch is connected with a capacitor to the ground, pin 20 of the U13 is connected with a pin 2 of the U13, and pin 14 of the U13 is connected with a pin 2 of the U13 in series; the 3 rd pin of the U14 is connected with a power supply ground, the 5 th pin of the U14 is connected with the 2 nd pin of the R116 resistor in the power supply circuit, the 4 th pin of the U14 is connected with the cathode of the D7 light-emitting diode in series with the R81 resistor, the anode of the U14 is connected with a 3.3V power supply, and the model of the U14 is SN74AUP1G07DCK which is mainly used for signal level conversion; the 3 rd pin of the U16 is connected with a power supply ground, the 5 th pin of the U16 is connected with the 2 nd pin of the R116 resistor in the power supply circuit, the 4 th pin of the U16 is connected with the cathode of the D9 light-emitting diode in series, the anode of the U16 is connected with a 3.3V power supply, and the model SN74AUP1G07DCK of the U16 is mainly used for signal level conversion; the 3 rd pin of the U17 is connected with a power supply ground, the 5 th pin of the U17 is connected with the 2 nd pin of the R116 resistor in the power supply circuit, the 4 th pin of the U17 is connected with the cathode of the D10 light-emitting diode in series with the R87 resistor, the anode of the U17 is connected with a 3.3V power supply, and the model of the U17 is SN74AUP1G07DCK which is mainly used for signal level conversion; the 3 rd pin of the U6 is connected with a power supply ground, the 5 th pin of the U6 is connected with a 1.8V power supply under the filtering of a C89 capacitor, the 4 th pin of the U6 is connected with an R49 resistor in series to the cathode of a D2 light-emitting diode, the anode of the U6 is connected with a 3.3V power supply, and the model of the U6 is SN74AUP1G06DCKR which is mainly used for signal level conversion; the 3 rd pin of the U8 is connected with a power supply ground, the 5 th pin of the U8 is connected with a 1.8V power supply under the filtering of a C97 capacitor, the 4 th pin of the U8 is connected with an R51 resistor in series to the cathode of a D3 light-emitting diode, the anode of the U8 is connected with the 3.3V power supply, and the model of the U8 is SN74AUP1G07DCK which is mainly used for signal level conversion; the 3 rd pin of the U9 is connected with a power supply ground, the 5 th pin of the U9 is connected with a 1.8V power supply under the filtering of a C100 capacitor, the 4 th pin of the U9 is connected with a resistor R57 in series to the cathode of a D5 light-emitting diode, the anode of the U9 is connected with a 3.3V power supply, and the model of the U9 is SN74AUP1G06DCKR which is mainly used for signal level conversion; the 15 th pin of U01 in the control circuit is connected with the power supply ground, the 8 th pin of U01 in the control circuit is connected with the R045 resistor to the 3.3V power supply in series under the filtering of the C040 and C041 capacitance, the 1 st pin of U01 is connected with the R08 resistor to the 3.3V power supply in series, the 3 rd pin of U01 is connected with the R07 resistor to the 3.3V power supply in series, the 18 th pin of U01 is connected with the R05 resistor to the 3.3V power supply in series, the 17 th pin of U01 is connected with the R06 resistor to the 3.3V power supply in series, the 16 th pin of U01 is connected with the R09 resistor to the power supply ground in series, the 4 th pin of U01 is connected with the C143 capacitor to the power supply ground in series, the 4 th pin of U01 is connected with the R99 resistor to the 2 nd pin of R116 in the power supply circuit, the 4 th pin of U01 is connected with the R101 resistor to the 1 st and 3 pins of the SP2 switch, and the 4 th and 2 pins of the SP2 switch are connected with the power supply ground; the 5 th pin of the U01 is connected with a C162 capacitor in series to the power ground, the 4 th pin of the U01 is connected with a R105 resistor in series to the 2 nd pin of a R116 in the power circuit, the 4 th pin of the U01 is connected with a R108 resistor in series to the 1 st pin and the 3 rd pin of an SP3 switch, and the 4 th pin and the 2 nd pin of the SP3 switch are connected with the power ground; the 6 th pin of the U01 is connected with a C165 capacitor to the power ground in series, the 4 th pin of the U01 is connected with a R111 resistor to the 2 nd pin of a R116 resistor in the power circuit in series, the 4 th pin of the U01 is connected with a R113 resistor to the 1 st pin and the 3 rd pin of the SP4 switch in series, and the 4 th pin and the 2 nd pin of the SP4 switch are connected with the power ground; the 7 th pin of the U01 is connected with a C163 capacitor to the power ground in series, the 4 th pin of the U01 is connected with a R106 resistor to the 2 nd pin of R116 in the power circuit in series, the 4 th pin of the U01 is connected with a R109 resistor to the 1 st pin and the 3 rd pin of the SP5 switch in series, and the 4 th pin and the 2 nd pin of the SP5 switch are connected with the power ground; the 20 th pin of the U01 is connected with a C161 capacitor to the power ground in series, the 4 th pin of the U01 is connected with a R104 resistor to the 2 nd pin of a R116 in the power circuit in series, the 4 th pin of the U01 is connected with a R107 resistor to the 1 st pin and the 3 rd pin of the SP1 switch in series, the 4 th pin and the 2 nd pin of the SP1 switch are connected with the power ground, and the model of the U01 is ESP-12E and is mainly used for being connected with a wireless WIFI network; the 19 th pin and the 20 th pin of the U01 are sequentially connected with the 4 th pin and the 5 th pin of the Pa1 connector, the 1 st pin and the 2 nd pin of the Pa1 connector are connected with the 1 st pin of the J13 interface in the power circuit, the 3 rd pin of the Pa1 connector is connected with the power ground, and the I2C buses of the 4 th pin and the 5 th pin of the Pa1 connector are used for connecting the circuits of the 4 projection units together for unified control.
The core device of the HDMI interface switching circuit is a TS3DV642A0RUAR chip U12 which is mainly used for switching HDMI signals, a 43 rd pin of the U12 is connected with power ground, a 1 st pin of the U12 is connected with a 1 st pin of a C177 capacitor in the power circuit under C129 capacitor filtering, 31, 32, 33, 34, 35, 36, 37 and 38 th pins of the U12 are sequentially connected with 12 th, 10 th, 3 th, 1 th, 6 th, 4 th, 9 th and 7 th pins of an HDMI1 interface, and 18 th, 19 th, 41 nd and 42 th pins of the U12 are sequentially connected with 13 th, 19 th, 16 th and 15 th pins of the HDMI1 interface; the pins 22, 23, 24, 25, 26, 27, 28 and 29 of the U12 are sequentially connected with pins 12, 10, 3, 1, 6, 4, 9 and 7 of an HDMI2 interface, pins 20, 21, 39 and 40 of the U12 are sequentially connected with pins 13, 19, 16 and 15 of the HDMI2 interface, pins 2, 17 and 16 of the U12 are sequentially connected with pins 36, 37 and 38 of the U13 in the control circuit, pins 10, 11, 7 and 8 of the U12 are sequentially connected with pins 6, 1, 3 and 4 of the U10, pins 5, 6, 12 and 13 of the U12 are sequentially connected with pins 6, 1, 3 and 4 of a U11 chip, pins 2 of the U12 are connected with a power supply ground, pins 5 of the U12 are connected with a 3.3V power supply, pins 3 of the U12 are connected with pins 1 of D8, pins 4 of the U12 are sequentially connected with pins 36, 37 and 38 of the U12, pins 10, 11 and pins 4 of the U12 are sequentially connected with pins 6, 1 and 18 of the U12 are connected with pins 1 of the U11 of the U12, and pins 1 of the U12 are connected with Q tube.
The core device of the HDMI interface data processing circuit is an ITE6801 chip U15, pins 26, 27, 28, 29, 31, 32, 33 and 34 of the U15 are sequentially connected with pins 13, 12, 6, 5, 8, 7, 11 and 10 of U12 in the HDMI interface switching circuit, pin 16 of the U15 is connected with pin 5 of the HDMI interface switching circuit U18 in series with R71 resistor, pin 17 of the U15 is connected with pin 6 of the HDMI interface switching circuit U18 in series with R73 resistor, pins 25, 30, 35 and 40 of the U15 are connected with 3.3V power under C122, C123, C124, C125 and C126 capacitor filter, pin 24 of the U15 is connected with 3.3V power under C127 and C130 capacitor filter, pin 24 of the U15 is connected with 1.2V power under C131 capacitor filter, pin 23 of the U15 is connected with 1.2V power under C135 and C137 capacitor filter inductor to 1.2V power under F8 capacitor filter, the 37 th pin of the U15 is connected with F9 inductance to 1.2V power supply in series under C138 and C140 capacitance filter, the 7 th, 15, 43, 48, 64 and 71 th pins of the U15 are connected with 1.2V power supply under C156, C157, C158, C159, C160, C154 and C155 capacitance filter, the R103 resistor is connected in parallel between the 38 th pin and the 39 th pin of the U15, the X3 crystal oscillator is connected in parallel between the 38 th pin and the 39 th pin of the U15, the 38 th pin of the U15 is connected with C152 capacitance to power supply ground in series, the 39 th pin of the U15 is connected with C153 capacitance to power supply ground in series, the 19 th pin of the U15 is connected with R69 resistance to the 14 th pin of the U12 of the HDMI interface switching circuit, the 6 th, 50, 55, 63, 70 th and 76 th pins of the U15 are connected with 1.8V power supply under C113, C112 and C114 capacitance filter, the 20 th pin of the U15 is connected with 3.3V power supply under C111 capacitance filter, the 39 th pin of the U15 is connected with the R33 th pin of the U15 in series, pins 5, 4, 3, 2, 1, 74, 73 and 72 of the U15 are sequentially connected with pins 1, 2, 3, 4, 5, 6, 7 and 8 of the RA1 resistor, pins 69, 68, 67, 66, 65, 62, 61 and 60 of the U15 are sequentially connected with pins 1, 2, 3, 4, 5, 6, 7 and 8 of the RA2 resistor, and pins 59, 58, 57, 56, 54, 53, 52 and 51 of the U15 are sequentially connected with pins 1, 2, 3, 4, 5, 6, 7 and 8 of the RA3 resistor.
The core device of the audio processing circuit is TLV320DAC3101 chip Ua2 which is mainly used for converting digital audio data into analog audio signals, pins 2 and 3 of the Ua2 are connected with a 1.8V power supply under Ca69 and Ca68 capacitance filtering, a 3.3V power supply in the power supply circuit is connected with a1 st pin of a Fa3 inductor, a2 nd pin of the Fa3 inductor is connected with a 17 th pin of the Ua2 under Ca14 capacitance filtering, a 17 th pin of the Ua2 is externally connected with Ca66 and Ca15 capacitance to ground filtering, a2 nd pin of the Fa3 inductor is connected with a 28 th pin of the Ua2 under Ca67 and Ca59 capacitance filtering, pins 33, 16, 18, 20, 25 and 29 of the Ua2 are connected with a power supply ground, pins 21 and 24 of the Ua2 are connected with 1 st pin of a J13 interface of the power supply circuit under Ca65, ca63 and Ca64 capacitance filtering, the 9 th pin and the 10 th pin of Ua2 are sequentially connected with the 14 th pin and the 13 th pin of U15 in the HDMI interface data processing circuit, the 19 th pin, the 22 th pin, the 23 th pin and the 26 th pin of Ua2 are sequentially connected with the 4 th pin, the 3 rd pin, the 2 nd pin and the 1 st pin of a Ja5 connector, the 30 th pin of Ua2 is connected with the 3 rd pin of a Ja2 interface in series with a C1 capacitor, the 27 th pin of Ua2 is connected with the 2 nd pin of the Ja2 interface in series with a Ca2 capacitor, the 1 st pin of the Ja2 connector is connected with a power supply ground, the 5 th pin, the 6 th pin, the 7 th pin and the 8 th pin of Ua2 are sequentially connected with the 1 st pin of an R92 resistor, an R93 resistor, an R95 resistor, the 2 nd pin of an R93 resistor, the R95 resistor and the 2 nd pin of an R98 resistor are sequentially connected with the 42 nd pin, 45, 46 and the 41 nd pin of U15 in the HDMI interface data processing circuit.
The C4, D6, D8, D10, E4, E13, F4, G12, H4, H12, J3, J13, K4, K12, L3, M4, M5, M8, M12, G13, C6, C8, F6, F7, F8, F9, F10, G6, G7, G8, G9, G10, H6, H7, H8, H9, H10, J6, J7, J8, J9, J10, K6, K7, K8, K9, K10 pins of the DPP3435 chip U5G in the display control circuit are connected with a power supply ground, the DPP3435 chip U5H has the structure that the pins D3, E3, M10, L13, H13, F13, D9, C5, D7, D12, J4, J12, K3, L4, L12, M6, M9 and C3 are externally connected with C61, C62, C63, C64, C65, C66, C67, C68, C69, C70, C71, C72 and C75, and are subjected to capacitive-to-ground filtering, the pins C7, C9, D4, E12, F12, K13 and M11 of the DPP3435 chip U5H are connected with a 1.8V power supply under the capacitive filtering of C77, C78, C79, C80 and C81, the M3, M7, N3 and N7 pins of the DPP3435 chip U5H are connected with an R59 resistor to a 1.8V power supply in series under the capacitive filtering of C81, C83, C84 and C85, the H2 pin of the DPP3435 chip U5H is connected with a C56 and C57 capacitor to the G3 and H3 pins of the DPP3435 chip U5H in series, the G3 and H3 pins of the DPP3435 chip U5H are connected with an F4 magnetic bead to the power supply ground in series, the J2 and H2 pin of the DPP3435 chip U5H is connected with an F3 magnetic bead to the D3 pin of the DPP3435 chip U5H in series, the R38 resistor is connected between the H1 and J1 pins of the DPP3435 chip U5A in parallel, the H1 pin of the DPP3435 chip U5A is connected with the 1 st pin of the X2 crystal oscillator, the J1 pin of the DPP3435 chip U5A is connected with the R41 resistor in series to the 3 rd pin of the X2 crystal oscillator, the 3 rd pin of the X2 crystal oscillator is connected with the C76 capacitor to the power ground in series, the C10 pin of the DPP3435 chip U5A is connected with the power ground, the R37 resistor in series with the A13 pin of the DPP3435 chip is connected with the 6 th pin of the U4 chip, the R39 resistor in series with the B13 pin of the DPP3435 chip U5A is connected with the 5 th pin of the U4 chip, the B12 pin of the DPP3435 chip U5A is connected with the R34 resistor in series to the 2 nd pin of the U4 chip, the A14 pin of the DPP3435 chip U5A is connected with the R40 resistor in series to the 1 st pin of the U4 chip, the 3 rd, 7 th and 8 th pins of the U4 chip are connected with the D11 pin of the DPP3435 chip U5H, the P2, P3, P1 and N5 pins of the DPP3435 chip U5E are sequentially connected with the 1 st pin of the R68, R74, R70 and R72 resistor in series, the 2 nd pins of the R68, R74, R70 and R72 resistor are sequentially connected with the 8 th, 75 th, 10 th and 9 th pins of the U15 chip in the HDMI interface data processing circuit, the K2, K1, L2, L1, M2, M1 and N2 are sequentially connected with the 16 th, 15 th, 13, 12, 11 and 9 th pins of the RA1 row resistor in the DPP3435 chip U5E, the pins R1, R2, R3, P4, R4, P5, R5 and P6 of the DPP3435 chip U5E are sequentially connected with the pins 16, 15, 14, 13, 12, 11, 10 and 9 of the RA2 resistor in the HDMI interface data processing circuit, the pins R6, P7, R7, P8, R8, P9, R9 and P10 of the DPP3435 chip U5E are sequentially connected with the pins 16, 15, 14, 13, 12, 11, 10 and 9 of the RA3 resistor in the HDMI interface data processing circuit, the pin N8 of the DPP3435 chip U5E is connected with the pin 3 of the U13 in the control circuit in series, and the DPP3435 chip is mainly used for converting video data into optical signals and outputting the optical signals to the projection lens interface circuit.
The 1 st and 2 nd pins of the U7 chip in the projection light processing circuit are connected with the 1 st pin of the J13 interface in the power circuit under the capacitance filtering of C92, C93, C94 and C95, the 10 th pin of the U7 chip is connected with the 1 st pin of the J13 interface in the power circuit under the capacitance filtering of C99, the 5 th, 12, 20, 23, 45, 46 and pins of the U7 chip are connected with the power ground, the 7 th pin of the U7 chip is connected with the R46 resistor in series with the C15 pin of the DPP3435 chip U5C, the 3 rd pin of the U7 chip is connected with the R47 resistor in series with the D14 pin of the DPP3435 chip U5C, the 8 th pin of the U7 chip is connected with the R48 resistor in series with the D15 pin of the DPP3435 chip U5C, the L5 inductor is connected between the 11 th pin and the 15 pin of the U7 chip in parallel, the 11 th pin of the U7 chip is connected with the cathode of the D4 diode, the anode C107 is connected with the power ground in series, the 15 th pin of the U7 chip is externally connected with a C105 capacitor to ground filter, the 17 th pin of the U7 chip is externally connected with a C106 capacitor to ground filter, the 19 th pin of the U7 chip is externally connected with a C103 capacitor to ground filter, the 18 th pin of the U7 chip is connected with the 1 st pin of the power circuit J13 interface under the C109 and C110 capacitor filter, the 21 st pin of the U7 chip is externally connected with a C108 capacitor filter and then is connected with a 1.8V power supply, an L6 inductor is connected between the 24 th pin and the 29 th pin of the U7 chip in parallel, the 29 th pin of the U7 chip is connected with the D3 pin of the DPP3435 chip U5C, the 28 th pin, the 31 th pin and the 34 th pin of the U7 chip are sequentially connected with the A12, the B15 th pin and the B14 pin of the DPP3435 chip U5D, the 44 th pin, the 43 th pin and the 48 th pin and the 47 th pin of the U7 chip are sequentially connected with an L4 inductor, the 42 th pin, the 40, 39, the 38 th pin and the 37 th pin of the U7 chip are sequentially connected with the 1 st pin, 2, 3 and 4 th pin of the J7 chip, the J7 connector is used for being connected with a matched projection lens to provide red, green and blue light sources for the lens, the model number of U7 is PAD2005, and the model number of U7 is mainly used for providing a light source for the projection lens and providing partial power supply for a DPP3435 chip.
Pins 1 and 50 of a J8 connector in the projection lens interface circuit are connected with a 1.8V power supply under C55 capacitance filtering, pins 37 and 38 of the J8 connector are connected with a 1.8V power supply under C73 capacitance filtering, pins 2, 7, 12, 15, 20, 21, 22, 23, 25, 49, 48, 44, 39, 36, 31, 30 and 26 of the J8 connector are connected with power ground, pins 47, 46 and 45 of the J8 connector are sequentially connected with pins 17, 15 and 14 of the U7 chip, pins 3 and 4 of the J8 connector are sequentially connected with pins B2 and B1 of a DPP3435 chip U5B, pin 6 of the J8 connector is connected with a resistor R31 in series to pin A1 of the DPP3435 chip U5B, the 5 th pin of the J8 connector is connected with an R32 resistor in series to the A2 pin of the DPP3435 chip U5B, the 8 th, 9 th, 10 th, 11 th, 13 th, 14 th, 16 th, 17 th, 18 th, 19 th, 32 th, 33 th, 34 th, 35 th, 36 th, 40 th, 41 th, 42 th and 43 th pins of the J8 connector are sequentially connected with the A3 th, B3 th, A4 th, B4 th, A7 th, B7 th, A10 th, A11 th, B9 th, A9 th, B8 th, A8 th, B6 th, B5 th and A5 th pins of the DPP3435 chip U5B, the 23 th, 27 th and 28 th pins of the J8 connector are sequentially connected with the 6 th, 5 th and 1 th pins of the U4 chip in the display control circuit, and the model of the J8 connector is AXT550124, and the J8 connector is mainly used for connecting with a matched projector lens.
The invention has the beneficial effects that:
(1) The television splice box circuit of the intelligent control system can switch video sources through mobile phone APP wireless operation.
(2) According to the television splice box circuit of the intelligent control system, each picture can be connected with two HDMI video sources, and 8 video signals can be connected in total for switching and watching.
(3) The television splice box circuit of the intelligent control system can simultaneously put four pictures into the television splice box circuit to form four pairs of pictures
The pictures are simultaneously put on a screen to be played.
Drawings
FIG. 1 is a power circuit of an embodiment of the present application;
FIG. 2 is a steering circuit of an embodiment of the present application;
FIG. 3 is a steering circuit of an embodiment of the present application;
fig. 4 is an HDMI interface switching circuit of the embodiment of the present application;
fig. 5 is an HDMI interface data processing circuit of an embodiment of the present application;
FIG. 6 is an audio processing circuit of an embodiment of the present application;
FIG. 7 is a display control circuit of an embodiment of the present application;
FIG. 8 is a display control circuit of an embodiment of the present application;
FIG. 9 is a display control circuit of an embodiment of the present application;
FIG. 10 is a projection lamp light processing circuit of an embodiment of the present application;
FIG. 11 is a projection lens interface circuit of an embodiment of the present application;
Fig. 12 is a functional schematic of an embodiment of the present application.
Detailed Description
In order to facilitate an understanding of the inventive circuit, the inventive circuit is described in more detail below with reference to the drawings and specific examples. The preferred embodiment of the present circuit is shown in the drawings, but the invention can be embodied in many different forms and is not limited to the embodiment described in the specification. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Working principle:
the circuit of the invention cooperates with the projection lens to put four pictures at the same time so as to display the pictures on the screen, the size of the pictures can be adjusted at will, the circuit can realize the self correction of the four pictures so that the four pictures are spliced together without overlapping and gaps, the circuit drawing of the circuit is a circuit of one projection unit, and the other three projection unit circuits are the same as the circuit of the first unit.
Embodiments are described below:
as shown in fig. 12, a television splice box circuit with an intelligent control system comprises a power supply circuit, a control circuit, an HDMI interface switching circuit, an HDMI interface data processing circuit, an audio processing circuit, a display control circuit, a projection light processing circuit and a projection lens interface circuit, wherein the power supply circuit adjusts the power supply voltage in a corresponding range to supply power for each unit circuit, the control circuit can adjust the volume, channel selection and picture geometric correction, the HDMI interface switching circuit is responsible for switching the video of an HDMI interface, the HDMI interface data processing circuit is responsible for converting HDMI interface data into video decoding data, the audio processing circuit is responsible for converting digital audio coding data into analog audio signals, the display control circuit is responsible for converting video data into optical signals and outputting the optical signals to the projection lens interface circuit, the projection light processing circuit is responsible for providing red, green and blue light sources, and the projection lens interface circuit is responsible for realizing connection with a projection lens.
As shown in FIG. 1, the 1 st pin of the J13 interface in the power circuit connects an external 5V power supply, after being subjected to C166 and C167 capacitance to ground filtering, an R114 resistor is connected in series to the anode of the D12 light-emitting diode, the cathode of the power supply is connected with the ground, the 1 st pin of the J13 interface is connected with the 4 th pin of the U20 stabilizing block under the C168 capacitance filtering, the model of the U20 stabilizing block is TPS71501DCK, the 2 nd pin of the U20 stabilizing block is connected with the power ground, the 5 th pin of the U20 stabilizing block is connected with the 1 st pin of the R116 resistor under the C169 capacitance filtering, the 1 st pin of the U20 stabilizing block is connected with the R119 resistor to the power ground in series, and the 1 st pin of the U20 stabilizing block is connected with the R118 resistor to the 5 th pin of the U20 stabilizing block in series; the 2 nd pin of the J13 interface is grounded; the 1 st pin of the J13 interface is connected with the 1 st pin of a U21 voltage stabilizing block under C170 capacitance filtering, the 2 nd pin of the U21 voltage stabilizing block is connected with power ground, the 3 rd pin of the U21 voltage stabilizing block is connected with the 1 st pin of an R120 resistor, the 2 nd pin of the U21 voltage stabilizing block is connected with the 1 st pin of the J13 interface, the 5 th pin of the U21 voltage stabilizing block is connected with the 1 st pin of an L7 inductor, the 2 nd pin of the U21 voltage stabilizing block outputs 1.8V power under C171 capacitance filtering, the 4 th pin of the U21 voltage stabilizing block is connected with an R122 resistor to power ground in series, the 4 th pin of the U21 voltage stabilizing block is connected with the R123 resistor to the 2 nd pin of the L7 inductor in series, and the model of the U21 voltage stabilizing block is TPS62260DDCT; the 1 st pin of the J13 interface is connected with the 1 st pin of a U22 voltage stabilizing block after C172 capacitance filtering, the 2 nd pin of the U22 voltage stabilizing block is connected with power ground, the 3 rd pin of the U22 voltage stabilizing block is connected with the 1 st pin of an R120 resistor, the 5 th pin of the U22 voltage stabilizing block is connected with the 1 st pin of an L8 inductor, the 2 nd pin outputs a 1.2V power supply under C173 capacitance filtering, the 4 th pin of the U22 voltage stabilizing block is connected with an R124 resistor in series to power ground, the 4 th pin of the U22 voltage stabilizing block is connected with the 2 nd pin of the L8 inductor in series with an R125 resistor, and the model of the U22 voltage stabilizing block is TPS62260DDCT; the 1 st pin of the J13 interface is connected with the 1 st pin of a U23 voltage stabilizing block after C174 capacitance filtering, the 2 nd pin of the U23 voltage stabilizing block is connected with power ground, the 3 rd pin of the U23 voltage stabilizing block is connected with the 1 st pin of an R120 resistor, the 5 th pin of the U23 voltage stabilizing block is connected with the 1 st pin of an L9 inductor, the 2 nd pin outputs a 3.3V power supply under C175 capacitance filtering, the 4 th pin of the U23 voltage stabilizing block is connected with an R126 resistor to power ground in series, the 4 th pin of the U23 voltage stabilizing block is connected with the 2 nd pin of the L9 inductor in series, and the model of the U23 voltage stabilizing block is TPS62260DDCT; the 1 st pin of J13 interface connects the 1 st pin of U24 steady voltage piece after the electric capacity filtering of C176, the 2 nd pin of U24 steady voltage piece connects power ground, the 1 st pin of R120 resistance is connected to the 3 rd pin of U24 steady voltage piece, the 1 st pin of L10 inductance is connected to the 5 th pin of U24 steady voltage piece, and the 1 st pin of C177 electric capacity is connected to its 2 nd pin, the 4 th pin of U24 steady voltage piece is in series with R128 resistance to power ground, the 4 th pin of U24 steady voltage piece is in series with R129 resistance to the 2 nd pin of L10 inductance, the 1 st pin of R121 resistance is connected to the 1 st pin of R120 resistance, the model of U24 steady voltage piece is TPS62260DDCT.
As shown in fig. 2 and fig. 3, the core device of the control circuit is a MSP430F2274IDAR chip U13, pins 2 and 16 of the U13 are connected in series with an R77 resistor to a pin 2 of the R116 resistor in the power circuit under the capacitive filtering of C117 and C118, pins 4 and 15 of the U13 are connected to the power ground, pin 3 of the U13 is connected to a pin 2 of the U6 chip, pin 6 of the U13 is connected to a pin 2 of the U9 chip, pin 7 of the U13 is connected in series with an R75 resistor to a pin 2 of the R77 resistor, pin 7 of the U13 is connected in series with a C128 capacitor to the power ground, pin 14 of the U13 is connected in series with a pin 1 of the SW1 switch, pin 3 and pin 6 of the SW1 switch is connected in series with an R90 resistor to a pin 2 of the R116 resistor in the power circuit, pin 1 and pin 4 of the SW1 switch is connected in series with an R96 resistor to the power ground, pin 2 of the SW1 switch is connected in series with a pin C141 to a pin 2 of the U9 chip, pin 7 is connected in series with a pin 2 of the U13 to an R77 resistor, and pin 14 of the U13 is connected in series with a pin 14 of the U13 is connected to a pin 2 of the U13, and pin 14 of the U13 is connected to a pin 2 of the U13 is connected to the U13; the 3 rd pin of the U14 is connected with a power supply ground, the 5 th pin of the U14 is connected with the 2 nd pin of the R116 resistor in the power supply circuit, the 4 th pin of the U14 is connected with the cathode of the D7 light-emitting diode in series with the R81 resistor, the anode of the U14 is connected with a 3.3V power supply, and the model of the U14 is SN74AUP1G07DCK which is mainly used for signal level conversion; the 3 rd pin of the U16 is connected with a power supply ground, the 5 th pin of the U16 is connected with the 2 nd pin of the R116 resistor in the power supply circuit, the 4 th pin of the U16 is connected with the cathode of the D9 light-emitting diode in series, the anode of the U16 is connected with a 3.3V power supply, and the model SN74AUP1G07DCK of the U16 is mainly used for signal level conversion; the 3 rd pin of the U17 is connected with a power supply ground, the 5 th pin of the U17 is connected with the 2 nd pin of the R116 resistor in the power supply circuit, the 4 th pin of the U17 is connected with the cathode of the D10 light-emitting diode in series with the R87 resistor, the anode of the U17 is connected with a 3.3V power supply, and the model of the U17 is SN74AUP1G07DCK which is mainly used for signal level conversion; the 3 rd pin of the U6 is connected with a power supply ground, the 5 th pin of the U6 is connected with a 1.8V power supply under the filtering of a C89 capacitor, the 4 th pin of the U6 is connected with an R49 resistor in series to the cathode of a D2 light-emitting diode, the anode of the U6 is connected with a 3.3V power supply, and the model of the U6 is SN74AUP1G06DCKR which is mainly used for signal level conversion; the 3 rd pin of the U8 is connected with a power supply ground, the 5 th pin of the U8 is connected with a 1.8V power supply under the filtering of a C97 capacitor, the 4 th pin of the U8 is connected with an R51 resistor in series to the cathode of a D3 light-emitting diode, the anode of the U8 is connected with the 3.3V power supply, and the model of the U8 is SN74AUP1G07DCK which is mainly used for signal level conversion; the 3 rd pin of the U9 is connected with a power supply ground, the 5 th pin of the U9 is connected with a 1.8V power supply under the filtering of a C100 capacitor, the 4 th pin of the U9 is connected with a resistor R57 in series to the cathode of a D5 light-emitting diode, the anode of the U9 is connected with a 3.3V power supply, and the model of the U9 is SN74AUP1G06DCKR which is mainly used for signal level conversion; the 15 th pin of U01 in the control circuit is connected with the power supply ground, the 8 th pin of U01 in the control circuit is connected with the R045 resistor to the 3.3V power supply in series under the filtering of the C040 and C041 capacitance, the 1 st pin of U01 is connected with the R08 resistor to the 3.3V power supply in series, the 3 rd pin of U01 is connected with the R07 resistor to the 3.3V power supply in series, the 18 th pin of U01 is connected with the R05 resistor to the 3.3V power supply in series, the 17 th pin of U01 is connected with the R06 resistor to the 3.3V power supply in series, the 16 th pin of U01 is connected with the R09 resistor to the power supply ground in series, the 4 th pin of U01 is connected with the C143 capacitor to the power supply ground in series, the 4 th pin of U01 is connected with the R99 resistor to the 2 nd pin of R116 in the power supply circuit, the 4 th pin of U01 is connected with the R101 resistor to the 1 st and 3 pins of the SP2 switch, and the 4 th and 2 pins of the SP2 switch are connected with the power supply ground; the 5 th pin of the U01 is connected with a C162 capacitor in series to the power ground, the 4 th pin of the U01 is connected with a R105 resistor in series to the 2 nd pin of a R116 in the power circuit, the 4 th pin of the U01 is connected with a R108 resistor in series to the 1 st pin and the 3 rd pin of an SP3 switch, and the 4 th pin and the 2 nd pin of the SP3 switch are connected with the power ground; the 6 th pin of the U01 is connected with a C165 capacitor to the power ground in series, the 4 th pin of the U01 is connected with a R111 resistor to the 2 nd pin of a R116 resistor in the power circuit in series, the 4 th pin of the U01 is connected with a R113 resistor to the 1 st pin and the 3 rd pin of the SP4 switch in series, and the 4 th pin and the 2 nd pin of the SP4 switch are connected with the power ground; the 7 th pin of the U01 is connected with a C163 capacitor to the power ground in series, the 4 th pin of the U01 is connected with a R106 resistor to the 2 nd pin of R116 in the power circuit in series, the 4 th pin of the U01 is connected with a R109 resistor to the 1 st pin and the 3 rd pin of the SP5 switch in series, and the 4 th pin and the 2 nd pin of the SP5 switch are connected with the power ground; the 20 th pin of the U01 is connected with a C161 capacitor to the power ground in series, the 4 th pin of the U01 is connected with a R104 resistor to the 2 nd pin of a R116 in the power circuit in series, the 4 th pin of the U01 is connected with a R107 resistor to the 1 st pin and the 3 rd pin of the SP1 switch in series, the 4 th pin and the 2 nd pin of the SP1 switch are connected with the power ground, and the model of the U01 is ESP-12E and is mainly used for being connected with a wireless WIFI network; the 19 th pin and the 20 th pin of the U01 are sequentially connected with the 4 th pin and the 5 th pin of the Pa1 connector, the 1 st pin and the 2 nd pin of the Pa1 connector are connected with the 1 st pin of the J13 interface in the power circuit, the 3 rd pin of the Pa1 connector is connected with the power ground, and the I2C buses of the 4 th pin and the 5 th pin of the Pa1 connector are used for connecting the circuits of the 4 projection units together for unified control.
As shown in fig. 4, the core device of the HDMI interface switching circuit is a TS3DV642A0RUAR chip U12, which is mainly used for switching signals of HDMI, the 43 rd pin of the U12 is connected to the power ground, the 1 st pin of the U12 is connected to the 1 st pin of the C177 capacitor in the power circuit under the filtering of the C129 capacitor, the 31 st, 32, 33, 34, 35, 36, 37, 38 pins of the U12 are sequentially connected to the 12 th, 10, 3, 1, 6, 4, 9, 7 th pins of the HDMI1 interface, and the 18 th, 19 th, 41, 42 th pins of the U12 are sequentially connected to the 13 th, 19, 16 th, 15 th pins of the HDMI1 interface; the pins 22, 23, 24, 25, 26, 27, 28 and 29 of the U12 are sequentially connected with pins 12, 10, 3, 1, 6, 4, 9 and 7 of an HDMI2 interface, pins 20, 21, 39 and 40 of the U12 are sequentially connected with pins 13, 19, 16 and 15 of the HDMI2 interface, pins 2, 17 and 16 of the U12 are sequentially connected with pins 36, 37 and 38 of the U13 in the control circuit, pins 10, 11, 7 and 8 of the U12 are sequentially connected with pins 6, 1, 3 and 4 of the U10, pins 5, 6, 12 and 13 of the U12 are sequentially connected with pins 6, 1, 3 and 4 of a U11 chip, pins 2 of the U12 are connected with a power supply ground, pins 5 of the U12 are connected with a 3.3V power supply, pins 3 of the U12 are connected with pins 1 of D8, pins 4 of the U12 are sequentially connected with pins 36, 37 and 38 of the U12, pins 10, 11 and pins 4 of the U12 are sequentially connected with pins 6, 1 and 18 of the U12 are connected with pins 1 of the U11 of the U12, and pins 1 of the U12 are connected with Q tube.
As shown in FIG. 5, the core device of the HDMI interface data processing circuit is an ITE6801 chip U15, pins 26, 27, 28, 29, 31, 32, 33 and 34 of the U15 are sequentially connected with pins 13, 12, 6, 5, 8, 7, 11 and 10 of U12 in the HDMI interface switching circuit, pin 16 of the U15 is connected with pin 5 of the HDMI interface switching circuit U18 in series with a resistor R71, pin 17 of the U15 is connected with pin 6 of the HDMI interface switching circuit U18 in series with a resistor R73, pins 25, 30, 35 and 40 of the U15 are connected with 3.3V power under C122, C123, C124, C125 and C126 capacitive filtering, pin 24 of the U15 is connected with 3.3V power under C127 and C130 capacitive filtering, pin 24 of the U15 is connected with 1.2V power under C131 capacitive filtering, pin 23 of the U15 is connected with 1.2V power under C135 and C137 capacitive filtering to 1.2V power under F8, the 37 th pin of the U15 is connected with F9 inductance to 1.2V power supply in series under C138 and C140 capacitance filter, the 7 th, 15, 43, 48, 64 and 71 th pins of the U15 are connected with 1.2V power supply under C156, C157, C158, C159, C160, C154 and C155 capacitance filter, the R103 resistor is connected in parallel between the 38 th pin and the 39 th pin of the U15, the X3 crystal oscillator is connected in parallel between the 38 th pin and the 39 th pin of the U15, the 38 th pin of the U15 is connected with C152 capacitance to power supply ground in series, the 39 th pin of the U15 is connected with C153 capacitance to power supply ground in series, the 19 th pin of the U15 is connected with R69 resistance to the 14 th pin of the U12 of the HDMI interface switching circuit, the 6 th, 50, 55, 63, 70 th and 76 th pins of the U15 are connected with 1.8V power supply under C113, C112 and C114 capacitance filter, the 20 th pin of the U15 is connected with 3.3V power supply under C111 capacitance filter, the 39 th pin of the U15 is connected with the R33 th pin of the U15 in series, pins 5, 4, 3, 2, 1, 74, 73 and 72 of the U15 are sequentially connected with pins 1, 2, 3, 4, 5, 6, 7 and 8 of the RA1 resistor, pins 69, 68, 67, 66, 65, 62, 61 and 60 of the U15 are sequentially connected with pins 1, 2, 3, 4, 5, 6, 7 and 8 of the RA2 resistor, and pins 59, 58, 57, 56, 54, 53, 52 and 51 of the U15 are sequentially connected with pins 1, 2, 3, 4, 5, 6, 7 and 8 of the RA3 resistor.
As shown in fig. 6, the core device of the audio processing circuit is TLV320DAC3101 chip Ua2, which is mainly used for converting digital audio data into analog audio signals, pins 2 and 3 of Ua2 are connected with 1.8V power supply under Ca69 and Ca68 capacitive filtering, 3.3V power supply in the power supply circuit is connected with pin 1 of Fa3 inductor, pin 2 of Fa3 inductor is connected with pin 17 of Ua2 under Ca14 capacitive filtering, pin 17 of Ua2 is externally connected with Ca66 and Ca15 capacitive to ground filtering, pin 2 of Fa3 inductor is connected with pin 28 of Ua2 under Ca67 and Ca59 capacitive filtering, pins 33, 16, 18, 20, 25, 29 and 1 of Ua2 are connected with power ground, pins 21 and 24 of Ua2 are connected with pin 1 of the interface of power supply circuit J13 under Ca65, ca63 and Ca64 capacitive filtering, the 9 th pin and the 10 th pin of Ua2 are sequentially connected with the 14 th pin and the 13 th pin of U15 in the HDMI interface data processing circuit, the 19 th pin, the 22 th pin, the 23 th pin and the 26 th pin of Ua2 are sequentially connected with the 4 th pin, the 3 rd pin, the 2 nd pin and the 1 st pin of a Ja5 connector, the 30 th pin of Ua2 is connected with the 3 rd pin of a Ja2 interface in series with a C1 capacitor, the 27 th pin of Ua2 is connected with the 2 nd pin of the Ja2 interface in series with a Ca2 capacitor, the 1 st pin of the Ja2 connector is connected with a power supply ground, the 5 th pin, the 6 th pin, the 7 th pin and the 8 th pin of Ua2 are sequentially connected with the 1 st pin of an R92 resistor, an R93 resistor, an R95 resistor, the 2 nd pin of an R93 resistor, the R95 resistor and the 2 nd pin of an R98 resistor are sequentially connected with the 42 nd pin, 45, 46 and the 41 nd pin of U15 in the HDMI interface data processing circuit.
As shown in FIG. 7 and FIG. 8 and FIG. 9, pins C4, D6, D8, D10, E4, E13, F4, G12, H4, H12, J3, J13, K4, K12, L3, M4, M5, M8, M12, G13, C6, C8, F6, F7, F8, F9, F10, G6, G7, G8, G9, G10, H6, H7, H8, H9, H10, J6, J7, J8, J9, J10, K6, K7, K8, K9 and K10 of the DPP3435 chip U5G in the display control circuit are connected with a power supply ground, the DPP3435 chip U5H has the structure that the pins D3, E3, M10, L13, H13, F13, D9, C5, D7, D12, J4, J12, K3, L4, L12, M6, M9 and C3 are externally connected with C61, C62, C63, C64, C65, C66, C67, C68, C69, C70, C71, C72 and C75, and are subjected to capacitive-to-ground filtering, the pins C7, C9, D4, E12, F12, K13 and M11 of the DPP3435 chip U5H are connected with a 1.8V power supply under the capacitive filtering of C77, C78, C79, C80 and C81, the M3, M7, N3 and N7 pins of the DPP3435 chip U5H are connected with an R59 resistor to a 1.8V power supply in series under the capacitive filtering of C81, C83, C84 and C85, the H2 pin of the DPP3435 chip U5H is connected with a C56 and C57 capacitor to the G3 and H3 pins of the DPP3435 chip U5H in series, the G3 and H3 pins of the DPP3435 chip U5H are connected with an F4 magnetic bead to the power supply ground in series, the J2 and H2 pin of the DPP3435 chip U5H are connected with an F3 magnetic bead to the D3 pin of the DPP3435 chip U5H in series, R38 resistor is connected in parallel between H1 and J1 pins of the DPP3435 chip U5A, H1 pin of the DPP3435 chip U5A is connected with 1 pin of the X2 crystal oscillator, J1 pin of the DPP3435 chip U5A is connected with R41 resistor in series to 3 pin of the X2 crystal oscillator, 3 pin of the X2 crystal oscillator is connected with C76 capacitor to power ground, C10 pin of the DPP3435 chip U5A is connected with power ground, A13 pin of the DPP3435 chip A is connected with R37 resistor in series to 6 pin of the U4 chip, the B13 pin of the DPP3435 chip U5A is connected with the R39 resistor in series to the 5 th pin of the U4 chip, the B12 pin of the DPP3435 chip U5A is connected with the R34 resistor in series to the 2 nd pin of the U4 chip, the A14 pin of the DPP3435 chip U5A is connected with the R40 resistor in series to the 1 st pin of the U4 chip, the 3 rd, 7 th and 8 th pins of the U4 chip are connected with the D11 pin of the DPP3435 chip U5H, the P2, P3, P1 and N5 pins of the DPP3435 chip U5E are sequentially connected with the 1 st pin of the R68, R74, R70 and R72 resistor, the 2 nd pin of the R68, R74, R70 and R72 resistor are sequentially connected with the 8 th, 75, 10 and 9 pins of the U15 chip in the HDMI interface data processing circuit, the K2, K1, L1, M2, M1, N2, HDMI, and N1 pins of the HDMI interface data processing circuit, the R12, and the R12, 13 th pins of the DPP3435 chip U5E are sequentially connected with the R12, R70 and R72, the pins R1, R2, R3, P4, R4, P5, R5 and P6 of the DPP3435 chip U5E are sequentially connected with the pins 16, 15, 14, 13, 12, 11, 10 and 9 of the RA2 resistor in the HDMI interface data processing circuit, the pins R6, P7, R7, P8, R8, P9, R9 and P10 of the DPP3435 chip U5E are sequentially connected with the pins 16, 15, 14, 13, 12, 11, 10 and 9 of the RA3 resistor in the HDMI interface data processing circuit, the pin N8 of the DPP3435 chip U5E is connected with the pin 3 of the U13 in the control circuit in series, and the DPP3435 chip is mainly used for converting video data into optical signals and outputting the optical signals to the projection lens interface circuit.
As shown in FIG. 10, pins 1 and 2 of the U7 chip in the projection light processing circuit are connected with pin 1 of the J13 interface in the power circuit under the capacitive filtering of C92, C93, C94 and C95, pin 10 of the U7 chip is connected with pin 1 of the J13 interface in the power circuit under the capacitive filtering of C99, pins 5, 12, 20, 23, 45 and 46 of the U7 chip are connected with the power ground, pin 7 of the U7 chip is connected with pin R46 in series with pin C15 of the DPP3435 chip U5C, pin 3 of the U7 chip is connected with pin R47 in series with pin D14 of the DPP3435 chip U5C, pin 8 of the U7 chip is connected with pin R48 in series with pin D15 of the DPP3435 chip U5C, pin 11 and pin 15 of the U7 chip are connected with L5 inductor in parallel, pin 11 of the U7 chip is connected with the cathode of the D4 diode, and anode thereof is connected with the power ground in series with C107, the 15 th pin of the U7 chip is externally connected with a C105 capacitor to ground filter, the 17 th pin of the U7 chip is externally connected with a C106 capacitor to ground filter, the 19 th pin of the U7 chip is externally connected with a C103 capacitor to ground filter, the 18 th pin of the U7 chip is connected with the 1 st pin of the power circuit J13 interface under the C109 and C110 capacitor filter, the 21 st pin of the U7 chip is externally connected with a C108 capacitor filter and then is connected with a 1.8V power supply, an L6 inductor is connected between the 24 th pin and the 29 th pin of the U7 chip in parallel, the 29 th pin of the U7 chip is connected with the D3 pin of the DPP3435 chip U5C, the 28 th pin, the 31 th pin and the 34 th pin of the U7 chip are sequentially connected with the A12, the B15 th pin and the B14 pin of the DPP3435 chip U5D, the 44 th pin, the 43 th pin and the 48 th pin and the 47 th pin of the U7 chip are sequentially connected with an L4 inductor, the 42 th pin, the 40, 39, the 38 th pin and the 37 th pin of the U7 chip are sequentially connected with the 1 st pin, 2, 3 and 4 th pin of the J7 chip, the J7 connector is used for being connected with a matched projection lens to provide red, green and blue light sources for the lens, the model number of U7 is PAD2005, and the model number of U7 is mainly used for providing a light source for the projection lens and providing partial power supply for a DPP3435 chip.
As shown in FIG. 11, pins 1 and 50 of the J8 connector in the projection lens interface circuit are connected with a 1.8V power supply under C55 capacitive filtering, pins 37 and 38 of the J8 connector are connected with a 1.8V power supply under C73 capacitive filtering, pins 2, 7, 12, 15, 20, 21, 22, 23, 25, 49, 48, 44, 39, 36, 31, 30 and 26 of the J8 connector are connected with power ground, pins 47, 46 and 45 of the J8 connector are sequentially connected with pins 17, 15 and 14 of the U7 chip, pins 3 and 4 of the J8 connector are sequentially connected with pins B2 and B1 of the DPP3435 chip U5B, pin 6 of the J8 connector is connected with a resistor R31 in series with pin A1 of the DPP3435 chip U5B, the 5 th pin of the J8 connector is connected with an R32 resistor in series to the A2 pin of the DPP3435 chip U5B, the 8 th, 9 th, 10 th, 11 th, 13 th, 14 th, 16 th, 17 th, 18 th, 19 th, 32 th, 33 th, 34 th, 35 th, 36 th, 40 th, 41 th, 42 th and 43 th pins of the J8 connector are sequentially connected with the A3 th, B3 th, A4 th, B4 th, A7 th, B7 th, A10 th, A11 th, B9 th, A9 th, B8 th, A8 th, B6 th, B5 th and A5 th pins of the DPP3435 chip U5B, the 23 th, 27 th and 28 th pins of the J8 connector are sequentially connected with the 6 th, 5 th and 1 th pins of the U4 chip in the display control circuit, and the model of the J8 connector is AXT550124, and the J8 connector is mainly used for connecting with a matched projector lens.

Claims (9)

1. The television splice box circuit with the intelligent control system comprises a power supply circuit, a control circuit, an HDMI interface switching circuit, an HDMI interface data processing circuit, an audio processing circuit, a display control circuit, a projection light processing circuit and a projection lens interface circuit, wherein the power supply circuit adjusts power supply voltage in a corresponding range to supply power for each unit circuit, the control circuit is used for adjusting volume, channel selection and picture geometric correction, the HDMI interface switching circuit is responsible for switching video of an HDMI interface, the HDMI interface data processing circuit is responsible for converting HDMI interface data into video decoding data, the audio processing circuit is responsible for converting digital audio coding data into analog audio signals, the display control circuit is responsible for converting video data into optical signals and outputting the optical signals to the projection lens interface circuit, the projection light processing circuit is responsible for providing red, green and blue light sources, and the projection lens interface circuit is connected with a projection lens;
the television splice box circuit has four paths with the same structure, each path of television splice box circuit is a projection unit circuit, and the four projection unit circuits are combined to form a multi-channel spliced projection picture so as to cooperate with a projection lens to simultaneously throw four pictures on a screen, realize self-correction of the four pictures and adjustment of the size of the picture, ensure that the four pictures are spliced without overlapping and gaps, each projection unit circuit is connected with two channels of HDMI video signals, and the projection unit circuit further comprises a key unit and a wireless network unit for controlling channel switching.
2. The television splice box circuit with the intelligent control system according to claim 1, wherein the 1 st pin of the J13 interface in the power circuit is connected with an external 5V power supply, the anode of a D12 light emitting diode is connected with an R114 resistor in series after being subjected to C166 and C167 capacitance-to-ground filtering, the cathode of the power supply is connected with the ground, the 1 st pin of the J13 interface is connected with the 4 th pin of a U20 voltage stabilizing block under the C168 capacitance filtering, the 2 nd pin of the U20 voltage stabilizing block is connected with the ground, the 5 th pin of the U20 voltage stabilizing block is connected with the 1 st pin of an R116 resistor under the C169 capacitance filtering, the 1 st pin of the U20 voltage stabilizing block is connected with the R119 resistor to the ground in series, and the 1 st pin of the U20 voltage stabilizing block is connected with the 5 th pin of the U20 voltage stabilizing block in series; the 2 nd pin of the J13 interface is grounded; the 1 st pin of the J13 interface is connected with the 1 st pin of a U21 voltage stabilizing block under C170 capacitance filtering, the 2 nd pin of the U21 voltage stabilizing block is connected with power ground, the 3 rd pin of the U21 voltage stabilizing block is connected with the 1 st pin of an R120 resistor, the 2 nd pin of the U21 voltage stabilizing block is connected with the 1 st pin of the J13 interface, the 5 th pin of the U21 voltage stabilizing block is connected with the 1 st pin of an L7 inductor, the 2 nd pin of the U21 voltage stabilizing block outputs 1.8V power under C171 capacitance filtering, the 4 th pin of the U21 voltage stabilizing block is connected with an R122 resistor to power ground in series, and the 4 th pin of the U21 voltage stabilizing block is connected with an R123 resistor to the 2 nd pin of the L7 inductor in series; the 1 st pin of the J13 interface is connected with the 1 st pin of a U22 voltage stabilizing block after C172 capacitance filtering, the 2 nd pin of the U22 voltage stabilizing block is connected with power ground, the 3 rd pin of the U22 voltage stabilizing block is connected with the 1 st pin of an R120 resistor, the 5 th pin of the U22 voltage stabilizing block is connected with the 1 st pin of an L8 inductor, the 2 nd pin outputs a 1.2V power supply under C173 capacitance filtering, the 4 th pin of the U22 voltage stabilizing block is connected with an R124 resistor in series to the power ground, and the 4 th pin of the U22 voltage stabilizing block is connected with an R125 resistor in series to the 2 nd pin of the L8 inductor; the 1 st pin of the J13 interface is connected with the 1 st pin of a U23 voltage stabilizing block after C174 capacitance filtering, the 2 nd pin of the U23 voltage stabilizing block is connected with power ground, the 3 rd pin of the U23 voltage stabilizing block is connected with the 1 st pin of an R120 resistor, the 5 th pin of the U23 voltage stabilizing block is connected with the 1 st pin of an L9 inductor, the 2 nd pin outputs a 3.3V power supply under C175 capacitance filtering, the 4 th pin of the U23 voltage stabilizing block is connected with an R126 resistor in series to the power ground, and the 4 th pin of the U23 voltage stabilizing block is connected with an R127 resistor in series to the 2 nd pin of the L9 inductor; the 1 st pin of J13 interface connects the 1 st pin of U24 steady voltage piece after the electric capacity filtering of C176, the 2 nd pin of U24 steady voltage piece connects power ground, the 1 st pin of R120 resistance is connected to the 3 rd pin of U24 steady voltage piece, the 1 st pin of L10 inductance is connected to the 5 th pin of U24 steady voltage piece, and the 1 st pin of C177 electric capacity is connected to its 2 nd pin, the 4 th pin of U24 steady voltage piece is in series with R128 resistance to power ground, the 4 th pin of U24 steady voltage piece is in series with R129 resistance to the 2 nd pin of L10 inductance, the 1 st pin of R120 resistance is connected the 1 st pin of R121 resistance.
3. The television splice box circuit with the intelligent control system according to claim 2, wherein pins 2 and 16 of a U13 chip in the control circuit are connected with an R77 resistor to a pin 2 of an R116 resistor in the power circuit in series under the capacitive filtering of C117 and C118, pins 4 and 15 of the U13 chip are connected with power ground, pin 3 of the U13 chip is connected with a pin 2 of a U6 chip, pin 6 of the U13 chip is connected with a pin 2 of a U9 chip, pin 7 of the U13 chip is connected with an R75 resistor to a pin 2 of an R77 resistor in series, pin 7 of the U13 chip is connected with a C128 capacitor to power ground, pin 14 of the U13 chip is connected with a pin 1 of a SW1 switch in series, pin 3 and pin 6 of the SW1 switch are connected with a pin 2 of the R116 resistor in the power circuit in series, pin 1 and pin 4R 96 of the SW1 switch is connected with power ground, pin 2 of the SW1 switch is connected with a pin 2 of the U9 chip is connected with a pin 2 of the U13 chip, pin 7 of the U13 chip is connected with a pin 14 of the U13 chip is connected with a pin 1 of the U13 switch in series, pin 14 of the U13 chip is connected with a pin 2 of the U13 chip, and pin 14 of the U13 is connected with a pin 2 of the U13 chip is connected with a U13 resistor; the 3 rd pin of the U14 chip is connected with a power supply ground, the 5 th pin of the U14 chip is connected with the 2 nd pin of the R116 resistor in the power supply circuit, the 4 th pin of the U14 chip is connected with the cathode of the D7 light-emitting diode in series with the R81 resistor, and the anode of the U14 chip is connected with a 3.3V power supply; the 3 rd pin of the U16 chip is connected with a power supply ground, the 5 th pin of the U16 chip is connected with the 2 nd pin of the R116 resistor in the power supply circuit, the 4 th pin of the U16 chip is connected with the cathode of the D9 light-emitting diode in series, and the anode of the U16 chip is connected with a 3.3V power supply; the 3 rd pin of the U17 chip is connected with a power supply ground, the 5 th pin of the U17 chip is connected with the 2 nd pin of the R116 resistor in the power supply circuit, the 4 th pin of the U17 chip is connected with the cathode of the D10 light-emitting diode in series with the R87 resistor, and the anode of the U17 chip is connected with a 3.3V power supply; the 3 rd pin of the U6 chip is connected with a power supply ground, the 5 th pin of the U6 chip is connected with a 1.8V power supply under the filtering of a C89 capacitor, the 4 th pin of the U6 chip is connected with an R49 resistor in series to the cathode of the D2 light-emitting diode, and the anode of the U6 chip is connected with a 3.3V power supply; the 3 rd pin of the U8 chip is connected with a power supply ground, the 5 th pin of the U8 chip is connected with a 1.8V power supply under the filtering of a C97 capacitor, the 4 th pin of the U8 chip is connected with an R51 resistor in series to the cathode of the D3 light-emitting diode, and the anode of the U8 chip is connected with a 3.3V power supply; the 3 rd pin of the U9 chip is connected with a power supply ground, the 5 th pin of the U9 chip is connected with a 1.8V power supply under the filtering of a C100 capacitor, the 4 th pin of the U9 chip is connected with a R57 resistor in series to the cathode of the D5 light-emitting diode, and the anode of the U9 chip is connected with a 3.3V power supply; the 15 th pin of the U01 chip in the control circuit is connected with the power supply ground, the 8 th pin of the U01 module in the control circuit is connected with the R045 resistor to the 3.3V power supply in series under the capacitance filtering of C040 and C041, the 1 st pin of the U01 module is connected with the R08 resistor to the 3.3V power supply in series, the 3 rd pin of the U01 module is connected with the R07 resistor to the 3.3V power supply in series, the 18 th pin of the U01 module is connected with the R05 resistor to the 3.3V power supply in series, the 17 th pin of the U01 module is connected with the R06 resistor to the 3.3V power supply in series, the 16 th pin of the U01 module is connected with the R09 resistor to the power supply ground in series, the 4 th pin of the U01 module is connected with the C143 capacitor to the power supply ground in series, the 4 th pin R99 resistor of the U01 module is connected with the 2 nd pin of the R116 in series, the 4 th pin of the U01 module is connected with the R101 resistor to the 1 st and 3 of the SP2 switch, and the 4 th pin of the SP2 switch is connected with the power supply ground; the 5 th pin of the U01 module is connected with a C162 capacitor in series to the power ground, the 4 th pin of the U01 module is connected with a R105 resistor in series to the 2 nd pin of a R116 in the power circuit, the 4 th pin of the U01 module is connected with a R108 resistor in series to the 1 st pin and the 3 rd pin of the SP3 switch, and the 4 th pin and the 2 nd pin of the SP3 switch are connected with the power ground; the 6 th pin of the U01 module is connected with a C165 capacitor to the power ground in series, the 4 th pin of the U01 module is connected with a R111 resistor to the 2 nd pin of a R116 resistor in the power circuit in series, the 4 th pin of the U01 module is connected with a R113 resistor to the 1 st pin and the 3 rd pin of the SP4 switch in series, and the 4 th pin and the 2 nd pin of the SP4 switch are connected with the power ground; the 7 th pin of the U01 module is connected with a C163 capacitor to the power ground in series, the 4 th pin of the U01 module is connected with a R106 resistor to the 2 nd pin of R116 in the power circuit in series, the 4 th pin of the U01 module is connected with a R109 resistor to the 1 st pin and the 3 rd pin of the SP5 switch in series, and the 4 th pin and the 2 nd pin of the SP5 switch are connected with the power ground; the 20 th pin of the U01 module is connected with the C161 capacitor to the power ground in series, the 4 th pin of the U01 module is connected with the R104 resistor to the 2 nd pin of the R116 in the power circuit in series, the 4 th pin of the U01 is connected with the R107 resistor to the 1 st pin and the 3 rd pin of the SP1 switch in series, and the 4 th pin and the 2 nd pin of the SP1 switch are connected with the power ground.
4. The television splice box circuit with the intelligent control system according to claim 3, wherein a 43 rd pin of a U12 chip in the HDMI interface switching circuit is connected to a power ground, a 1 st pin of the U12 chip is connected to a 1 st pin of the C177 capacitor in the power circuit under C129 capacitor filtering, 31, 32, 33, 34, 35, 36, 37, 38 th pins of the U12 chip are sequentially connected to 12 th, 10, 3, 1, 6, 4, 9, 7 th pins of an HDMI1 interface, and 18 th, 19 th, 41, 42 th pins of the U12 chip are sequentially connected to 13 th, 19 th, 16 th, 15 th pins of the HDMI1 interface; the U12 chip is characterized in that pins 22, 23, 24, 25, 26, 27, 28 and 29 of the U12 chip are sequentially connected with pins 12, 10, 3, 1, 6, 4, 9 and 7 of an HDMI2 interface, pins 20, 21, 39 and 40 of the U12 chip are sequentially connected with pins 13, 19, 16 and 15 of the HDMI2 interface, pins 2, 17 and 16 of the U12 chip are sequentially connected with pins 36, 37 and 38 of a U13 chip in the control circuit, pins 10, 11, 7 and 8 of the U12 chip are sequentially connected with pins 6, 1, 3 and 4 of a U10 chip, pins 5, 6, 12 and 13 of the U12 chip are sequentially connected with pins 6, 1, 3 and 4 of the U11 chip, pin 2 of the U12 chip is connected with a power supply place, pin 5 of the U12 chip is connected with a 3.3V power supply, pin 3 of the U12 chip is connected with pin 1 of a D8, pin 4 of the U12 chip is sequentially connected with pins 6, 1 of the U12 chip is connected with pin 2 of the U12 chip, pin 3 of the U12 chip is connected with pins 3, and pin 2 of the U12 chip is connected with pins 1 of the U12 chip.
5. The television splice box circuit with the intelligent control system according to claim 4, wherein pins 26, 27, 28, 29, 31, 32, 33, 34 of the U15 chip in the HDMI interface data processing circuit are sequentially connected with pins 13, 12, 6, 5, 8, 7, 11, 10 of the U12 chip in the HDMI interface switching circuit, pin 16 of the U15 chip is connected with pin 5 of the HDMI interface switching circuit U18 in series with R71 resistor, pin 17 of the U15 chip is connected with pin 6 of the HDMI interface switching circuit U18 in series with R73 resistor, pins 25, 30, 35, 40 of the U15 chip are connected with 3.3V power under C122, C123, C124, C125, C126 capacitor filter, pin 24 of the U15 chip is connected with 3.3V power under C127, C130 capacitor filter, pin 24 of the U15 chip is connected with 1.2V power under C131 capacitor filter, the 23 rd pin of the U15 chip is connected with F8 inductance to 1.2V power supply in series under C135 and C137 capacitance filter, the 37 th pin of the U15 chip is connected with F9 inductance to 1.2V power supply in series under C138 and C140 capacitance filter, the 7 th, 15, 43, 48, 64 and 71 th pins of the U15 chip are connected with 1.2V power supply under C156, C157, C158, C159, C160, C154 and C155 capacitance filter, the R103 resistor is connected in parallel between the 38 th pin and the 39 th pin of the U15 chip, the X3 crystal oscillator is connected in parallel between the 38 th pin and the 39 th pin of the U15 chip, the 38 th pin of the U15 chip is connected with C152 capacitance to power ground in series, the 39 th pin of the U15 chip is connected with C153 capacitance to power ground, the 19 th pin R69 resistance of the U15 chip is connected with the 14 th pin of the U12 chip in series, the 6 th, 50, 55, 63, 70 and 76 th pins of the U15 chip are connected with C113 and C113, the C1.114V power supply capacitor is connected with the C12, the 20 th pin of the U15 chip is connected with a 3.3V power supply under C111 capacitive filtering, the 12 th pin of the U15 chip is connected with the 33 rd pin of the U13 in the control circuit in series with an R78 resistor, the 5 th, 4, 3, 2, 1, 74, 73 and 72 th pins of the U15 chip are sequentially connected with the 1 st, 2, 3, 4, 5, 6, 7 and 8 th pins of RA1 row block, the 69 th, 68, 67, 66, 65, 62, 61 and 60 th pins of the U15 chip are sequentially connected with the 1 st, 2 nd, 3 rd, 4 th, 5, 6 th, 7 th and 8 th pins of RA2 row block, and the 59 th, 58 th, 57, 56, 54, 53, 52 and 51 th pins of the U15 chip are sequentially connected with the 1 st, 2 nd, 3 th, 4 th, 5 th, 6 th, 7 and 8 th pins of RA3 row block.
6. The television splice box circuit with intelligent control system according to claim 5, wherein pins 2 and 3 of the Ua2 chip in the audio processing circuit are connected to a 1.8V power supply under Ca69 and Ca68 capacitive filtering, pin 1 of the Fa3 inductor is connected to pin 1 of the Ua 3 inductor, pin 2 of the Fa3 inductor is connected to pin 17 of the Ua2 chip under Ca14 capacitive filtering, pin 17 of the Ua2 chip is externally connected to Ca66 and Ca15 capacitive to ground filtering, pin 2 of the Fa3 inductor is connected to pin 28 of the Ua2 chip under Ca67 and Ca59 capacitive filtering, pins 33, 16, 18, 20, 25, 29, 1 of the Ua2 chip are connected to power ground, pins 21 and 24 of the Ua2 chip are connected to pin 1 of the J13 interface of the power supply circuit under Ca65, ca63 and Ca64 capacitive filtering, the 9 th pin and the 10 th pin of the Ua2 chip are sequentially connected with the 14 th pin and the 13 th pin of the U15 chip in the HDMI interface data processing circuit, the 19 th pin, the 22 th pin, the 23 th pin and the 26 th pin of the Ua2 chip are sequentially connected with the 4 th pin, the 3 rd pin, the 2 nd pin and the 1 st pin of the Ja5 connector, the 30 th pin of the Ua2 chip is connected with the 3 rd pin of the Ja2 interface in series with a C1 capacitor, the 27 th pin of the Ua2 chip is connected with the 2 nd pin of the Ja2 interface in series with a Ca2 capacitor, the 1 st pin of the Ja2 connector is connected with a power supply ground, the 5 th pin, the 6 th pin, the 7 th pin and the 8 th pin of the Ua2 chip are sequentially connected with the 1 st pin of the R92 resistor, the R93 resistor, the R95 resistor and the R98, and the 2 nd pin of the R92, the R93 resistor are sequentially connected with the 42 th pin, the 45, the 46 pin and the 41 nd pin of the U15 chip in the HDMI interface data processing circuit.
7. The television splice box circuit with intelligent control system according to claim 6, wherein pins C4, D6, D8, D10, E4, E13, F4, G12, H4, H12, J3, J13, K4, K12, L3, M4, M5, M8, M12, G13, C6, C8, F6, F7, F8, F9, F10, G6, G7, G8, G9, G10, H6, H7, H8, H9, H10, J6, J7, J8, J9, J10, K6, K7, K8, K9, K10 of the DPP3435 chip U5G are connected to a power supply ground, the DPP3435 chip U5H has capacitance-to-ground filtering of D3, E3, M10, L13, H13, F13, D9, C5, D7, D12, J4, J12, K3, L4, L12, M6, M9, C3 pin external C61, C62, C63, C64, C65, C66, C67, C68, C69, C70, C71, C72, C75, C7, C9, D4, E12, F12, K13 and M11 pins of the DPP3435 chip U5H are connected with a 1.8V power supply under the capacitive filtering of C77, C78, C79, C80 and C81, the M3, M7, N3 and N7 pins of the DPP3435 chip U5H are connected with an R59 resistor to a 1.8V power supply under the capacitive filtering of C81, C83, C84 and C85, the H2 pin of the DPP3435 chip U5H is connected with a C56 and C57 capacitor to the G3 and H3 pins of the DPP3435 chip U5H in series, the G3 and H3 pins of the DPP3435 chip U5H are connected with a F4 magnetic bead to the power ground, the J2 and H2 pins of the DPP3435 chip U5H are connected with a F3 pin of the DPP3435 chip U5H in series, a R38 resistor is connected between H1 and a J1 pin of the DPP3435 chip U5A in parallel, the H35 chip U35 chip is connected with a G3 and the H3 pin of the DPP3435 chip U5H is connected with a C3 pin of the DPP3435 chip U5H 1 in series, the C35 chip is connected with a C1 pin of the DPP 35 chip U5H 1 is connected with a C1, the pin A13 of the DPP3435 chip is connected with the R37 resistor in series to the 6 th pin of the U4 chip, the pin B13 of the DPP3435 chip U5A is connected with the R39 resistor in series to the 5 th pin of the U4 chip, the pin B12 of the DPP3435 chip U5A is connected with the R34 resistor in series to the 2 nd pin of the U4 chip, the pin A14 of the DPP3435 chip U5A is connected with the R40 resistor in series to the 1 st pin of the U4 chip, the 3 rd, 7 th and 8 th pins of the U4 chip are connected with the D11 pin of the DPP3435 chip U5H, the P2, P3, P1 and N5 pins of the DPP3435 chip U5E are sequentially connected with the 1 st pin of the R68, R74, R70 and R72 resistor, the 2 nd pin of the R68, R74, R70 and R72 resistor are sequentially connected with the 8 th, 75, 10 and 9 th pins of the U15 chip in the HDMI interface data processing circuit, the pins K2, K1, L2, L1, M2, M1, N2 and N1 of the DPP3435 chip U5E are sequentially connected with the pins 16, 15, 14, 13, 12, 11, 10 and 9 of the RA1 resistor in the HDMI interface data processing circuit, the pins R1, R2, R3, P4, R4, P5, R5 and P6 of the DPP3435 chip U5E are sequentially connected with the pins 16, 15, 14, 13, 12, 11, 10 and 9 of the RA2 resistor in the HDMI interface data processing circuit, the pins R6, P7, R7, P8, R8, P9, R9 and P10 of the DPP3435 chip U5E are sequentially connected with the pins 16, 15, 14, 13, 12, 11, 10 and 9 of the RA3 resistor in the HDMI interface data processing circuit, the pin R58 of the DPP3435 chip U5E is connected with the pins R58 of the DPP3435 chip U5E in series, and the pin N13 of the DPP3435 chip U5E is connected with the control circuit.
8. The television splice box circuit with intelligent control system according to claim 7, wherein pins 1 and 2 of the U7 chip in the projection light processing circuit are connected with pin 1 of the J13 interface in the power circuit under the capacitive filtering of C92, C93, C94 and C95, pin 10 of the U7 chip is connected with pin 1 of the J13 interface in the power circuit under the capacitive filtering of C99, pins 5, 12, 20, 23, 45, 46 and 7 of the U7 chip are connected with power ground, pin 7 of the U7 chip is connected with R46 resistor in series with pin C15 of the DPP3435 chip U5C, pin 3 of the U7 chip is connected with R47 resistor in series with pin D14 of the DPP3435 chip U5C, pin 8 of the U7 chip is connected with R48 resistor in series with pin D15 of the DPP3435 chip U5C, L5 inductor is connected in parallel between pins 11 and 15 of the U7 chip, the 11 th pin of the U7 chip is connected with the cathode of the D4 diode, the anode of the U7 chip is connected with a C107 capacitor in series to the power ground, the 15 th pin of the U7 chip is connected with a C105 capacitor to ground filter, the 17 th pin of the U7 chip is connected with a C106 capacitor to ground filter, the 19 th pin of the U7 chip is connected with a C103 capacitor to ground filter, the 18 th pin of the U7 chip is connected with the 1 st pin of the J13 interface of the power circuit under the filtering of C109 and C110 capacitors, the 21 st pin of the U7 chip is connected with a C108 capacitor filter and then is connected with a 1.8V power supply, an L6 inductor is connected in parallel between the 24 th pin and the 29 th pin of the U7 chip, the 29 th pin of the U7 chip is connected with the D3 pin of the U5C of the DPP3435 chip, the 28 th pins 31 and 34 th pins of the U7 chip are sequentially connected with the A12, B15 and B14 pins of the U5D of the DPP3435 chip, the L4 inductance is connected between the 44 th pins 43 and 48 th pins and 47 pins of the U7 chip in parallel, and the L4 inductance is 42 th chip is connected between the U7 chip, 40. Pins 39, 38 and 37 are sequentially connected with pins 1, 2, 3 and 4 of the J7 connector.
9. The television splice box circuit with intelligent control system according to claim 8, wherein pins 1 and 50 of the J8 connector in the projection lens interface circuit are connected to a 1.8V power supply under C55 capacitive filtering, pins 37 and 38 of the J8 connector are connected to a 1.8V power supply under C73 capacitive filtering, pins 2, 7, 12, 15, 20, 21, 22, 23, 25, 49, 48, 44, 39, 36, 31, 30, 26 of the J8 connector are connected to power ground, pins 47, 46, 45 of the J8 connector are sequentially connected to pins 17, 15, 14 of the U7 chip, pins 3 and 4 of the J8 connector are sequentially connected to pins B2 and B1 of the DPP3435 chip U5B, the 6 th pin of the J8 connector is connected with the R31 resistor in series to the A1 pin of the DPP3435 chip U5B, the 5 th pin of the J8 connector is connected with the R32 resistor in series to the A2 pin of the DPP3435 chip U5B, the 8 th, 9, 10, 11, 13, 14, 16, 17, 18, 19, 32, 33, 34, 35, 36, 40, 41, 42 and 43 pins of the J8 connector are sequentially connected with the A3, B3, A4, B4, A7, B7, A10, B10, A11, B9, A9, B8, A8, B6, B5 and A5 pins of the DPP3435 chip U5B, and the 23 rd, 27 and 28 pins of the J8 connector are sequentially connected with the 6 th, 5 and 1 pins of the U4 chip in the display control circuit.
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