CN113629057B - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN113629057B CN113629057B CN202110908060.3A CN202110908060A CN113629057B CN 113629057 B CN113629057 B CN 113629057B CN 202110908060 A CN202110908060 A CN 202110908060A CN 113629057 B CN113629057 B CN 113629057B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 77
- 239000000463 material Substances 0.000 claims description 73
- 150000002500 ions Chemical class 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 7
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 238000003860 storage Methods 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 81
- 238000000034 method Methods 0.000 description 29
- 230000008569 process Effects 0.000 description 23
- 238000004132 cross linking Methods 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 238000006243 chemical reaction Methods 0.000 description 9
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 230000003667 anti-reflective effect Effects 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 239000000969 carrier Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 230000008901 benefit Effects 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
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- 229910052759 nickel Inorganic materials 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
- 229910052721 tungsten Inorganic materials 0.000 description 4
- 239000010937 tungsten Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/488—Word lines
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- Semiconductor Memories (AREA)
Abstract
The embodiment of the invention discloses a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises a substrate, an active column structure, a word line, a gate dielectric layer and a body line, wherein the active column structure is arranged on the substrate; the word line is arranged on the first side of the active column structure and extends along the first direction, and the gate dielectric layer is arranged between the word line and the channel layer of the active column structure; the body line is arranged on the second side of the active column structure, extends along the first direction and is in direct contact with the channel layer; wherein the first side and the second side are oppositely disposed.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a manufacturing method thereof.
Background
Each memory cell of the dynamic random access memory (dynamic random access memory, DRAM) includes a storage capacitor and a transistor by which data writing or reading of the memory cell is controlled. However, the vertical transistor of the memory in the related art has a problem of unstable array threshold voltage, which causes a problem of error capacitance signal, resulting in lower yield.
Disclosure of Invention
The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof, which are used for solving the problem of capacitance signal errors in the related art.
The semiconductor structure of the embodiment of the invention comprises:
a substrate;
an active column structure disposed on the substrate;
a word line arranged on a first side of the active column structure and extending along a first direction;
the gate dielectric layer is arranged between the word line and the channel layer of the active column structure; and
the body line is arranged on the second side of the active column structure, extends along the first direction and is in direct contact with the channel layer;
wherein the first side and the second side are oppositely disposed.
According to some embodiments of the invention, the number of the active pillar structures is plural, and the plural active pillar structures are arranged on the substrate in an array manner;
the number of the word lines and the number of the body lines are multiple, and the word lines and the body lines which are arranged in pairs are respectively arranged on the first side and the second side of each active column structure.
According to some embodiments of the invention, the substrate comprises an array region and a peripheral region, the active pillar structure being disposed on the array region;
adjacent two of the body lines are connected at portions of the peripheral region.
According to some embodiments of the invention, the word line and the body line each include a bottom surface facing the substrate, a first side surface facing the active pillar structure and connected to the bottom surface, and a second side surface connected to the bottom surface and the first side surface;
wherein the second side surface is a curved surface.
According to some embodiments of the invention, the second side is an outer arc surface.
According to some embodiments of the invention, the semiconductor structure further comprises a bit line disposed on the substrate and below the word line and the body line;
the bit line extends along a second direction and is contacted with the drain electrode layer of the active column structure;
the first direction and the second direction are perpendicular to each other.
According to some embodiments of the invention, the bit lines are plural in number, and the bit lines arranged in pairs are respectively arranged on two opposite sides of the active pillar structure.
According to some embodiments of the invention, bit line trenches are respectively arranged on two opposite sides of the drain electrode layer, and part of the bit lines are arranged in the bit line trenches.
According to some embodiments of the invention, the drain layer and the source layer of the active pillar structure are a first doping type layer, and the channel layer of the active pillar structure is a second doping type layer.
The manufacturing method of the semiconductor structure provided by the embodiment of the invention comprises the following steps:
forming a substrate, wherein an active column structure extending along a direction perpendicular to the substrate is formed on the substrate, and comprises a source electrode layer, a channel layer and a drain electrode layer;
forming a gate dielectric layer and a word line on a first side of the channel layer, wherein the gate dielectric layer is arranged between the word line and the channel layer;
forming a body line on a second side of the channel layer, the body line in direct contact with the channel layer;
the word lines and the body lines extend along a first direction, and the first side and the second side are opposite.
According to some embodiments of the present invention, a gate dielectric layer and a word line are formed on a first side of the channel layer, the gate dielectric layer being disposed between the word line and the channel layer, and a body line is formed on a second side of the channel layer, the body line being in direct contact with the channel layer, comprising:
forming a gate dielectric layer on the side wall of the channel layer;
removing the gate dielectric layer on the second side of the channel layer;
depositing a word line material layer, the word line material layer filling gaps between adjacent active pillar structures;
and etching the word line material layer to form the word line and the body line.
According to some embodiments of the invention, forming a substrate comprises:
providing an initial substrate;
and etching part of the initial substrate along the thickness direction of the initial substrate to form the active column structure, wherein the initial substrate which is not etched is the substrate.
According to some embodiments of the invention, forming the substrate further comprises:
and doping second type ions into the substrate between the adjacent active column structures to form a well region.
According to some embodiments of the invention, the method further comprises:
bit lines are respectively formed on two opposite sides of the active column structure, are arranged below the word lines and the body lines, extend along a second direction, and are perpendicular to the first direction;
forming bit lines on opposite sides of the active pillar structure, respectively, comprising:
etching two opposite side walls of the active column structure to form bit line trenches respectively located on the two opposite side walls of the drain electrode layer;
and forming bit lines, wherein the bit lines respectively cover the bit line grooves of the drain electrode layer.
According to some embodiments of the invention, the method further comprises:
and carrying out ion implantation on the top of the active column structure, and forming a source electrode layer of the active column structure by the doped top of the active column structure.
According to some embodiments of the invention, the method further comprises:
and forming a storage structure electrically connected with the source electrode layer above the active column structure.
One embodiment of the above invention has at least the following advantages or benefits:
in one aspect, a bottom surface of the active pillar structure serving as an active region of the vertical transistor can be directly in contact connection with the substrate to form a carrier channel; on the other hand, the body line serves as a channel between the active pillar structure and the substrate, and can also introduce excess inversion carriers induced in the vertical transistor channel layer region into the substrate. The two aspects cooperate to effectively solve the problem of unstable threshold voltage of the vertical transistor caused by existence of redundant carriers, and reduce or even avoid the floating body effect of the semiconductor structure.
Drawings
The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
Fig. 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.
Fig. 2 shows a schematic cross-section along X-X in fig. 1.
Fig. 3 to 24 are schematic perspective views of different process stages of a method for manufacturing a semiconductor structure according to an embodiment of the invention.
Wherein reference numerals are as follows:
100. substrate 100a, initial substrate
110. Active pillar structure 1101, first sidewall
1102. Second sidewall 110b, top
111. Drain layer 112, channel layer
1123. Bit line trench 113, source layer
120a, word line 120b, body line
121. Bottom surface 122, first side surface
123. Second side 131, bit line
210. First photoresist layer 211, first opening
220. Second photoresist layer 221, second opening
230. Third photoresist layer 231, third opening
240. Fourth photoresist layer
241. Fourth opening 250, fifth photoresist layer
310. First sacrificial layer 320, second sacrificial layer
410. First dielectric layer 411, remaining first dielectric layer
420. Second dielectric layer 421, remaining second dielectric layer
430. Third dielectric layer 440, fourth dielectric layer
520. Trench 600, word line material layer
601. Bit line material layer 700, memory structure
D1, a first direction D2, a second direction
D3, third direction
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted.
As shown in fig. 1 and 2, fig. 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention. The semiconductor structure of the embodiment of the invention comprises: the active column structure 110 is arranged on the substrate 100 and comprises a source electrode layer 113, a channel layer 112 and a drain electrode layer 111; the word line 120a is disposed on a first side of the active pillar structure 110 and extends along a first direction D1; the gate dielectric layer is disposed between the word line 120a and the channel layer 112 of the active pillar structure 110; the body line 120b is disposed on the second side of the active pillar structure 110 and extends along the first direction D1, and the body line 120b is in direct contact with the channel layer 112; wherein the first side and the second side are oppositely disposed.
The active pillar structures 110 extend in a third direction D3 in fig. 1. The active pillar structure 110 includes a source layer 113, a drain layer 111, and a channel layer 112. In this embodiment, by adjusting the position of the word line 120a and adding the body line 120b connecting the active pillar structure 110 and the substrate 100, so that the word line 120a and the body line 120b are distributed on opposite sides of the active pillar structure 110, on one hand, the bottom surface of the active pillar structure 110, which is the vertical transistor active region, can be directly in contact connection with the substrate 100, forming a carrier channel; on the other hand, the body line 120b can also introduce the excess inversion carriers induced in the vertical transistor channel layer region into the substrate 100 as a channel between the active pillar structure 110 and the substrate 100. The two aspects cooperate to effectively solve the problem of unstable threshold voltage of the vertical transistor caused by existence of redundant carriers, and reduce or even avoid the floating body effect of the semiconductor structure.
The material of the active pillar structures 110 may be, but not limited to, silicon, and the material of the substrate 100 may also be, but not limited to, silicon.
In the present embodiment, the number of the active pillar structures 110 is plural, and the plurality of active pillar structures 110 are disposed on the substrate 100 in an array manner. The number of word lines 120a and body lines 120b is plural, and the word lines 120a and body lines 120b arranged in pairs are respectively arranged on opposite sides of the channel layer 112 of each active pillar structure 110.
In one embodiment, the word line 120a and the body line 120b are disposed in the same layer and are the same material.
Specifically, the word line 120a and the body line 120b are arranged in the same layer and made of the same material, so that the word line 120a and the body line 120b can be formed simultaneously, the steps for forming the semiconductor structure are simplified, and the manufacturing cost of the semiconductor structure is reduced. The material of the word line 120a and the body line 120b122 may be conductive materials, such as copper, aluminum, tungsten, nickel, or polysilicon.
In one embodiment, the substrate 100 includes an array region and a peripheral region, and the active pillar structures 110 are disposed on the array region. Adjacent two body lines 120b are connected at portions of the peripheral region. Compared with the design scheme of the single-sided word line 120a in the related art, the body lines 120b arranged in pairs are connected at the peripheral region, so that the connected transistors can be opened by both the body lines 120b, the problem that the transistors cannot be opened due to the disconnection of the single-sided word line is avoided, and the yield is improved.
Optionally, the word line 120a and the body line 120b each include a bottom surface 121 facing the substrate 100, a first side surface 122 facing the active pillar structure 110 and connected to the bottom surface 121, and a second side surface 123 connected to the bottom surface 121 and the first side surface 122; wherein the second side 123 is curved. By designing the second sides 123 of the word lines 120a and the body lines 120b to be curved, the word lines 120a and the body lines 120b are less prone to leakage.
Preferably, the second side 123 is an outer arc surface.
In one embodiment, the semiconductor structure further includes a bit line 131, wherein the bit line 131 is disposed on the substrate 100 and is located below the word line 120a and the body line 120 b; the bit line 131 extends in the second direction D2 and contacts the drain layer 111; the first direction D1 and the second direction D2 are perpendicular to each other.
The material of the bit line 131 may be a conductive material such as copper, aluminum, tungsten, nickel, or polysilicon.
Alternatively, the number of the bit lines 131 is plural, each bit line 131 extends along the second direction D2, and the bit lines 131 disposed in pairs are disposed on opposite sides of the active pillar structure 110.
Optionally, the semiconductor structure further comprises a memory structure 700, the memory structure 700 being formed above the active pillar structures 110.
Alternatively, the memory structure 700 may be a magnetic tunnel junction structure, a capacitive memory structure, a resistive memory structure, a phase change memory structure, or a ferroelectric memory structure.
As shown in fig. 2, fig. 2 is a schematic cross-sectional view taken along line X-X in fig. 1. The active pillar structure 110 includes a source layer 113, a channel layer 112, and a drain layer 111. The drain layer 111 is provided on the surface of the substrate 100, the channel layer 112 is provided above the drain layer 111, and the source layer 113 is provided above the channel layer 112. Bit lines 131 arranged in pairs are respectively arranged at two opposite sides of the drain layer 111.
Alternatively, bit line trenches 1123 are respectively formed on opposite sides of the drain layer 111, and a portion of the bit lines 131 are disposed in the bit line trenches 1123.
In the present embodiment, by disposing the bit lines 131 disposed in pairs in the bit line trenches 1123, respectively, the contact area of the bit lines 131 can be increased and the contact resistance value can be reduced. In addition, the bit lines 131 arranged in pairs are disposed on opposite sides of the active pillar structure 110, so as to avoid the limitation of the minimum line width of the mask or the machine.
Optionally, the drain layer 111 and the source layer 113 are first doping type layers, and the channel layer 112 is a second doping type layer.
Specifically, the drain layer 111 and the source layer 113 may be N-type doped, and the channel layer 112 may be P-type doped.
In another aspect of the present invention, a method of fabricating a semiconductor structure is also provided. As shown in fig. 3 to 24, fig. 3 to 24 are schematic perspective views illustrating different process stages of a method for manufacturing a semiconductor structure according to an embodiment of the present invention.
The manufacturing method of the semiconductor structure provided by the embodiment of the invention comprises the following steps: forming a substrate, wherein an active column structure extending along a direction perpendicular to the substrate is formed on the substrate, and the active column structure comprises a source electrode layer, a channel layer and a drain electrode layer; forming a gate dielectric layer and a word line on a first side of the channel layer, wherein the gate dielectric layer is arranged between the word line and the channel layer; forming a body line on a second side of the channel layer, the body line in direct contact with the channel layer; the word lines and the body lines extend along a first direction, and the first side and the second side are opposite.
Specifically, as shown in fig. 3, an initial substrate 100a is provided, and a first photoresist layer 210 is formed on a surface of the initial substrate 100a, the first photoresist layer 210 having a first opening 211.
It is understood that the substrate 100 may be a single crystal silicon substrate, a single crystal germanium substrate, a germanium silicon substrate, or the like. The substrate 100 may also be N-type or P-type doped. In this embodiment, the substrate 100 is a P-type doped monocrystalline silicon substrate.
As an example, the material of the first photoresist layer 210 is an anti-reflective material with a positive photoresist or a positive photoresist, and the exposure treatment is performed on the area of the first photoresist layer 210 except the area where the first opening 211 is to be formed, so that the material of the first photoresist layer 210 in the exposed area undergoes degradation reaction, while the material of the first photoresist layer 210 in the unexposed area remains unchanged; the first photoresist layer 210 after the exposure process is subjected to a developing process, a material having a degradation reaction is dissolved in a developing solution, and a material having no degradation reaction is not dissolved in the developing solution, thereby forming the first photoresist layer 210 having the first opening 211.
As another embodiment, the material of the first photoresist layer 210 is an anti-reflective material or a negative photoresist having a negative photoresist characteristic, so that the area of the first photoresist layer 210 corresponding to the area where the first opening 211 is to be formed is exposed, such that the material of the first photoresist layer 210 in the exposed area undergoes a cross-linking reaction (cross-linking), while the material of the first photoresist layer 210 in the unexposed area remains unchanged; the first photoresist layer 210 after the exposure process is subjected to a developing process, the material undergoing a cross-linking reaction is insoluble in a developing solution, and the material not undergoing a cross-linking reaction is soluble in a developing solution, thereby forming the first photoresist layer 210 having the first opening 211.
As shown in fig. 4, along the thickness direction (the third direction D3) of the initial substrate 100a, a portion of the initial substrate 100a is etched with the first photoresist layer 210 as a mask, an active pillar structure 110 is formed, and the initial substrate that is not etched is the substrate 100.
The active pillar structures 110 may extend along a third direction D3, wherein the first direction D1, the second direction D2, and the third direction D3 are perpendicular to each other. It should be appreciated that the number of active pillar structures 110 should be dependent upon design requirements.
As shown in fig. 5, a first sacrificial layer 310 is deposited, the first sacrificial layer 310 covering the sidewalls of the active pillar structures 110 and the surface of the substrate 100. Of course, the first sacrificial layer 310 may also cover the top surface of the active pillar structure 110, and the first photoresist layer 210 is formed on the upper surface of the first sacrificial layer 310.
In an embodiment, the material of the first sacrificial layer 310 may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or the like.
In this embodiment, the material of the first sacrificial layer 310 is silicon oxide.
After the first sacrificial layer 310 is deposited, the second type ions are doped into the substrate between adjacent active pillar structures 110, forming a well region.
It should be noted that, during the doping process, since the first photoresist layer 210 covers the top surface of each active pillar structure 110, the doping ions do not enter into the active pillar structures 110. In addition, the presence of the first sacrificial layer 310 may protect the substrate 100 from damage during doping.
As shown in fig. 6, after P-type doping, the first sacrificial layer 310 and the first photoresist layer 210 are removed.
As shown in fig. 7, a first dielectric layer 410 is deposited, the first dielectric layer 410 fills the gaps between adjacent active pillar structures 110, followed by a mechanical planarization process.
In an embodiment, the material of the first dielectric layer 410 may be an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc.
As shown in fig. 8, a second photoresist layer 220 is formed on the top surface of the active pillar structures 110 and the surface of the first dielectric layer 410, the second photoresist layer 220 having a second opening 221. The second opening 221 separates the second photoresist layer 220 into a plurality of stripe-shaped structures, and the plurality of stripe-shaped structures respectively cover the top surfaces of the plurality of columns of active pillar structures 110 and the top surfaces of the first dielectric layer 410 between two adjacent active pillar structures 110 in the plurality of active pillar structures 110.
As an example, the material of the second photoresist layer 220 is an anti-reflective material with a positive photoresist or a positive photoresist, and the exposure treatment is performed on the area of the second photoresist layer 220 except for the area where the second opening 221 is to be formed, so that the material of the second photoresist layer 220 in the exposed area undergoes degradation reaction, while the material of the second photoresist layer 220 in the unexposed area remains unchanged; the second photoresist layer 220 after the exposure process is subjected to a developing process, the material having undergone degradation reaction is dissolved in a developing solution, and the material having not undergone degradation reaction is not dissolved in the developing solution, thereby forming the second photoresist layer 220 having the second opening 221.
As another embodiment, the material of the second photoresist layer 220 is an anti-reflective material or a negative photoresist having a negative photoresist characteristic, so that the area of the second photoresist layer 220 corresponding to the area where the second opening 221 is to be formed is exposed to light, so that the material of the second photoresist layer 220 in the exposed area undergoes a cross-linking reaction (cross-linking), while the material of the second photoresist layer 220 in the unexposed area remains unchanged; the second photoresist layer 220 after the exposure process is subjected to a developing process, the material undergoing a cross-linking reaction is insoluble in a developing solution, and the material not undergoing a cross-linking reaction is soluble in a developing solution, thereby forming the second photoresist layer 220 having the second opening 221.
After forming the second photoresist layer 220 with the second opening 221, a portion of the first dielectric layer 410 is etched along the third direction D3 with the second photoresist layer 220 as a mask, and the remaining first dielectric layer 411 covers the bottom of the trench formed by etching to provide insulation between the bit line 131 and the substrate 100 formed subsequently.
As shown in fig. 9, bit line trenches 1123 are formed in opposite sidewalls of the active pillar structure 110, i.e., the first sidewall 1101 and the second sidewall 1102, respectively. The bit line trench 1123 is configured to receive a portion of the bit line 131.
As shown in fig. 10, the second photoresist layer 220 is removed.
As shown in fig. 11, a second sacrificial layer 320 is deposited, the second sacrificial layer 320 covering the inner walls of the bit line trenches 1123.
A third photoresist layer 230 is formed on the top surface of the active pillar structure 110 and the surface of the second sacrificial layer 320, the third photoresist layer 230 having a third opening 231. The second sacrificial layer 320 may further cover the top surface of the active pillar structure 110, and a third photoresist layer 230 is formed on the top surface of the second sacrificial layer 320.
The third opening 231 separates the third photoresist layer 230 into a plurality of stripe-shaped structures, and the plurality of stripe-shaped structures respectively cover the top surfaces of the plurality of columns of active pillar structures 110 and the top surfaces of the first dielectric layer 410 between two adjacent active pillar structures 110 in the plurality of columns of active pillar structures 110.
As an example, the material of the third photoresist layer 230 is an anti-reflective material with a positive photoresist or a positive photoresist, and the area of the third photoresist layer 230 except for the area where the third opening 231 is to be formed is exposed, so that the material of the third photoresist layer 230 in the exposed area undergoes degradation reaction, while the material of the third photoresist layer 230 in the unexposed area remains unchanged; the third photoresist layer 230 after the exposure process is subjected to a developing process, the material having undergone degradation reaction is dissolved in a developing solution, and the material having not undergone degradation reaction is not dissolved in the developing solution, thereby forming the third photoresist layer 230 having the third opening 231.
As another embodiment, the material of the third photoresist layer 230 is an anti-reflective material or a negative photoresist having a negative photoresist characteristic, so that the region of the third photoresist layer 230 corresponding to the region where the third opening 231 is to be formed is exposed to light, so that the material of the third photoresist layer 230 in the exposed region undergoes a cross-linking reaction (cross-linking), while the material of the third photoresist layer 230 in the unexposed region remains unchanged; the third photoresist layer 230 after the exposure process is subjected to a developing process, the material undergoing a cross-linking reaction is insoluble in a developing solution, and the material not undergoing a cross-linking reaction is soluble in a developing solution, thereby forming the third photoresist layer 230 having the third opening 231.
In an embodiment, the material of the second sacrificial layer 320 may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, or the like.
In this embodiment, the material of the second sacrificial layer 320 is silicon oxide.
As shown in fig. 12 and 13, the bottom of the active pillar structure 110 is doped with a first type of ion and the top of the active pillar structure 110 is doped with a second type of ion. Wherein the first type of ions is of a different conductivity type than the second type of ions.
Alternatively, the first type of ion doping may be an N-type doping and the second type of ion doping may be a P-type doping.
As an example, the N-type doping, the P-type doping may be by an ion implantation or diffusion process.
As shown in connection with fig. 2, drain layer 111 includes a bottom region of doped active pillar structure 110 and channel layer 112 includes a top region of doped active pillar structure 110.
It should be noted that the second sacrificial layer 320 may serve to protect the active pillar structure 110 from being damaged during the doping process.
In addition, the bit line trenches 1123 are provided on opposite sides of the drain layer 111.
As shown in fig. 14, the third photoresist layer 230 and the second sacrificial layer 320 are removed and a bit line material layer 601 is deposited. The bit line material layer 601 covers the inner walls of the bit line trench 1123.
In one embodiment, the material of the bit line material layer 601 may be a metal material, such as aluminum, tungsten, copper, nickel, silver, polysilicon, and other conductive materials.
As shown in fig. 15, the deposition of the bit line material layer 601 is followed by a mechanical planarization process. A fourth photoresist layer 240 is formed on the surface of the bit line material layer 601 and the top surface of the active pillar structures 110, the fourth photoresist layer 240 having a fourth opening 241. The bit line material layer 601 is etched using the fourth photoresist layer 240 as a mask until the surface of the first dielectric layer 411 remains. Finally, bit lines 131 buried in the bit line trenches 1123 and covering the sidewalls of the active pillar structures 110 are formed.
As shown in fig. 2, the paired bit lines 131 cover the bit line trenches 1123 on both sides of the drain layer 111, respectively.
In the present embodiment, by disposing the bit lines 131 disposed in pairs in the bit line trenches 1123 of the first and second sidewalls of the active pillar structures 110, respectively, the contact area of the bit lines 131 can be increased and the contact resistance value can be reduced. In addition, the bit lines 131 arranged in pairs are disposed on opposite sides of the active pillar structure 110, so as to avoid the limitation of the minimum line width of the mask or the device.
As shown in fig. 16, the fourth photoresist layer 240 is removed and a second dielectric layer 420 is deposited, followed by a mechanical planarization process.
As shown in fig. 17, after performing the mechanical planarization process, a portion of the second dielectric layer 420 is etched, and the remaining second dielectric layer 421 covers a portion of the sidewalls of the active pillar structures 110 to expose the top portions 110b of the active pillar structures 110.
As shown in fig. 18, the top portion 110b is P-doped, for example, by an ion implantation or diffusion process.
It should be noted that, although not shown in the drawings, a sacrificial layer may be deposited on the top surface and the side surfaces of the top portion 110b of the active pillar structure 110 before the P-type doping is performed on the top portion 110b. In this way, the sacrificial layer may protect the top 110b from damage during the P-type doping. After the P-type doping is completed, the sacrificial layer is removed.
A gate dielectric layer is formed on the top and side surfaces of the top 110b of the active pillar structures 110 and the surface of the remaining second dielectric layer 421. The gate dielectric layer may be formed, for example, by an Atomic Layer Deposition (ALD) process, so that the thickness of the gate dielectric layer may be precisely controlled.
It is understood that the gate dielectric layer is formed to cover the sidewalls of the channel layer 112.
Then, the gate dielectric layer on the surface of the remaining second dielectric layer 421 and the top gate dielectric layer on the top 110b are removed, and the gate dielectric layer on the side of the top 110b is left. At the same time, the gate dielectric layer on the top 110 side is removed to expose one side of the channel layer 112. The channel layer 112 is exposed for direct contact with a body line formed later.
As shown in fig. 19, the top 110b is P-doped, and after forming a gate dielectric layer on one side of the channel layer 112, a third dielectric layer 430 is deposited, and the third dielectric layer 430 fills the gaps between adjacent active pillar structures 110. A mechanical planarization process is performed and a fifth photoresist layer 250 is formed on the surface of the third dielectric layer 430 and the top surface of the active pillar structures 110.
In one embodiment, the material of the third dielectric layer 430 may be an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc
In this embodiment, the third dielectric layer 430 and the second dielectric layer 420 are the same material.
The fifth photoresist layer 250 has an opening corresponding to the word line trench. The opening may be elongated, and an extending direction thereof may be perpendicular to an extending direction (the second direction D2) of the bit line 131.
In an embodiment, the fifth photoresist layer 250 has an anti-reflective material with negative/positive photoresist characteristics or a negative photoresist, and the specific exposure/development process may be performed in the manner of the first to fourth photoresist layers, which will not be described herein.
As shown in fig. 20, the third dielectric layer 430 is etched using the fifth photoresist layer 250 as a mask to form a trench 520 and expose the gate dielectric layer.
Optionally, the depth of the trench 520 is such as to reveal the top 110b of the active pillar structure 110.
As shown in fig. 21, a word line material layer 600 is deposited, the word line material layer 600 filling the gaps between adjacent active pillar structures 110. The word line material layer 600 covers the gate dielectric layer located on the channel layer 112 side and the exposed channel layer 112.
In one embodiment, the material of the word line material layer 600 may be a metal material, such as aluminum, tungsten, copper, nickel, silver, polysilicon, or the like.
As shown in fig. 22, the word line material layer 600 is etched to form the word lines 120a and the body lines 120b. The word line 120a and the body line 120b are located above the bit line 131, and each extend along the first direction D1. The word line 120a and the body line 120b are respectively located at two opposite sides of the active pillar structure 110, the gate dielectric layer is disposed between the word line 120a and the channel layer 112, and the body line 120b is in direct contact with the channel layer 112. Compared with the design of the word line surrounding active column structure in the related art, the arrangement mode of the word line and the body line in the embodiment of the invention can avoid floating body effect (floating body) caused by the arrangement position of the word line, thereby solving the problem that the capacitance signal is influenced due to unstable critical voltage and improving the yield of products.
It should be noted that, the floating body effect causes that the substrate of the transistor element cannot be connected to the wafer substrate, so that the point location of the transistor element is not necessarily equal to VBB, and further causes the problem of unstable threshold voltage of the element.
As shown in fig. 23, the top 110b of the active pillar structure 110 is ion-implanted, and after the ion implantation is performed on the top 110b of the active pillar structure 110, a source layer is formed from the doped top of the active pillar structure.
Specifically, the top 110b of the active pillar structure 110 is N-doped to form the source layer 113. As described above, the active pillar structures 110 respectively form N-doped regions and P-doped regions. The top 110b of the active pillar structure 110 is N-doped, and the doped top of the active pillar structure forms a source layer.
To this end, a drain layer 111, a channel layer 112, and a source layer 113 are sequentially formed in the active pillar structure 110. The drain layer 111 and the source layer 113 are first doped layers, and the channel layer 112 is a second doped layer. The first doping type layer may be N-type doped, and the second doping type layer may be P-type doped.
As shown in fig. 24, the method of the embodiment of the present invention further includes:
a memory structure 700 is formed over the active pillar structures 110. The memory structure 700 is electrically connected to the source layer.
Alternatively, the memory structure 700 may be a magnetic tunnel junction structure, a capacitive memory structure, a resistive memory structure, a phase change memory structure, or a ferroelectric memory structure.
In summary, the semiconductor structure and the manufacturing method thereof according to the embodiments of the present invention have at least the following advantages and beneficial effects:
the word lines 120a and the body lines 120b are distributed on opposite sides of the active pillar structures 110, on one hand, so that the bottom surfaces of the active pillar structures 110, which are the vertical transistor active regions, can be directly in contact connection with the substrate 100 to form carrier channels; on the other hand, the body line 120b can also introduce the excess inversion carriers induced in the vertical transistor channel layer region into the substrate 100 as a channel between the active pillar structure 110 and the substrate 100. The two aspects cooperate to effectively solve the problem of unstable threshold voltage of the vertical transistor caused by existence of redundant carriers, and reduce or even avoid the floating body effect of the semiconductor structure.
In the inventive embodiments, the terms "first," "second," "third," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; the term "plurality" means two or more, unless expressly defined otherwise. The terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; "coupled" may be directly coupled or indirectly coupled through intermediaries. The specific meaning of the above terms in the embodiments of the invention will be understood by those skilled in the art according to the specific circumstances.
In the description of the embodiments of the invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "left", "right", "front", "rear", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience in describing the embodiments of the invention and to simplify the description, and do not indicate or imply that the devices or units referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the embodiments of the invention.
In the description of the present specification, the terms "one embodiment," "some embodiments," "particular embodiments," and the like, mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of an embodiment of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above is only a preferred embodiment of the invention and is not intended to limit the embodiment of the invention, and various modifications and variations can be made to the embodiment of the invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.
Claims (14)
1. A semiconductor structure, comprising:
a substrate;
an active column structure disposed on the substrate;
a word line arranged on a first side of the active column structure and extending along a first direction;
the gate dielectric layer is arranged between the word line and the channel layer of the active column structure; and
the body line is arranged on the second side of the active column structure, extends along the first direction and is in direct contact with the channel layer;
wherein the first side and the second side are oppositely disposed; the word line and the body line each include a bottom surface facing the substrate, a first side surface facing the active pillar structure and connected to the bottom surface, and a second side surface connected to the bottom surface and the first side surface; the second side surface is a curved surface.
2. The semiconductor structure of claim 1, wherein the number of active pillar structures is a plurality, and the plurality of active pillar structures are disposed in an array on the substrate;
the number of the word lines and the number of the body lines are multiple, and the word lines and the body lines which are arranged in pairs are respectively arranged on the first side and the second side of each active column structure.
3. The semiconductor structure of claim 2, wherein the substrate comprises an array region and a peripheral region, the active pillar structure being disposed on the array region;
adjacent two of the body lines are connected at portions of the peripheral region.
4. The semiconductor structure of claim 1, wherein the second side is an outer arc surface.
5. The semiconductor structure of claim 1, further comprising a bit line disposed on the substrate and below the word line and the body line;
the bit line extends along a second direction and is contacted with the drain electrode layer of the active column structure;
the first direction and the second direction are perpendicular to each other.
6. The semiconductor structure of claim 5, wherein the number of bit lines is plural, and the bit lines arranged in pairs are respectively disposed on opposite sides of the active pillar structure.
7. The semiconductor structure of claim 6, wherein bit line trenches are respectively provided on opposite sides of the drain layer, and a portion of the bit lines are disposed in the bit line trenches.
8. The semiconductor structure of claim 1, wherein the drain and source layers of the active pillar structure are first doped layers and the active pillar structure channel layer is a second doped layer.
9. A method of fabricating a semiconductor structure, comprising:
forming a substrate, wherein an active column structure extending along a direction perpendicular to the substrate is formed on the substrate, and comprises a source electrode layer, a channel layer and a drain electrode layer;
forming a gate dielectric layer and a word line on a first side of the channel layer, wherein the gate dielectric layer is arranged between the word line and the channel layer;
forming a body line on a second side of the channel layer, the body line in direct contact with the channel layer;
wherein the word line and the body line both extend along a first direction, the first side and the second side being oppositely disposed;
etching two opposite side walls of the active column structure to form bit line trenches respectively located on the two opposite side walls of the drain electrode layer;
forming bit lines, wherein the bit lines respectively cover the bit line grooves of the drain electrode layer; the bit line is arranged below the word line and the body line and extends along a second direction, and the second direction and the first direction are perpendicular to each other.
10. The method of manufacturing a semiconductor structure of claim 9, wherein forming a gate dielectric layer and a word line on a first side of the channel layer, the gate dielectric layer being disposed between the word line and the channel layer, forming a body line on a second side of the channel layer, the body line being in direct contact with the channel layer, comprises:
forming a gate dielectric layer on the side wall of the channel layer;
removing the gate dielectric layer on the second side of the channel layer;
depositing a word line material layer, the word line material layer filling gaps between adjacent active pillar structures;
and etching the word line material layer to form the word line and the body line.
11. The method of manufacturing a semiconductor structure of claim 9, wherein forming a substrate comprises:
providing an initial substrate;
and etching part of the initial substrate along the thickness direction of the initial substrate to form the active column structure, wherein the initial substrate which is not etched is the substrate.
12. The method of manufacturing a semiconductor structure of claim 11, wherein forming a substrate further comprises:
and doping second type ions into the substrate between the adjacent active column structures to form a well region.
13. The method of manufacturing a semiconductor structure of claim 9, further comprising:
and carrying out ion implantation on the top of the active column structure, and forming a source electrode layer of the active column structure by the doped top of the active column structure.
14. The method of manufacturing a semiconductor structure of claim 13, further comprising:
and forming a storage structure electrically connected with the source electrode layer above the active column structure.
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| KR101820022B1 (en) * | 2010-11-11 | 2018-01-19 | 삼성전자주식회사 | Semiconductor devices having vertical channel transistors and methods for fabricating the same |
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| TW201007888A (en) * | 2008-08-15 | 2010-02-16 | Nanya Technology Corp | Vertical transistor and array of vertical transistor |
| CN102446920A (en) * | 2010-10-08 | 2012-05-09 | 三星电子株式会社 | Semiconductor device with vertical channel transistor and method of fabricating the same |
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