CN113628586B - Grid driving unit, grid driving circuit, display device and driving method - Google Patents

Grid driving unit, grid driving circuit, display device and driving method Download PDF

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Publication number
CN113628586B
CN113628586B CN202111113162.2A CN202111113162A CN113628586B CN 113628586 B CN113628586 B CN 113628586B CN 202111113162 A CN202111113162 A CN 202111113162A CN 113628586 B CN113628586 B CN 113628586B
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output
signal
pull
resistor
terminal
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CN113628586A (en
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吴旺娣
陈凯
李方庆
韩飞
陈沫
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BOE Technology Group Co Ltd
Hefei BOE Display Lighting Co Ltd
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BOE Technology Group Co Ltd
Hefei BOE Display Lighting Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention discloses a gate driving unit, a gate driving circuit, a display device and a driving method, wherein the gate driving unit of one embodiment comprises: the first grid driving circuit comprises an output switch, the first grid driving circuit is connected with a signal input end, a clock signal end and a front end output end, and the output switch is connected with the front end output end and the clock signal end; the second circuit comprises a first resistor and a second resistor, wherein one end of the first resistor is connected with the front end output end, the other end of the first resistor is connected with the output end, one end of the second resistor is connected with the output end, and the other end of the second resistor is connected with the first signal line. The embodiment provided by the invention can effectively reduce the problem of uneven display caused by different output voltages among different rows due to the process fluctuation of the thin film transistor, and has practical application value.

Description

Grid driving unit, grid driving circuit, display device and driving method
Technical Field
The present invention relates to the field of display technologies, and in particular, to a gate driving unit, a gate driving circuit, a display device, and a gate driving method.
Background
A Gate On Array (GOA) is a technology for integrating Gate driving circuits On a TFT substrate, where each Gate driving unit is used as a shift register to sequentially transmit scanning signals to the next Gate driving unit, and the TFT switches of the TFTs are turned On line by line to complete data signal input of each pixel unit of the display device. With the rapid development of flat panel display technology, the demand for the picture quality of the display device is higher and higher.
Disclosure of Invention
In order to solve at least one of the above problems, the present invention provides a gate driving unit including:
the first grid driving circuit is connected with a signal input end, a clock signal end and a front end output end and comprises an output switch, and the output switch is connected with the front end output end and the clock signal end;
the second circuit is connected front end output and output, including first resistance and second resistance, wherein, the one end of first resistance with the front end output is connected, the other end and the output of first resistance are connected, the one end of second resistance with the output is connected, the other end and the first signal line connection of second resistance, the second resistance with output switch has the same ripple characteristic.
For example, in some embodiments of the gate driving unit provided in the present application, the output switch and the second resistor are both thin film transistors, and the second resistor includes a control terminal, a first terminal and a second terminal, where the control terminal is connected to a second signal line, the first terminal is connected to the output terminal, and the second terminal is connected to the first signal line.
For example, in some embodiments of the gate driving unit provided in the present application, the second resistor and the output switch are formed simultaneously by using the same material and the same process step.
For example, in the gate driving unit provided in some embodiments of the present application, the active layer of the second resistor is a-Si, and the gate insulating layer of the second resistor is G-SiNX.
For example, in the gate driving unit provided in some embodiments of the present application, a fluctuation of the resistance value of the second resistor follows a fluctuation of the output switch, and the resistance value of the first resistor is within a variation range of the resistance value of the second resistor;
the resistance value of the first resistor is larger than or equal to 1k omega and smaller than or equal to 3k omega.
For example, in some embodiments of the present application, there is provided a gate driving unit, wherein the first gate driving circuit includes:
an input circuit connected to a signal input and a pull-up node, configured to pass a received input signal to the pull-up node when the input signal at the signal input is at an active input level;
a reset circuit connected to the reset signal terminal, the first power voltage terminal and the pull-up node, and configured to pull down the pull-up signal at the pull-up node to the power voltage of the first power voltage terminal when the reset signal of the reset signal terminal is at an active control level;
the pull-down control circuit is connected with the second power supply voltage end, the third power supply voltage end, the pull-up node, the pull-down node and the first power supply voltage end and is configured to control whether the pull-down circuit operates or not;
a pull-down circuit connected to a pull-down node, a pull-up node, a first supply voltage terminal, and the front-end output terminal, and configured to pull-down the front-end output terminal and the pull-up node to a supply voltage of the first supply voltage terminal when a pull-down signal at the pull-down node is at an active pull-down level; and
an output circuit comprising an output switch connected to the clock signal terminal, the pull-up node and the front-end output terminal and configured to output the clock signal of the clock signal terminal to the front-end output terminal when the pull-up signal at the pull-up node is at an active pull-up level.
The invention provides a grid driving circuit which comprises a plurality of cascade-connected grid driving units.
The invention provides a display device which comprises the grid driving circuit.
The invention provides a grid driving method of a display device, which comprises the following steps:
when an input signal of the signal input end is at an effective input level, the first grid driving circuit controls the output switch to output a clock signal of the clock signal end to the front-end output end so as to output a first output signal;
the second circuit divides the first output signal according to the first resistor and the second resistor, and outputs the voltage on the second resistor as a second output signal from an output end.
For example, in the gate driving method provided by some embodiments of the present application, the controlling the output switch to output the clock signal of the clock signal terminal to the front-end output terminal to output the first output signal when the input signal of the signal input terminal is at the valid input level further includes: when the output capability of the output switch is reduced, the first output signal is reduced;
the second circuit divides the first output signal according to a first resistor and a second resistor, and outputs the voltage across the second resistor as a second output signal from an output terminal, further comprising: the resistance value of the second resistor is increased to compensate the second output signal;
or
When the input signal of the signal input end is at the effective input level, the first gate driving circuit controls the output switch to output the clock signal of the clock signal end to the front-end output end to output the first output signal further comprises: when the output capacity of the output switch rises, the first output signal increases;
the second circuit divides the first output signal according to a first resistor and a second resistor, and outputs the voltage across the second resistor as a second output signal from an output terminal, further comprising: the resistance value of the second resistor is reduced to compensate the second output signal.
The invention has the following beneficial effects:
aiming at the existing problems, the invention provides a grid driving unit, a grid driving circuit, a display device and a grid driving method, wherein the grid driving unit comprises a first grid driving circuit and a second circuit, the first grid driving circuit comprises an output switch, the second circuit comprises a first resistor and a second resistor, and the second resistor with the same fluctuation characteristic as the output switch is used, so that the difference of electric signals output by each grid driving unit is effectively improved, the problem of uneven display caused by different output voltages among different rows due to process fluctuation of a thin film transistor is relieved, the display effect is improved, and the grid driving unit has practical application value.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 shows a block diagram of a gate driving unit according to an embodiment of the present invention;
fig. 2 is a circuit diagram of the gate driving unit according to an embodiment of the invention;
FIG. 3 illustrates a cross-sectional view of the second resistor in accordance with one embodiment of the present invention;
fig. 4 shows a flowchart of a gate driving method according to an embodiment of the invention.
Detailed Description
In order to more clearly illustrate the invention, the invention is further described below with reference to preferred embodiments and the accompanying drawings. Similar parts in the figures are denoted by the same reference numerals. It is to be understood by persons skilled in the art that the following detailed description is illustrative and not restrictive, and is not to be taken as limiting the scope of the invention.
In the prior art, the display device using the GOA technology has the problem of uneven display of a display device screen caused by uneven voltage of output ends of all GOA units.
In view of the above situation, the inventors have made extensive studies and experiments to propose that the voltage non-uniformity at the output of the GOA cell is due to: in the prior art, the output voltage is controlled by changing the internal driving structure of the GOA unit (such as the aspect ratio of the thin film transistor) to change the display brightness, but the output voltage of each GOA unit is not uniform due to the influence of the working environment of the thin film transistor, so that the difference is generated, the gate signal input to the display substrate is also different, the display of the panel is not uniform, and the quality of the product is greatly influenced.
In view of the above-described problems and the causes for the problems, as shown in fig. 1, one embodiment of the present invention provides a gate driving unit including:
the first grid driving circuit is connected with a signal input end, a clock signal end and a front end output end and comprises an output switch, and the output switch is connected with the front end output end and the clock signal end;
the second circuit is connected with the front end output end and the output end and comprises a first resistor and a second resistor, wherein one end of the first resistor is connected with the front end output end, the other end of the first resistor is connected with the output end, one end of the second resistor is connected with the output end, the other end of the second resistor is connected with the first signal line, and the second resistor has the same fluctuation characteristic with the output switch.
In this embodiment, in view of the problem of manufacturing process of the thin film transistor in the prior art, there is a difference in the output gate signals caused by fluctuation in different operating environments, which results in uneven display, the gate driving unit is provided with: the first grid driving circuit is used for realizing the function of outputting the grid driving signals, and the second circuit is used for adjusting the difference of each grid driving unit, the difference of electric signals output by each grid driving unit can be improved through the first resistor and the second resistor, wherein the first resistor and the second resistor have the same fluctuation characteristic as the first grid driving circuit, the difference of electric signals output by each grid driving unit can be improved, the problem of uneven display caused by different output voltages among different rows due to process fluctuation of the thin film transistor is effectively solved, the display effect is improved, and the display circuit has practical application value.
In a specific example, as shown in fig. 2, the first gate driving circuit, which includes an input circuit 201, a reset circuit 202, a pull-down control circuit 203, a pull-down circuit 204, and an output circuit 205, includes a plurality of thin film transistors and a plurality of capacitors, wherein the output switch M3 is turned on in response to a potential of the pull-up node to output a clock signal of the clock signal terminal to the front-end output terminal to output a first output signal.
In an alternative embodiment, the first gate driving circuit includes:
the Input circuit 201 is connected to the signal Input terminal and the pull-up node PU, and configured to pass the received Input signal to the pull-up node PU when the Input signal Input at the signal Input terminal is at an active Input level.
The RESET circuit 202 is connected to the RESET signal terminal RESET, the first power supply voltage terminal VSS, and the pull-up node PU, and is configured to pull down the pull-up signal at the pull-up node PU to the power supply voltage of the first power supply voltage terminal VSS when the RESET signal of the RESET signal terminal RESET is at an active control level.
The pull-down control circuit 203 is connected to the second power voltage terminal VDD1, the third power voltage terminal VDD2, the pull-up node PU, the pull-down nodes PD1 and PD2, and the first power voltage terminal VSS, and configured to control whether the pull-down circuit 204 operates.
For example, the pull-down control circuit 203 generates a pull-down signal at a non-active pull-down level at the pull-down node PD when the pull-up signal at the pull-up node PU is at an active pull-up level; while the pull-up signal at the pull-up node PU is at a non-active pull-up level, the high-level voltage signal VDD1 or VDD2 is supplied to the pull-down nodes PD1 and PD2 in response to the high-level voltage signal VDD1 or VDD 2.
The pull-down circuit 204 is connected to the pull-down node PD, the pull-up node PU, the first power voltage terminal VSS, and the front-end output terminal, and configured to pull down the front-end output terminal and the pull-up node PU to the power voltage of the first power voltage terminal VSS when the pull-down signal at the pull-down node PD is at an effective pull-down level.
The output circuit 205 is connected to the clock signal terminal CLK, the pull-up node PU and the front-end output terminal, and configured to output the clock signal of the clock signal terminal CLK to the front-end output terminal when the pull-up signal at the pull-up node PU is at an active pull-up level.
In the present embodiment, the INPUT circuit 201 includes an INPUT transistor M1, a gate and a first pole of the INPUT transistor M1 are connected to the signal INPUT terminal INPUT, and a second pole of the INPUT transistor M1 is connected to the pull-up node PU. When the INPUT signal at the signal INPUT terminal INPUT is at a high level, the INPUT transistor M1 is turned on, and transmits the INPUT signal at the signal INPUT terminal INPUT to the pull-up node PU.
It should be noted that the specific implementation structure, control manner, and the like of the input circuit 201 do not limit the embodiments of the present disclosure.
In the present embodiment, the RESET circuit 202 includes a RESET transistor M2, a gate of the RESET transistor M2 is connected to a RESET signal terminal RESET, a first pole is connected to the pull-up node PU, and a second pole is connected to the first power supply voltage terminal VSS. When the RESET signal at the RESET signal terminal RESET is at a high level, the RESET transistor M2 is turned on, pulling down the pull-up signal at the pull-up node PU to the supply voltage of the first supply voltage terminal VSS. It is worth noting that the reset circuit 202 is merely an example, and may have other configurations.
In the present embodiment, the pull-down control circuit 203 includes a first pull-down control circuit and a second pull-down control circuit, and the pull-down node PD includes a first pull-down node PD1 and a second pull-down node PD2. The first pull-down control circuit includes a first pull-down control transistor M5, a second pull-down control transistor M6, a third pull-down control transistor M9, and a fourth pull-down control transistor M8. The grid electrode of the first pull-down control transistor M5 is connected with a first pull-down control node PD _ CN1, the first pole is connected with a second power supply voltage end VDD1, and the second pole is connected with the first pull-down node PD 1; the gate of the second pull-down control transistor M6 is connected to the pull-up node PU, the first pole is connected to the first pull-down node PD1, and the second pole is connected to the first power supply voltage terminal VSS; the grid and the first pole of the third pull-down control transistor M9 are connected with the second power supply voltage end VDD1, and the second pole is connected with the first pull-down control node PD _ CN 1; the gate of the fourth pull-down control transistor M8 is connected to the pull-up node PU, the first pole is connected to the first pull-down control node PD _ CN1, and the second pole is connected to the first power voltage terminal VSS.
The second pull-down control circuit includes a fifth pull-down control transistor M5', a sixth pull-down control transistor M6', a seventh pull-down control transistor M9', and an eighth pull-down control transistor M8'. The gate of the fifth pull-down control transistor M5' is connected to the second pull-down control node PD _ CN2, the first pole is connected to the third power voltage terminal VDD2, and the second pole is connected to the second pull-down node PD 2; a gate of the sixth pull-down control transistor M6' is connected to the pull-up node PU, a first pole is connected to the second pull-down node PD2, and a second pole is connected to the first power voltage terminal VSS; the gate and the first pole of the seventh pull-down control transistor M9' are connected to the third power voltage terminal VDD2, and the second pole is connected to the second pull-down control node PD _ CN 2; the gate of the eighth pull-down control transistor M8' is connected to the pull-up node PU, the first pole is connected to the second pull-down control node PD _ CN2, and the second pole is connected to the first power voltage terminal VSS.
In the present embodiment, the pull-down circuit 204 includes a first pull-down circuit and a second pull-down circuit. The first pull-down circuit comprises a first node pull-down transistor M10 and a first output pull-down transistor M11, a grid electrode of the first node pull-down transistor M10 and a grid electrode of the first output pull-down transistor M11 are connected with a first pull-down node PD1, a second pole of the first node pull-down transistor M10 and a second pole of the first output pull-down transistor M11 are connected with a first power supply voltage end VSS, a first pole of the first node pull-down transistor M10 is connected with a pull-up node PU, and a first pole of the first output pull-down transistor M11 is connected with a front end output end. When the pull-down signal at the first pull-down node PD1 is at a high level, the first node pull-down transistor M10 and the first output pull-down transistor M11 are turned on, respectively pulling down the pull-up node PU and the front-end output terminal to the power supply voltage of the first power supply voltage terminal VSS.
The second pull-down circuit comprises a second node pull-down transistor M10 'and a second output pull-down transistor M11', the grid electrode of the second node pull-down transistor M10 'and the grid electrode of the second output pull-down transistor M11' are connected with a second pull-down node PD2, the second pole of the second node pull-down transistor M10 'and the second pole of the second output pull-down transistor M11' are connected with a first power supply voltage terminal VSS, the first pole of the second node pull-down transistor M10 'is connected with a pull-up node PU, and the first pole of the second output pull-down transistor M11' is connected with a front end output end. When the pull-down signal at the second pull-down node PD2 is at a high level, the second node pull-down transistor M10 'and the second output pull-down transistor M11' are turned on, respectively pulling down the pull-up node PU and the front-end output terminal to the power supply voltage of the first power supply voltage terminal VSS.
It is to be noted that the pull-down control circuit 203 and the pull-down circuit 204 described above are merely examples, and may have other configurations.
In this embodiment, the output circuit 205 includes an output switch M3 and a second capacitor C2, a gate of the output switch M3 is connected to the pull-up node PU, a first pole of the output switch M3 is connected to the clock signal terminal CLK, and a second pole of the output switch M3 is connected to the front-end output terminal; a first end of the second capacitor C2 is connected to the pull-up node PU, and a second end of the second capacitor C2 is connected to the front-end output terminal. When the pull-up signal at the pull-up node PU is at a high level, the output switch M3 is turned on, and outputs the second clock signal of the clock signal terminal CLK to the front-end output terminal.
It should be noted that the output circuit 205 described above is merely an example, and may have other structures.
It should be noted that the first gate driving circuit in this embodiment is only used to illustrate a specific implementation manner of the present application, and the present application is not limited to this specific implementation manner.
In the present embodiment, as shown in fig. 2, the second circuit includes a first resistor R0 and a second resistor M12, and the second resistor M12 has the same ripple characteristic as the output switch M3.
The output switch and the second resistor are both thin film transistors, the second resistor M12 includes a control end, a first end and a second end, the control end is connected with a second signal line, the first end is connected with the output end, and the second end is connected with the first signal line.
Specifically, as shown in fig. 3, the second resistor M12 includes:
a gate 101 provided on the substrate 100, the gate 101 being connected to a second signal line Vgh,
a gate insulating layer 102 covering the gate electrode 101, the gate insulating layer 102 being G-SiNX,
an active layer 103 disposed on the gate insulating layer 102, the active layer 103a-Si,
and a source electrode 104 and a drain electrode 105 disposed on the active layer 103, wherein one of the source electrode 104 and the drain electrode 105 is connected to the first signal line Vgl, and the other is connected to the output terminal V01.
In the present embodiment, the active layer 103a-Si is a core layer of the thin film transistor, and the electrical characteristics and functions of the thin film transistor are mainly determined by the layer material, wherein the film quality of the active layer 103a-Si affects the current of the thin film transistor. Specifically, under the same conditions, the better the film quality of the active layer 103a-Si, the higher the current, and vice versa, and according to the relationship between the film quality of the sheet resistance and the resistance: r = ρ L/S, where ρ is the resistivity, L is the length of the material, S is the area, and L and S are related to the membranous.
In this embodiment, the output switch M3 and the second resistor M12 are formed simultaneously by using the same material and the same process step, that is, the second resistor M12 and the output switch M3 have the same ripple characteristics.
Specifically, the output switch M3 and the second resistor M12 in this embodiment use the same active layer a-Si material, and the process conditions, especially the film quality, are the same, when the film quality changes due to process fluctuation, the film quality of the second resistor M12 and the output switch M3 of the first gate driving circuit will change synchronously, so that the process difference of a-Si in the output switch M3 is improved by using the second resistor M12. Furthermore, since the active layer a-si is made of a semiconductor material and has a large resistance, the gate of the second resistor M12 is connected to the high-voltage signal Vgh, and the source and the drain are respectively connected to the low-voltage signal Vgl and the output terminal V01, so that the second resistor M12 is turned on to realize a voltage division function, and the voltage value of the voltage V01 output by the output terminal is adjusted.
It should be noted that the active layer and the gate insulating layer used in this embodiment are made of a-Si and G-SiNX only for describing the specific embodiments of the present application, and the material of the thin film transistor is not particularly limited. Also, it will be understood by those skilled in the art that thin film transistors formed with the same materials, process steps, and the like have the same ripple characteristics. Therefore, those skilled in the art should select appropriate materials and process steps to fabricate the thin film transistor according to the actual application requirements, and detailed description thereof is omitted here.
In the practical application process, when an input signal of a signal input end is at an effective input level, a first grid driving circuit controls an output switch to output a clock signal of a clock signal end to a front-end output end so as to output a first output signal; the second circuit divides the first output signal according to the first resistor and the second resistor, and outputs the voltage on the second resistor as a second output signal from an output end.
In the prior art, the gate driving circuit only includes the first gate driving circuit, the first output signal output from the front end output terminal is transmitted to the display substrate as the gate driving signal, and when the output switch M3 has fluctuation, a voltage difference exists between the gate driving signals output from different rows.
Specifically, as shown in fig. 2, the gate driving signal output by the gate driving circuit is a first output signal V1 output by the front end output terminal in the figure, and when the process fluctuation causes the first output signal V1 to change into V1', where V1' = xV1, the voltage difference change is the difference (1-x) V1 'between V1 and V1'.
In this embodiment, the second resistor having the same fluctuation characteristic as the output switch M3 is used to reduce the fluctuation of the gate driving signal caused by the output switch M3, so as to improve the voltage difference between the gate driving signals output by different rows, thereby improving the display effect of the display device.
Specifically, when the gate driving unit does not work, no signal is output from CLK, and a first output signal V1 output by the front-end output terminal is at a low level; since the second resistor M12 is connected to the low voltage signal Vgl, the gate driving signal V01 output by the output terminal is at a low level, i.e., there is no voltage difference between the two ends of the first resistor R0, and the gate driving signal V01 output by the output terminal is the low voltage signal Vgl. Therefore, the signals output between the grid driving units in each row have no voltage difference.
Specifically, when the gate driving unit operates, CLK is an effective signal output, the output switch M3 is turned on, and the first output signal V1 output by the front-end output terminal is at a high level; meanwhile, the second resistor M12 is turned on, the first resistor R0 and the second resistor M12 form a series circuit, and the gate driving signal V01 output by the output terminal is an electrical signal divided by the second resistor M12.
Specifically, the current of the series loop is:
Figure BDA0003274432130000081
thus, the following results are obtained:
Figure BDA0003274432130000082
in the present embodiment, when the process fluctuation causes the first output signal V1 to change to V1', the differential pressure thereof changes to the difference (1-x) V1' between V1 and V1'.
Meanwhile, the fluctuation of the gate driving signal V01 output from the output terminal due to process fluctuation is V01', that is, xV01, and the voltage difference thereof varies as the difference between V01 and V01':
Figure BDA0003274432130000091
in an optional embodiment, the fluctuation of the resistance of the second resistor M12 follows the fluctuation of the output switch M3, and the resistance of the first resistor R0 is within the range of the change of the resistance of the second resistor M12, specifically, the resistance of the first resistor is greater than or equal to 1k Ω and less than or equal to 3k Ω.
I.e., R0 is approximately equal to M12, then
Figure BDA0003274432130000092
Therefore, the difference between the output gate driving signals of the gate driving unit of this embodiment due to the process fluctuation is:
Figure BDA0003274432130000093
in the prior art, the difference of the output gate driving signals of the gate driving unit caused by process fluctuation is as follows: (1-x) V1', i.e., the difference of the gate driving signals of the present embodiment is smallIn the prior art, the difference of the gate driving signals, that is, the second resistor having the same fluctuation characteristic as the output switch is used in the embodiment, the difference of the electrical signals output by each gate driving unit can be improved, the problem of uneven display caused by different output voltages between different rows due to process fluctuation of the thin film transistor is effectively solved, the display effect is improved, and the display device has practical application value.
In a specific example, as shown in fig. 2, when the output capability of the output switch M3 is reduced, the first output signal V1 is reduced, the resistance value of the second resistor M12 is increased to compensate for a second output signal output by the output terminal, which is a gate driving signal, so that the difference of output gate driving signals caused by the fluctuation of the output switch M3 is improved, and the display effect is effectively improved.
In another specific example, as shown in fig. 2, when the output capability of the output switch M3 increases, the first output signal V1 increases, the resistance of the second resistor M12 decreases to compensate for the second output signal output by the output terminal, which is the gate driving signal, so as to improve the difference of the output gate driving signals caused by the fluctuation of the output switch M3, and effectively improve the display effect.
Based on the gate driving unit of the above embodiment, the present application further provides a gate driving circuit, which includes a plurality of cascaded gate driving units.
The gate driving unit of the present embodiment can be applied to a liquid crystal display device as well as an electroluminescent diode display device.
Based on the gate driving circuit of the above embodiment, the present application further provides a display device, including the gate driving circuit.
The display device of the present embodiment may be a liquid crystal display device or an electroluminescent diode display device. It should be noted that the foregoing embodiments and the following advantageous effects are also applicable to the present embodiment, and therefore, the same portions are not described again.
Based on the gate driving unit, the gate driving circuit and the display device of the above embodiments, an embodiment of the present application further provides a gate driving method, as shown in fig. 4, including:
when the input signal of the signal input end is at an effective input level, the first grid drive circuit controls the output switch to output the clock signal of the clock signal end to the front end output end so as to output a first output signal;
the second circuit divides the first output signal according to the first resistor and the second resistor, and outputs the voltage on the second resistor as a second output signal from an output end.
In this embodiment, in view of the problem of manufacturing process of the thin film transistor in the prior art, there is a difference in the output gate signals caused by fluctuation in different operating environments, which results in uneven display, the gate driving unit is provided with: the first grid driving circuit is used for outputting grid driving signals, and the second circuit is used for adjusting the difference of each grid driving unit.
In an optional embodiment, the controlling the output switch to output the clock signal from the clock signal terminal to the front-end output terminal to output the first output signal when the input signal at the signal input terminal is at the valid input level further comprises: when the output capability of the output switch is reduced, the first output signal is reduced; the second circuit divides the first output signal according to the first resistor and the second resistor, and outputs the voltage across the second resistor as the second output signal from the output terminal, further comprising: the resistance of the second resistor is increased to compensate for the second output signal.
In this embodiment, the second resistor having the same fluctuation characteristic as the output switch follows the fluctuation of the output switch, so that the difference of the electrical signals output by each gate driving unit is improved, the problem of uneven display caused by different output voltages between different rows due to process fluctuation of the thin film transistor is effectively solved, and the display effect can be improved.
In another optional embodiment, the controlling the output switch to output the clock signal from the clock signal terminal to the front-end output terminal to output the first output signal when the input signal at the signal input terminal is at the valid input level further comprises: when the output capacity of the output switch rises, the first output signal increases; the second circuit divides the first output signal according to the first resistor and the second resistor, and outputs the voltage across the second resistor as the second output signal from the output terminal, further comprising: the resistance value of the second resistor is reduced to compensate the second output signal.
In this embodiment, the second resistor having the same fluctuation characteristic as the output switch follows the fluctuation of the output switch, so that the difference of the electrical signals output by each gate driving unit is improved, the problem of uneven display caused by different output voltages between different rows due to process fluctuation of the thin film transistor is effectively solved, and the display effect can be improved.
Since the gate driving method provided by this embodiment corresponds to the display devices provided by the above embodiments, the previous embodiments are also applicable to the gate driving method provided by this embodiment, and will not be described in detail in this embodiment.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention, and it will be obvious to those skilled in the art that other variations or modifications may be made on the basis of the above description, and all embodiments may not be exhaustive, and all obvious variations or modifications may be included within the scope of the present invention.

Claims (9)

1. A gate drive unit, comprising:
the first grid driving circuit is connected with a signal input end, a clock signal end and a front end output end and comprises an output switch, and the output switch is connected with the front end output end and the clock signal end;
the second circuit is connected with the front-end output end and the output end and comprises a first resistor and a second resistor, wherein one end of the first resistor is connected with the front-end output end, the other end of the first resistor is connected with the output end, one end of the second resistor is connected with the output end, and the other end of the second resistor is connected with the first signal line;
the first gate driving circuit includes:
an input circuit connected to a signal input and a pull-up node, configured to pass a received input signal to the pull-up node when the input signal at the signal input is at an active input level;
a reset circuit connected to the reset signal terminal, the first power voltage terminal and the pull-up node, and configured to pull down the pull-up signal at the pull-up node to the power voltage of the first power voltage terminal when the reset signal of the reset signal terminal is at an active control level;
the pull-down control circuit is connected with the second power supply voltage end, the third power supply voltage end, the pull-up node, the pull-down node and the first power supply voltage end and is configured to control whether the pull-down circuit operates or not;
a pull-down circuit connected to a pull-down node, a pull-up node, a first supply voltage terminal, and the front-end output terminal, and configured to pull-down the front-end output terminal and the pull-up node to a supply voltage of the first supply voltage terminal when a pull-down signal at the pull-down node is at an active pull-down level; and
an output circuit comprising an output switch connected to the clock signal terminal, the pull-up node and the front-end output terminal and configured to output the clock signal of the clock signal terminal to the front-end output terminal when the pull-up signal at the pull-up node is at an active pull-up level. .
2. A gate driving unit according to claim 1, wherein the output switch and the second resistor are both thin film transistors, the second resistor includes a control terminal, a first terminal and a second terminal, the control terminal is connected to a second signal line, the first terminal is connected to the output terminal, and the second terminal is connected to the first signal line.
3. A gate drive unit as claimed in claim 2, wherein the second resistor and the output switch are formed simultaneously using the same material and the same process steps.
4. A gate drive unit as claimed in claim 3, wherein the active layer of the second resistor is a-Si and the gate insulating layer of the second resistor is G-SiNX.
5. A gate drive unit as claimed in claim 3, wherein the fluctuations of the resistance of the second resistor follow the fluctuations of the output switch, and the resistance of the first resistor is within a variation range of the resistance of the second resistor;
the resistance value of the first resistor is larger than or equal to 1k omega and smaller than or equal to 3k omega.
6. A gate drive circuit comprising a plurality of cascaded gate drive units according to any one of claims 1-5.
7. A display device comprising the gate driver circuit according to claim 6.
8. A gate driving method using the display device according to claim 7, comprising:
when an input signal of the signal input end is at an effective input level, the first grid driving circuit controls the output switch to output a clock signal of the clock signal end to the front-end output end so as to output a first output signal;
the second circuit divides the first output signal according to the first resistor and the second resistor, and outputs the voltage on the second resistor as a second output signal from an output end.
9. The gate driving method according to claim 8,
when the input signal of the signal input end is at the effective input level, the first gate driving circuit controls the output switch to output the clock signal of the clock signal end to the front-end output end to output the first output signal further comprises: when the output capability of the output switch is reduced, the first output signal is reduced;
the second circuit divides the first output signal according to a first resistor and a second resistor, and outputs the voltage across the second resistor as a second output signal from an output terminal, further comprising: the resistance value of the second resistor is increased to compensate the second output signal;
or
When the input signal of the signal input end is at the effective input level, the first gate driving circuit controls the output switch to output the clock signal of the clock signal end to the front-end output end to output the first output signal further comprises: when the output capacity of the output switch is increased, the first output signal is increased;
the second circuit divides the first output signal according to a first resistor and a second resistor, and outputs the voltage across the second resistor as a second output signal from an output terminal, further comprising: the resistance value of the second resistor is reduced to compensate the second output signal.
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