CN113612908A - Image acquisition and display device based on FPGA - Google Patents

Image acquisition and display device based on FPGA Download PDF

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Publication number
CN113612908A
CN113612908A CN202110870623.4A CN202110870623A CN113612908A CN 113612908 A CN113612908 A CN 113612908A CN 202110870623 A CN202110870623 A CN 202110870623A CN 113612908 A CN113612908 A CN 113612908A
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China
Prior art keywords
fpga
chip
module
display
interface
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CN202110870623.4A
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Chinese (zh)
Inventor
王明博
曾文兵
王亚飞
左国星
朱祥
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Hubei Sanjiang Aerospace Wanfeng Technology Development Co Ltd
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Hubei Sanjiang Aerospace Wanfeng Technology Development Co Ltd
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Priority to CN202110870623.4A priority Critical patent/CN113612908A/en
Publication of CN113612908A publication Critical patent/CN113612908A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/50—Constructional details
    • H04N23/54—Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/60—Control of cameras or camera modules
    • H04N23/667—Camera operation mode switching, e.g. between still and video, sport and normal or high- and low-resolution modes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/80—Camera processing pipelines; Components thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/765—Interface circuits between an apparatus for recording and another apparatus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/18—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

The invention discloses an image acquisition and display device based on FPGA, comprising: the device comprises an FPGA chip, a Camera Link decoding chip, a digital-to-analog conversion chip and a transceiver; the FPGA chip comprises a Camera Link acquisition interface, a display interface capable of being switched between a PAL system and a VGA mode and an asynchronous RS422 interface, the Camera Link decoding chip is electrically connected with the FPGA chip through the Camera Link acquisition interface, the digital-to-analog conversion chip is electrically connected with the FPGA chip through the display interface, and the transceiver is electrically connected with the FPGA chip through the asynchronous RS422 interface. The invention can realize the collection of image data, display and output of the collected image data after overlapping characters, and switch between PAL mode and VGA mode during display and output, and has the advantages of good performance, high real-time performance and low cost.

Description

Image acquisition and display device based on FPGA
Technical Field
The invention belongs to the technical field of information processing, and particularly relates to an image acquisition and display device based on an FPGA (field programmable gate array).
Background
Although the conventional image acquisition and display device can also realize image acquisition and display with high resolution and high frame frequency, the cost, power consumption, reliability, real-time performance, starting time and other aspects of the system are not satisfactory, so that an image acquisition and display solution with high real-time performance and low power consumption at lower cost and power consumption is urgently needed.
Disclosure of Invention
Aiming at least one defect or improvement requirement in the prior art, the invention provides an image acquisition and display device based on an FPGA (field programmable gate array), which can realize the acquisition of image data, the display output of the acquired image data after overlapping characters and the switching between a PAL (programmable array) mode and a VGA (video graphics array) mode during the display output and has the advantages of good performance, high real-time performance and low cost.
To achieve the above object, according to a first aspect of the present invention, there is provided an image capturing and displaying apparatus based on an FPGA, comprising: the device comprises an FPGA chip, a Camera Link decoding chip, a digital-to-analog conversion chip and a transceiver;
the FPGA chip comprises a Camera Link acquisition interface, a display interface capable of being switched between a PAL system and a VGA mode and an asynchronous RS422 interface, the Camera Link decoding chip is electrically connected with the FPGA chip through the Camera Link acquisition interface, the digital-to-analog conversion chip is electrically connected with the FPGA chip through the display interface, and the transceiver is electrically connected with the FPGA chip through the asynchronous RS422 interface;
the image acquisition and display device is in serial communication with an upper computer through the transceiver, and performs information interaction with the Camera Link decoding chip and the digital-to-analog conversion chip according to an instruction of the upper computer, so that image data acquisition, display output of the acquired image data after characters are overlapped, and switching between a PAL mode and a VGA mode during display output are realized.
Preferably, the image acquisition and display device based on the FPGA further comprises a data cache module, and the data cache module and the FPGA chip adopt a Fly-By topology structure, so that all chips of the data cache module share a control line and an address line.
Preferably, the image acquisition and display device based on the FPGA further comprises a power circuit, and the power circuit comprises an EMI filter, a DC/DC isolation power module and a voltage reduction and stabilization module which are electrically connected in sequence.
Preferably, the image acquisition and display device based on the FPGA further comprises a watchdog circuit, the FPGA chip further comprises a power-on reset interface, the watchdog circuit is electrically connected with the FPGA chip through the power-on reset interface, the watchdog circuit is used for monitoring the input voltage of the power module, and if the input voltage of the power module drops to a preset threshold value, a reset signal is generated to enable the FPGA chip to enter a reset state.
Preferably, the FPGA chip includes a PAL display module and a VGA display module, the PAL display module is configured to generate PAL-mode image signals, and the VGA display module is configured to generate VGA-mode image signals.
Preferably, the PAL display module is divided into a PLL module, a synchronization module, and a PAL control module, the PLL module divides a system clock into, for example, a PAL signal pixel clock, the synchronization module completes implementation of signals such as a line blanking pulse, a line synchronization pulse, a front equalization pulse, a rear equalization pulse, a tooth pulse, a line blanking, a field blanking, and the like, and then processes a composite synchronization signal and a composite blanking signal, and is further configured to output a parity field FIFO read-write enable signal, and the PAL control module implements reading of image data according to the parity field FIFO read-write enable signal output by the synchronization module.
Preferably, the VGA display module is divided into a PLL (phase locked loop) module, a synchronization module and a VGA control module, the PLL module is used for dividing the frequency of a system clock into pixel clocks of VGA signals, the synchronization module is used for realizing the control of line-field synchronization signals and also used for outputting the current line address, column address and effective signals of an image display area, and the VGA control module is used for realizing the control of RGB (red, green and blue) signals, the control of the line address and the column address, the image display control and the frame control function.
Preferably, the transceiver comprises a power isolation and signal isolation module.
Preferably, the FPGA chip adopts an XC7K325T-2FFG900 chip, the Camera Link decoding chip adopts a DS90CR286AMTD chip, the digital-to-analog conversion chip adopts an ADV7123 chip, and the transceiver adopts an LTM2881 type transceiver.
Preferably, the watchdog circuit is implemented by a MAX708S chip.
In general, compared with the prior art, the invention has the following beneficial effects: the FPGA-based image acquisition and display device takes a programmable logic unit FPGA as a core and is combined with a high-capacity cache chip to realize embedded image acquisition and display with high performance, high real-time performance, low power consumption and low cost. Specifically, the method is characterized in that:
(1) by adopting the scheme of the embedded system, the starting time is short, the cost is low, the reliability is high, and the environmental suitability is strong.
(2) The image acquisition can realize the real-time acquisition and display of high-resolution and high-frame-frequency images.
(3) The PAL display system and the VGA display system can automatically switch the display system according to the instruction, automatically filter the image noise and complete the blind pixel replacement.
(4) And the asynchronous RS422 serial port display information is received through the transceiver and the asynchronous RS422 interface, and the image acquired by the FPGA is overlapped with part of the characters and then is displayed and output through the PAL/VGA, so that the function of automatically overlapping the characters is realized.
(5) The power consumption management module can switch between a low power consumption mode and a full-speed mode according to the instruction, so that the power consumption of the system is further reduced.
(6) The method is suitable for vehicle-mounted, ship-mounted and airborne high-speed image acquisition and display scenes, and has good application value and popularization prospect.
Drawings
FIG. 1 is a schematic diagram of an FPGA-based image capture and display device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an FPGA chip of an embodiment of the present invention;
FIG. 3 is a schematic diagram of a data caching module according to an embodiment of the invention;
FIG. 4 is a schematic diagram of a power supply circuit of an embodiment of the present invention;
FIG. 5 is a schematic diagram of a Camera Link image acquisition signal according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a PAL/VGA display driver according to an embodiment of the invention;
FIG. 7 is a schematic diagram of a PAL display module according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a VGA display module in accordance with an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
The image acquisition and display device based on the FPGA comprises: the device comprises an FPGA chip, a Camera Link decoding chip, a digital-to-analog conversion chip and a transceiver. The FPGA chip comprises a Camera Link acquisition interface, a display interface capable of switching between a PAL system and a VGA mode and an asynchronous RS422 interface, the Camera Link decoding chip is electrically connected with the FPGA chip through the Camera Link acquisition interface, the digital-to-analog conversion chip is electrically connected with the FPGA chip through the display interface, and the transceiver is electrically connected with the FPGA chip through the asynchronous RS422 interface.
The image acquisition and display device is in serial communication with the upper computer through the transceiver, and performs information interaction with the Camera Link decoding chip and the digital-to-analog conversion chip according to the instruction of the upper computer, so that the acquisition of image data, the display output of the acquired image data after overlapping characters, and the switching between the PAL mode and the VGA mode during the display output are realized.
Furthermore, the image acquisition and display device based on the FPGA also comprises a data cache module, and the data cache module and the FPGA chip adopt a Fly-By topological structure, so that all chips of the data cache module share a control line and an address line.
Furthermore, the image acquisition and display device based on the FPGA further comprises a power circuit, and the power circuit comprises an EMI filter, a DC/DC isolation power module and a voltage reduction and stabilization module which are sequentially and electrically connected.
Furthermore, the image acquisition and display device based on the FPGA further comprises a watchdog circuit, the FPGA chip further comprises a power-on reset interface, the watchdog circuit is electrically connected with the FPGA chip through the power-on reset interface, the watchdog circuit is used for monitoring the input voltage of the power module, and if the input voltage of the power module drops to a preset threshold value, a reset signal is generated to enable the FPGA chip to enter a reset state.
Furthermore, the FPGA chip comprises a PAL display module and a VGA display module, wherein the PAL display module is used for generating PAL-mode image signals, and the VGA display module is used for generating VGA-mode image signals.
In one embodiment, the FPGA chip preferably adopts an XC7K325T-2FFG900 chip, the Camera Link decoding chip preferably adopts a DS90CR286AMTD chip, the digital-to-analog conversion chip adopts an ADV7123 chip, and the transceiver preferably adopts an LTM2881 type transceiver.
As shown in fig. 1, the image acquisition and display device adopts K7 series FPGA chip XC7K325T-2FFG900 in combination with DS90CR286AMTD and ADV7123 to realize image acquisition and display. The data interface mainly comprises 1 path of Camera Link acquisition interface in a Medium mode, 1 path of asynchronous RS422 interface and one path of PAL/VGA display interface; meanwhile, the FPGA externally expands 4 pieces of DDR3 chips MT41J256M16HA-125IT and a 256Mbit NOR FLASH. The FPGA mainly completes the Camera Link acquisition, image quantization, PAL/VGA display driving, character superposition, DDR3 read-write and asynchronous RS422 interface protocol in a Medium mode. The asynchronous RS422 bus transceiver adopts an LTM2881 transceiver with power isolation and signal isolation, and the port of the transceiver is directly connected with the FPGA, so that the area of a PCB (printed circuit board) can be effectively reduced, and the reliability of a system is enhanced. And the asynchronous RS422 bus interface is connected with the upper computer to update and upgrade the FPGA program.
As shown in fig. 2, the FPGA chip of the embodiment of the present invention includes a DDR3 read-write module, a reset module, a Camera Link decoding module, a data processing module, an asynchronous RS422 IP core, a PAL display module, a VGA display module, and a PLL clock distribution module. The data processing module mainly realizes the functions of asynchronous RS422 data analysis and forwarding, image data flow control, video display system control, character superposition and the like.
As shown in fig. 3, the DDR3 selects four magnesium lights MT41J256M16HA-125IT to form a ping-pong architecture with a total capacity of 2GB, thereby realizing high resolution and high frame rate image data caching. A Fly-By topological structure is adopted between the FPGA and the DDR3 chips, so that control lines and address lines are shared between the DDR3 chips, and the topological complexity is simplified. The DDR3 bus has a read-write rate of 1.6Gbps/32bit, and meets the read-write requirements of 1920 multiplied by 1080/100Hz high resolution, high frame frequency and real-time images.
As shown in fig. 4, the external power supply voltage input range of the system is 16V to 40V, and the power supply circuit adopts a multi-stage power supply mode. The external power supply 24VDC _ EXT is converted into 28V and 28V _ GND in the board through an EMI filter (XGJLC252-1B-6A/50) and is converted into 12V through a DC/DC isolation power supply module WK 382812S-65M. 12V is converted to +0.75V, +1.0V, +1.2V, +1.5V, +3.3V, +5V required by the system via LTM4650 and LTM 4644. The voltages output by the power chips LTM4650 and LTM4644 are controlled by the FPGA chip, and the FPGA chip controls the output and the turn-off of the power chips according to the real-time working scene to control the power consumption of the system. Meanwhile, the FPGA adaptively reduces the read-write speed and the display frame frequency of the DDR3, and further reduces the power consumption of the system.
The power-on reset signal is generated by adopting MAX708S, the 24V power supply is monitored after optical coupling isolation, and if the power supply voltage is reduced to 15V (the power supply voltage range is 16V-40V), the reset signal is generated to enable the FPGA to enter a reset state, so that the system is prevented from being damaged when the voltage is abnormal. When the voltage returns to normal, the FPGA enters a working state, and the system returns to normal. The starting time of the equipment is mainly the starting time of the FPGA. The FPGA selects an XCF32P configuration circuit to realize loading starting after power-on, the configuration mode is an active parallel mode, the time consumption is about 60ms, the starting time of the watchdog circuit MAX708S is 200ms, and the total starting time is about 260 ms.
As shown in fig. 5, the Camerlink video signals are 4 sets of differential data signals and one set of differential clock signals, and are converted into 28 data signals and one clock signal PCLK by the serial decoder chip DS90CR286 AMTD. Wherein, the 28 data signal lines are respectively 3 groups of 8bit video data lines, and 3 groups of control lines of an FVAL field effective signal, an LVAL line effective signal and a DVAL data effective signal. And the 28 signal lines are connected into the FPGA, and the FPGA program completes video analysis according to the decoded clock, the decoded data effective signal, the decoded line field effective signal and the decoded image data according to the time sequence requirement of the thermal imager and stores the video analysis into a cache.
As shown in FIG. 6, PAL/VGA display is realized by using a digital-to-analog conversion chip DA 7123. All functional pins of the DA7123 are introduced into a general IO pin of the FPGA, and the PAL/VGA display system is controlled by the FPGA according to an asynchronous RS422 instruction.
As shown in fig. 7, the PAL display module is divided into a PLL phase-locked loop module, a synchronization module, and a PAL control module. Wherein the PLL module divides the system clock to a pixel clock of 13.5 Mhz; the PAL control module reads the image data in the FIFO according to the odd-even field FIFO read-write enabling signal output by the synchronization module.
As shown in fig. 8, the VGA display module is divided into a PLL module, a synchronization module, and a VGA control module. Wherein the PLL module divides the system clock to a pixel clock of 40 Mhz; the VGA control module is used for realizing the functions of controlling RGB signals, controlling row addresses and column addresses, controlling image display, controlling frames and the like.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (10)

1. The utility model provides an image acquisition and display device based on FPGA which characterized in that includes: the device comprises an FPGA chip, a Camera Link decoding chip, a digital-to-analog conversion chip and a transceiver;
the FPGA chip comprises a Camera Link acquisition interface, a display interface capable of being switched between a PAL system and a VGA mode and an asynchronous RS422 interface, the Camera Link decoding chip is electrically connected with the FPGA chip through the Camera Link acquisition interface, the digital-to-analog conversion chip is electrically connected with the FPGA chip through the display interface, and the transceiver is electrically connected with the FPGA chip through the asynchronous RS422 interface;
the image acquisition and display device is in serial communication with an upper computer through the transceiver, and performs information interaction with the Camera Link decoding chip and the digital-to-analog conversion chip according to an instruction of the upper computer, so that image data acquisition, display output of the acquired image data after characters are overlapped, and switching between a PAL mode and a VGA mode during display output are realized.
2. The FPGA-based image acquisition and display device of claim 1, further comprising a data cache module, wherein the data cache module and the FPGA chip adopt a Fly-By topology structure, so that control lines and address lines are shared among all chips of the data cache module.
3. The FPGA-based image capture and display device of claim 1, further comprising a power circuit comprising an EMI filter, a DC/DC isolation power module and a buck regulator module electrically connected in sequence.
4. The FPGA-based image acquisition and display device of claim 3, further comprising a watchdog circuit, wherein the FPGA chip further comprises a power-on reset interface, the watchdog circuit is electrically connected to the FPGA chip via the power-on reset interface, the watchdog circuit is configured to monitor the input voltage of the power module, and if the input voltage of the power module drops to a preset threshold, a reset signal is generated to enable the FPGA chip to enter a reset state.
5. The FPGA-based image capture and display device of claim 1, wherein the FPGA chip comprises a PAL display module for generating PAL-format image signals and a VGA display module for generating VGA-mode image signals.
6. The FPGA-based image capture and display device of claim 5, wherein the PAL display module is divided into a PLL module, a synchronization module, and a PAL control module, the PLL module divides a system clock into, for example, PAL signal pixel clocks, the synchronization module performs line blanking, line synchronization, pre-equalization, post-equalization, tooth, line blanking, and field blanking, and then the run-length composite synchronization and composite blanking signals, and further provides for an output odd-even field FIFO read/write enable signal, and the PAL control module reads image data according to the odd-even field FIFO read/write enable signal output by the synchronization module.
7. The FPGA-based image capture and display device of claim 5, wherein the VGA display module is divided into a PLL module for dividing a system clock into pixel clocks of VGA signals, a synchronization module for performing line-field synchronization signal control and outputting a current line address, a current column address and an image display area valid signal, and a VGA control module for performing RGB signal control, line address and column address control, image display control and frame control.
8. The FPGA-based image capture and display device of claim 1 wherein said transceiver comprises a power isolation and signal isolation module.
9. The FPGA-based image capturing and displaying device of claim 1, wherein said FPGA chip is XC7K325T-2FFG900 chip, said Camera Link decoding chip is DS90CR286AMTD chip, said digital-to-analog conversion chip is ADV7123 chip, and said transceiver is LTM2881 transceiver.
10. The FPGA-based image capture and display device of claim 4, wherein the watchdog circuit employs a MAX708S chip.
CN202110870623.4A 2021-07-30 2021-07-30 Image acquisition and display device based on FPGA Pending CN113612908A (en)

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Application publication date: 20211105