CN113612478B - ADC key circuit calibration method, system, storage medium and key circuit - Google Patents
ADC key circuit calibration method, system, storage medium and key circuit Download PDFInfo
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Abstract
An ADC key circuit calibration method, a system, a storage medium and a key circuit are provided, wherein the ADC key circuit calibration method comprises the following steps: acquiring a first reference sampling value corresponding to a first reference voltage actually output by an ADC output port of the key circuit when the key circuit is not operated; calculating error gain according to the first reference sampling value and the second reference sampling value, wherein the second reference sampling value is calculated according to a voltage division reference circuit, and the voltage division reference circuit is arranged at an ADC output port of the key circuit; and correcting the actual key voltage output by the output port of the ADC by using the error gain to obtain a key calibration voltage, wherein the actual key voltage is generated during key operation in the key circuit. The invention can obtain the error gain when the key circuit is not operated, and can realize the correction of the actual voltage value collected by the ADC channel by using the error gain when the key circuit is operated subsequently, thereby effectively solving the problem of reduced ADC identification precision and prolonging the service life of the key circuit.
Description
Technical Field
The invention belongs to the field of electronic circuits, and particularly relates to an ADC (analog to digital converter) key circuit calibration method, an ADC key circuit calibration system, a storage medium and a key circuit.
Background
A key circuit based on an ADC is a common circuit, and the principle is to implement multiple key detection through ADC channels. The ADC-based key circuit has two defects, one is that the difference between a voltage value sampled by an ADC channel and a theoretical voltage value is easily caused due to overlong key service time or change of working environment temperature, so that the sampled voltage value exceeds a key preset range, and the conditions of key interference and misoperation occur; secondly, the ADC circuit itself has a gain error, which is a deviation between an actual transmission characteristic curve and an ideal transmission characteristic curve of the ADC. Both of which ultimately lead to reduced ADC identification accuracy.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art. Therefore, the invention provides an ADC key circuit calibration method which solves the problem that the ADC identification precision is reduced. The invention also provides an ADC key circuit calibration system, an ADC key circuit and a storage medium for storing the computer executable instruction of the ADC key circuit calibration method.
According to the embodiment of the first aspect of the invention, the ADC keying circuit calibration method comprises the following steps:
acquiring a first reference sampling value corresponding to a first reference voltage actually output by an ADC output port of the key circuit when the key circuit is not operated;
calculating error gain according to the first reference sampling value and a second reference sampling value, wherein the second reference sampling value is obtained by calculation according to a voltage division reference circuit, and the voltage division reference circuit is arranged at an ADC (analog to digital converter) output port of the key circuit;
and correcting the actual key voltage output by the ADC output port by using the error gain to obtain a key calibration voltage, wherein the actual key voltage is generated during key operation in the key circuit.
The ADC key circuit calibration method provided by the embodiment of the invention at least has the following technical effects: the voltage division reference circuit can be used for calculating a second reference sampling value when the key circuit is not operated, and then the second reference sampling value is compared with a first reference sampling value collected by an ADC (analog to digital converter) channel when the key circuit is not operated, so that the error gain when the key circuit is not operated can be obtained. Subsequently, when the key circuit is operated, the actual sampling value acquired by the ADC channel can meet the error gain with the theoretical sampling value, and further the actual voltage value acquired by the ADC channel can be corrected by utilizing the error gain. The ADC key circuit calibration method provided by the embodiment of the invention effectively solves the problem of reduced ADC identification precision, can greatly prolong the service life of the key circuit, and is suitable for industrial popularization.
According to some embodiments of the invention, said calculating an error gain from said first and second reference sample values comprises the steps of: and calculating the ratio of the first reference sampling value to the second reference sampling value, and recording the ratio as the error gain.
According to some embodiments of the invention, the voltage division reference circuit comprises a pull-up resistor and a pull-down resistor; one end of the pull-up resistor is connected with the output port of the ADC, and the other end of the pull-up resistor is connected with a working voltage; one end of the pull-down resistor is connected with the ADC output port, and the other end of the pull-down resistor is connected with a ground wire.
According to some embodiments of the invention, the second reference sample value is calculated according to a voltage division reference circuit, comprising the steps of:
calculating a second reference voltage of the ADC output port when the key circuit is not operated according to the resistance value of the pull-up resistor, the resistance value of the pull-down resistor and the working voltage;
confirming a maximum ADC reading value of an ADC channel and a reference voltage of the ADC channel;
and calculating the second reference sampling value according to the ratio of the second reference voltage to the reference voltage and the maximum ADC reading value of the ADC channel.
According to some embodiments of the present invention, the correcting the actual key voltage output from the output port of the ADC by using the error gain comprises:
acquiring an actual ADC reading value corresponding to the actual key voltage;
correcting the actual ADC reading value by using the error gain, and recording the corrected actual ADC reading value as a corrected ADC reading value;
and calculating the key calibration voltage by using the corrected ADC reading value, the maximum ADC reading value and the reference voltage.
According to the second aspect of the invention, the ADC keying circuit calibration system comprises:
the device comprises a reference sampling value acquisition module, a first reference sampling value acquisition module and a second reference sampling value acquisition module, wherein the reference sampling value acquisition module is used for acquiring a first reference sampling value corresponding to a first reference voltage actually output by an ADC (analog to digital converter) output port of a key circuit when the key circuit is not operated;
the gain calculation module is used for calculating error gain according to the first reference sampling value and the second reference sampling value, the second reference sampling value is obtained by calculation according to a voltage division reference circuit, and the voltage division reference circuit is arranged at an ADC output port of the key circuit;
and the correction module is used for correcting the actual key voltage output by the ADC output port by using the error gain so as to obtain a key calibration voltage, wherein the actual key voltage is generated during key operation in the key circuit.
The ADC key circuit calibration system provided by the embodiment of the invention at least has the following technical effects: the reference sampling value acquisition module can acquire a first reference sampling value when the key circuit is not operated; the gain calculation module can calculate a second reference sampling value when the key circuit is not operated by using the voltage division reference circuit, and then can obtain the error gain when the key circuit is not operated by comparing the second reference sampling value with the first reference sampling value. Subsequently, when the key circuit is operated, the actual sampling value collected by the ADC channel can meet the error gain with the theoretical sampling value, and then the correction module can correct the actual voltage value collected by the ADC channel by using the error gain. The ADC key circuit calibration system effectively solves the problem of reduced ADC identification precision, can greatly prolong the service life of the key circuit, and is suitable for industrial popularization.
According to some embodiments of the invention, the voltage division reference circuit comprises a pull-up resistor and a pull-down resistor; one end of the pull-up resistor is connected with the output port of the ADC, and the other end of the pull-up resistor is connected with a working voltage; one end of the pull-down resistor is connected with the ADC output port, and the other end of the pull-down resistor is connected with a ground wire.
The ADC key circuit according to the third aspect of the invention comprises a key circuit, the above key circuit calibration system, and a voltage division reference circuit disposed at an ADC output port of the key circuit, wherein the voltage division reference circuit is used to assist in correcting an actual key voltage output by the ADC output port.
The ADC keying circuit according to the embodiment of the invention at least has the following technical effects: the second reference sampling value when the key circuit is not operated can be calculated by utilizing the voltage division reference circuit, and then the error gain when the key circuit is not operated can be obtained by comparing the second reference sampling value with the first reference sampling value when the key circuit is not operated. And when the key circuit is operated subsequently, the actual voltage value collected by the ADC channel can be corrected by utilizing the error gain. The ADC key circuit provided by the embodiment of the invention effectively solves the problem of reduced ADC identification precision, greatly prolongs the service life and is suitable for industrial popularization.
According to some embodiments of the invention, the voltage division reference circuit comprises a pull-up resistor and a pull-down resistor; one end of the pull-up resistor is connected with the output port of the ADC, and the other end of the pull-up resistor is connected with a working voltage; one end of the pull-down resistor is connected with the ADC output port, and the other end of the pull-down resistor is connected with a ground wire.
According to a fourth aspect of the invention, a computer-readable storage medium stores computer-executable instructions for causing a computer to perform the ADC key circuit calibration method described above.
The computer-readable storage medium according to the embodiment of the invention has at least the following advantages: storage and transfer of computer-executable instructions may be facilitated by a storage medium.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a simplified flowchart of an ADC key circuit calibration method according to an embodiment of the present invention;
FIG. 2 is a block diagram of an ADC keying circuit calibration system according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an ADC keying circuit according to an embodiment of the invention.
Reference numerals:
the reference circuit 100 is divided.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, it is to be understood that the directional descriptions, such as the directions of upper, lower, front, rear, left, right, etc., are merely provided to facilitate the description of the present invention and to simplify the description, and are not intended to indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present invention.
In the description of the present invention, a plurality of means is one or more, a plurality of means is two or more, and greater than, less than, more than, etc. are understood as excluding the essential numbers, and greater than, less than, etc. are understood as including the essential numbers. If there is a description of first and second for the purpose of distinguishing technical features only, this is not to be understood as indicating or implying a relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of technical features indicated.
In the description of the present invention, unless otherwise specifically limited, terms such as set, installation, connection and the like should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention by combining the specific contents of the technical solutions.
An ADC key circuit calibration method according to an embodiment of the first aspect of the invention is described below with reference to fig. 1 to 3.
The ADC key circuit calibration method provided by the embodiment of the invention comprises the following steps:
acquiring a first reference sampling value corresponding to a first reference voltage actually output by an ADC output port of the key circuit when the key circuit is not operated;
calculating error gain according to the first reference sampling value and the second reference sampling value, wherein the second reference sampling value is calculated according to the voltage division reference circuit 100, and the voltage division reference circuit 100 is arranged at an ADC output port of the key circuit;
and correcting the actual key voltage output by the output port of the ADC by using the error gain to obtain a key calibration voltage, wherein the actual key voltage is generated during key operation in the key circuit.
Referring to fig. 1 to 3, the voltage division reference circuit 100 is disposed at an ADC output port of the key circuit, and the ADC output port is connected to an ADC channel through which an input voltage signal is collected. When the key circuit is not operated, only the first reference voltage generated by the voltage division reference circuit 100 is input to the ADC channel, and the first reference voltage is collected by the ADC channel and converted into the first reference sampling value. After the voltage dividing reference circuit 100 is determined, a theoretical voltage value (i.e., a second reference voltage) at the output port of the ADC may be calculated by using the operating voltage and a specific resistance relationship in the voltage dividing reference circuit 100, and the reference voltage of the ADC channel and the maximum ADC reading value corresponding to the reference voltage may be predetermined, so that a theoretical reading value (i.e., a second reference sampling value) of the second reference strip voltage value may be determined by using a proportional relationship between the second reference strip voltage value and the reference voltage.
When the ADC channel and the key circuit are completely normal, the first reference sample value and the second reference sample value should be the same, but once the ADC channel or the key circuit has an error or a change, the first reference sample value read by the ADC channel inevitably changes. At this time, the specific change rule, that is, the error gain, can be determined by using the first reference sample value and the second reference sample value. After the key operation, the actual key voltage can be corrected by using the error gain to obtain the key calibration voltage.
According to the calibration method of the ADC key circuit provided by the embodiment of the invention, the voltage division reference circuit 100 can be used for calculating the second reference sampling value when the key circuit is not operated, and then the second reference sampling value is compared with the first reference sampling value collected by the ADC channel when the key circuit is not operated, so that the error gain when the key circuit is not operated can be obtained. When the key circuit is operated subsequently, the actual sampling value collected by the ADC channel can certainly meet the error gain as well as the theoretical sampling value, and further, the actual voltage value collected by the ADC channel can be corrected by utilizing the error gain. The ADC key circuit calibration method provided by the embodiment of the invention effectively solves the problem of reduced ADC identification precision, can greatly prolong the service life of the key circuit, and is suitable for industrial popularization.
In some embodiments of the invention, calculating an error gain from the first reference sample value and the second reference sample value comprises the steps of: the ratio of the first reference sample value to the second reference sample value is calculated and recorded as the error gain. The error gain can be determined by directly calculating the ratio of the first reference sample value to the second reference sample value for one hundred years, and then the actual key voltage can be corrected by using the error gain.
In some embodiments of the present invention, the voltage divider reference circuit 100 includes a pull-up resistor R23 and a pull-down resistor R21; one end of a pull-up resistor R23 is connected with the output port of the ADC, and the other end of the pull-up resistor R23 is used for connecting working voltage; one end of the pull-down resistor R21 is connected with the output port of the ADC, and the other end of the pull-down resistor R21 is connected with the ground wire. A voltage division circuit composed of the pull-up resistor R23 and the pull-down resistor R21 can be used as the voltage division reference circuit 100, and the theoretical voltage value of the ADC output port, that is, the second reference voltage, can be calculated through the pull-up resistor R23, the pull-down resistor R21 and the working voltage. Briefly, taking the example that the pull-up resistor R23 is 15K, the pull-down resistor R21 is 20K, and the operating voltage is 3.3V, the second reference voltage at the output port of the ADC is (20/(15+20)) × 3.3V — 1.89V.
In some embodiments of the present invention, the second reference sample value is calculated according to the voltage division reference circuit 100, and the method comprises the following steps:
calculating a second reference voltage of the ADC output port when the key circuit is not operated according to the resistance value of the pull-up resistor R23, the resistance value of the pull-down resistor R21 and the working voltage;
confirming a maximum ADC reading value of an ADC channel and a reference voltage of the ADC channel;
and calculating a second reference sampling value according to the ratio of the second reference voltage to the reference voltage and the maximum ADC reading value of the ADC channel.
The pull-up resistor R23 and the pull-down resistor R21 form a voltage division circuit, and then the second reference voltage at the joint of the two resistors can be directly calculated by using the working voltage. After the entire key circuit is determined, the maximum ADC reading value for the ADC channel and the reference voltage corresponding to the maximum ADC reading value may be determined. A proportional relationship can be calculated using the second reference voltage and the reference voltage, and the maximum ADC reading value and the second reference sample value correspond to the reference voltage and the second reference voltage, respectively, so that the proportional relationship can be directly used to calculate the second reference sample value.
In some embodiments of the present invention, the correcting the actual key voltage output from the output port of the ADC by using the error gain comprises:
Acquiring an actual ADC reading value corresponding to the actual key voltage;
correcting the actual ADC reading value by using the error gain, and recording the corrected actual ADC reading value as a corrected ADC reading value;
and calculating the key calibration voltage by using the corrected ADC reading value, the maximum ADC reading value and the reference voltage.
When the actual key voltage is corrected by the error gain, the actual key voltage is not directly corrected. After the actual key voltage enters the ADC channel, the actual key voltage is converted into an actual ADC reading value corresponding to the actual key voltage, the actual ADC reading value is corrected by using error gain to obtain a corrected ADC reading value, and the key calibration voltage corresponding to the corrected ADC reading value can be reversely calculated by using the proportional relation between the corrected ADC reading value and the maximum ADC reading value and the corresponding relation between the maximum ADC reading value and the reference voltage.
To better illustrate the principles, a minimum embodiment is illustrated.
Assuming that the first reference sample value is NdefaultSecond reference sample value is Nref，ADC channel maximum ADC reading value is NmaxThe reference voltage of the ADC is 2V, and the actual ADC reading value of the ADC channel is NkeyThe corrected key calibration voltage is V tranAnd the error gain is delta, then:
Δ＝Ndefault/Nref
Vtran＝((Nkey/Nmax)/Δ)*Vref
the above calculation formula is used here to further explain by taking 8-bit ADC, ADC reference voltage 2V, operating voltage 3.3V, pull-up resistor 15K, and pull-down resistor R21 20K as examples. The second reference voltage is 1.89V calculated by the working voltage, the pull-up resistor R23 and the pull-down resistor R21, and then N is further calculatedrefAt 242, assume that N can be read when the key circuit is not operatingdefaultTo 230, then according to the formula Δ ═ Ndefault/NrefThe error gain Δ may be calculated as 230/242-0.95.
When the key circuit is not operated, the actual ADC reading value read by the ADC channel is 208, and then the formula V is usedtran＝((Nkey/Nmax)/Δ)*VrefThe calibration voltage V of the key can be calculatedtranIt was 208/256/0.95 × 2.0V, i.e. 1.71V. Also, using this principle, the key calibration voltage can be calculated using the actual ADC reading value and error gain for each key.
The ADC key circuit calibration system according to the embodiment of the second aspect of the invention comprises a reference sampling value acquisition module, a gain calculation module and a correction module.
The device comprises a reference sampling value acquisition module, a first reference sampling value acquisition module and a second reference sampling value acquisition module, wherein the reference sampling value acquisition module is used for acquiring a first reference sampling value corresponding to a first reference voltage actually output by an ADC (analog to digital converter) output port of a key circuit when the key circuit is not operated;
The gain calculation module is used for calculating error gain according to the first reference sampling value and the second reference sampling value, the second reference sampling value is calculated according to the voltage division reference circuit 100, and the voltage division reference circuit 100 is arranged at an ADC output port of the key circuit;
and the correction module is used for correcting the actual key voltage output by the ADC output port by using the error gain to obtain a key calibration voltage, and the actual key voltage is generated during key operation in the key circuit.
Referring to fig. 1 to 3, the voltage division reference circuit 100 is disposed at an ADC output port of the key circuit, and the ADC output port is connected to an ADC channel through which an input voltage signal is collected. When the key circuit is not operated, only the first reference voltage generated by the voltage division reference circuit 100 is input to the ADC channel, and after the ADC channel collects the first reference voltage, the first reference voltage is converted into a first reference sampling value, and the reference sampling value acquisition module may acquire the first reference sampling value. After the voltage dividing reference circuit 100 is determined, a theoretical voltage value (i.e., a second reference voltage) at the output port of the ADC may be calculated by using the operating voltage and a specific resistance relationship in the voltage dividing reference circuit 100, and the reference voltage of the ADC channel and the maximum ADC reading value corresponding to the reference voltage may be predetermined, so that a theoretical reading value (i.e., a second reference sampling value) of the second reference strip voltage value may be determined by using a proportional relationship between the second reference strip voltage value and the reference voltage.
When the ADC channel and the key circuit are completely normal, the first reference sample value and the second reference sample value should be the same, but once the ADC channel or the key circuit has an error or a change, the first reference sample value read by the ADC channel inevitably changes. At this time, the gain calculation module can determine a specific change rule by using the first reference sampling value and the second reference sampling value, and further calculate the error gain. After the subsequent key operation, the correction module can correct the actual key voltage by using the error gain to obtain the key calibration voltage.
According to the ADC key circuit calibration system provided by the embodiment of the invention, the reference sampling value acquisition module can acquire a first reference sampling value when the key circuit is not operated; the gain calculation module may calculate a second reference sample value when the key circuit is not operated by using the voltage division reference circuit 100, and then may obtain an error gain when the key circuit is not operated by comparing the second reference sample value with the first reference sample value. When the key circuit is operated subsequently, the actual sampling value collected by the ADC channel can certainly meet the error gain as well as the theoretical sampling value, and then the correction module can correct the actual voltage value collected by the ADC channel by using the error gain. The ADC key circuit calibration system effectively solves the problem of reduced ADC identification precision, can greatly prolong the service life of the key circuit, and is suitable for industrial popularization.
In some embodiments of the present invention, the voltage division reference circuit 100 includes a pull-up resistor R23 and a pull-down resistor R21; one end of a pull-up resistor R23 is connected with the output port of the ADC, and the other end of the pull-up resistor R23 is used for connecting working voltage; one end of the pull-down resistor R21 is connected with the output port of the ADC, and the other end of the pull-down resistor R21 is connected with the ground wire. A voltage division circuit consisting of the pull-up resistor R23 and the pull-down resistor R21 can be used as a voltage division reference circuit 100, and the theoretical voltage value of the ADC output port can be calculated through the pull-up resistor R23, the pull-down resistor R21 and the working voltage. Briefly, taking the example that the pull-up resistor R23 is 15K, the pull-down resistor R21 is 20K, and the operating voltage is 3.3V, the second reference voltage at the output port of the ADC is (20/(15+20)) × 3.3V — 1.89V.
The ADC key circuit according to the third aspect of the invention includes a key circuit, the above key circuit calibration system, and a voltage division reference circuit 100 disposed at an ADC output port of the key circuit, where the voltage division reference circuit 100 is used to assist in correcting an actual key voltage output by the ADC output port.
According to the ADC key circuit of the embodiment of the present invention, the voltage-dividing reference circuit 100 may calculate the second reference sampling value when the key circuit is not operated, and then compare the second reference sampling value with the first reference sampling value when the key circuit is not operated, so as to obtain the error gain when the key circuit is not operated. And when the key circuit is operated subsequently, the error gain can be utilized to correct the actual voltage value acquired by the ADC channel. The ADC key circuit provided by the embodiment of the invention effectively solves the problem of reduced ADC identification precision, greatly prolongs the service life, and is suitable for industrial popularization.
In addition, referring to fig. 3, a brief description is given of a key circuit to which the voltage division reference circuit 100 in the embodiment of the present invention is added.
In fig. 3, the key circuit includes a plurality of keys connected in parallel, each key is connected with a voltage divider resistor in series, the resistance of the voltage divider resistor connected in series with each key is different, the voltage divider resistor and the key connected in series are connected between the ground line and the input port of the ADC channel, and the connection point of the input port of the series structure and the ADC channel is the output port of the ADC. The voltage division reference circuit 100 comprises a pull-up resistor R23 and a pull-down resistor R21 which are connected in series, wherein one end, far away from the pull-down resistor R21, of the pull-up resistor R23 is connected with a working voltage, one end, far away from the pull-up resistor R23, of the pull-down resistor R21 is connected with a ground wire, and a common point of the pull-up resistor R23 and the pull-down resistor R21 is connected to an input port of an ADC channel. Because the working voltage exists and the resistance value of each divider resistor is different, different voltage values can be obtained at the output port of the ADC after different keys in the key circuit are pressed, and different actual ADC reading values can be obtained after the working voltage is input into an ADC channel.
In some embodiments of the present invention, the voltage division reference circuit 100 includes a pull-up resistor R23 and a pull-down resistor R21; one end of a pull-up resistor R23 is connected with the output port of the ADC, and the other end of the pull-up resistor R23 is used for connecting working voltage; one end of the pull-down resistor R21 is connected with the output port of the ADC, and the other end of the pull-down resistor R21 is connected with the ground wire. A voltage division circuit consisting of the pull-up resistor R23 and the pull-down resistor R21 can be used as a voltage division reference circuit 100, and the theoretical voltage value of the ADC output port can be calculated through the pull-up resistor R23, the pull-down resistor R21 and the working voltage. Briefly, taking the example that the pull-up resistor R23 is 15K, the pull-down resistor R21 is 20K, and the operating voltage is 3.3V, the second reference voltage at the output port of the ADC is (20/(15+20)) × 3.3V — 1.89V.
A storage medium according to an embodiment of a fourth aspect of the invention includes: DDR and the ADC keying circuit calibration system. And the ADC key circuit calibration system is connected with the DDR controller through a DFI interface.
According to the storage medium provided by the embodiment of the invention, by adding the ADC key circuit calibration system on the original DDR, errors caused by factors such as process, temperature and voltage can be effectively eliminated, and dynamic compensation is realized.
According to a fourth aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions for causing a computer to perform the ADC key circuit calibration method described above.
Computer-readable storage media according to embodiments of the present invention may facilitate storage and transfer of computer-executable instructions by the storage media.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although the embodiments of the present invention have been described in detail, the present invention is not limited to the embodiments, and those skilled in the art can understand that: various changes, modifications, substitutions and alterations can be made to the embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.
Claims (6)
1. An ADC key circuit calibration method is characterized by comprising the following steps:
acquiring a first reference sampling value corresponding to a first reference voltage actually output by an ADC output port of the key circuit when the key circuit is not operated;
calculating error gain according to the first reference sampling value and a second reference sampling value, wherein the second reference sampling value is obtained by calculation according to a voltage division reference circuit which is arranged at an ADC output port of the key circuit; the voltage division reference circuit comprises a pull-up resistor and a pull-down resistor; one end of the pull-up resistor is connected with the output port of the ADC, and the other end of the pull-up resistor is connected with a working voltage; one end of the pull-down resistor is connected with the ADC output port, and the other end of the pull-down resistor is connected with a ground wire;
correcting the actual key voltage output by the ADC output port by using the error gain to obtain a key calibration voltage, wherein the actual key voltage is generated during key operation in the key circuit;
The second reference sampling value is calculated according to a voltage division reference circuit, and the method comprises the following steps of:
calculating a second reference voltage of the ADC output port when the key circuit is not operated according to the resistance value of the pull-up resistor, the resistance value of the pull-down resistor and the working voltage;
confirming a maximum ADC reading value of an ADC channel and a reference voltage of the ADC channel;
and calculating the second reference sampling value according to the ratio of the second reference voltage to the reference voltage and the maximum ADC reading value of the ADC channel.
2. The ADC keying circuit calibration method of claim 1, wherein said calculating an error gain based on said first and second reference sample values comprises the steps of: the ratio of the first and second reference sample values is calculated and this ratio is taken as the error gain.
3. The ADC keying circuit calibration method of claim 1, wherein said correcting an actual key voltage output from said ADC output port by using said error gain comprises:
acquiring an actual ADC reading value corresponding to the actual key voltage;
Correcting the actual ADC reading value by using the error gain, and recording the corrected actual ADC reading value as a corrected ADC reading value;
and calculating the key calibration voltage by using the corrected ADC reading value, the maximum ADC reading value and the reference voltage.
4. An ADC keying circuit calibration system, comprising:
the key circuit comprises a reference sampling value acquisition module, a first voltage reference acquisition module and a second voltage reference acquisition module, wherein the reference sampling value acquisition module is used for acquiring a first reference sampling value corresponding to a first reference voltage actually output by an ADC (analog to digital converter) output port of the key circuit when the key circuit is not operated;
the gain calculation module is used for calculating error gain according to the first reference sampling value and the second reference sampling value, the second reference sampling value is obtained by calculation according to a voltage division reference circuit, and the voltage division reference circuit is arranged at an ADC output port of the key circuit; the voltage division reference circuit comprises a pull-up resistor and a pull-down resistor; one end of the pull-up resistor is connected with the output port of the ADC, and the other end of the pull-up resistor is connected with a working voltage; one end of the pull-down resistor is connected with the ADC output port, and the other end of the pull-down resistor is connected with a ground wire;
the correction module is used for correcting the actual key voltage output by the ADC output port by using the error gain to obtain a key calibration voltage, and the actual key voltage is generated during key operation in the key circuit;
The second reference sampling value is calculated according to the voltage division reference circuit, and the method comprises the following steps:
calculating a second reference voltage of the ADC output port when the key circuit is not operated according to the resistance value of the pull-up resistor, the resistance value of the pull-down resistor and the working voltage;
confirming a maximum ADC reading value of an ADC channel and a reference voltage of the ADC channel;
and calculating the second reference sampling value according to the ratio of the second reference voltage to the reference voltage and the maximum ADC reading value of the ADC channel.
5. An ADC key circuit, comprising a key circuit, the key circuit calibration system of claim 4, and a voltage division reference circuit disposed at an ADC output port of the key circuit, wherein the voltage division reference circuit is used for assisting in correcting an actual key voltage output from the ADC output port.
6. A computer-readable storage medium characterized by: the computer-readable storage medium stores computer-executable instructions for causing a computer to perform a method of ADC key circuit calibration as claimed in any one of claims 1 to 3.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110827886.7A CN113612478B (en) | 2021-07-22 | 2021-07-22 | ADC key circuit calibration method, system, storage medium and key circuit |
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| CN203984397U (en) * | 2014-07-04 | 2014-12-03 | 深圳市普兰电子技术有限公司 | A kind of calibration circuit of new A DC key scanning circuit |
| CN105577189B (en) * | 2015-12-16 | 2019-09-27 | 上海移为通信技术股份有限公司 | A kind of high-precision adc calibration method |
| CN109799919A (en) * | 2018-12-25 | 2019-05-24 | 珠海慧联科技有限公司 | A kind of single channel ADC realizes the method and device of key and knob |
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