CN113609808A - PCIExpress signal integrity improvement method for navigation display system - Google Patents
PCIExpress signal integrity improvement method for navigation display system Download PDFInfo
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Abstract
The invention discloses a method for improving the integrity of a PCI express signal of a navigation display system. The method for improving the integrity of the PCI express signal of the navigation display system comprises the steps of setting simulation parameters of a circuit board in the navigation display system to set the characteristic impedance of the PCB of the circuit board, performing crosstalk noise simulation on the circuit board of the navigation display system after the simulation parameters are set to obtain the coupling length and the distance between the differential transmission lines, and performing channel analysis simulation on the circuit board of the navigation display system with the obtained coupling length and the obtained distance between the differential transmission lines to improve the integrity of the PCI express signal. The method for improving the integrity of the PCI express signal of the navigation display system ensures the quality of the signal in the circuit system by using a simulation analysis method, greatly improves the design efficiency, reduces the cost and realizes the aim of correct design.
Description
Technical Field
The invention relates to the technical field of high-speed circuit design, in particular to a PCI express signal integrity improvement method of a navigation display system.
Background
The navigation display system requires that the navigation display system has higher rapidity and accuracy for real-time data transmission than general requirements, the data can be transmitted quickly and accurately, and the pci express bus can well solve the problems. However, since the signal transmission rate can reach 5Gb/s, the increase of the operating frequency and the increase of the bus bandwidth bring many problems that the space limitation of the PCB, the signal noise, the signal integrity and the avoidance of signal interference, the wiring length, the setup and hold time in the system timing sequence, and the electromagnetic radiation (EMI) do not meet the design requirements.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a pci express signal integrity improving method for a navigation display system, which is used to solve the problems that the increase of the operating frequency and the increase of the bus bandwidth in the prior art inevitably bring about the space limitation of the PCB, the signal noise, the signal integrity and the avoidance of signal mutual interference, the wiring length, the setup and hold time in the system timing sequence, and the electromagnetic radiation (EMI) that do not meet the design requirements.
To achieve the above and other related objects, the present invention provides a pci express signal integrity improving method for a navigation display system, including:
s1, setting simulation parameters of a circuit board in the navigation display system to set PCB characteristic impedance of the circuit board;
s2, performing crosstalk noise simulation on the circuit board of the navigation display system after simulation parameter setting to obtain the coupling length and the distance between the differential transmission lines;
and S3, performing channel analysis simulation on the circuit board of the navigation display system with the coupling length and the distance between the differential transmission lines, so as to improve the integrity of the PCI express signal.
In an embodiment of the present invention, the setting of the simulation parameters of the circuit board in the navigation display system in step S1 refers to setting the characteristic impedance of the PCB according to the laminated structure and the filling material of the circuit board.
In an embodiment of the present invention, the step of performing crosstalk noise simulation on the circuit board of the navigation display system after the simulation parameter setting is performed to obtain the coupling length and the distance between the differential transmission lines includes:
constructing three differential pairs under the coupling of adjacent transmission lines, wherein the middle differential pair is used as an attacked network, and the two differential pairs at the two sides are used as attacking networks;
setting transmission rate under transmission line coupling to obtain the size of crosstalk noise of an attacked network;
the attacked network is subjected to crosstalk noise to determine the coupling length and spacing between differential transmission lines.
In an embodiment of the present invention, the step of performing channel analysis simulation on the circuit board of the navigation display system, on which the coupling length and the distance between the differential transmission lines are obtained, to improve the integrity of the pci express signal includes:
channel analysis simulation is carried out by utilizing a pre-emphasis technology to obtain parameters of an eye pattern of a signal received by a receiving end in a circuit board from a transmitting end;
parameters of an eye diagram of a signal are made to meet index requirements of pci express industry specifications to improve the integrity of pci express signals.
In an embodiment of the present invention, the laminated structure includes a number of layers of a circuit board, and the number of layers of the circuit board is divided into a first layer wiring layer, a bottom layer wiring layer, a ground layer, and a power supply layer.
In an embodiment of the present invention, the filling material is FR-4 material.
As described above, the pci express signal integrity improving method of the navigation display system of the present invention has the following beneficial effects:
the PCI express signal integrity improvement method of the navigation display system avoids the problems of space limitation of a PCB, signal noise, signal integrity and signal mutual interference caused by the improvement of working frequency and the increase of bus bandwidth, and the wiring length, the establishment and maintenance time in the system time sequence and the electromagnetic radiation (EMI) meet the design.
The method for improving the integrity of the PCI express signal of the navigation display system ensures the quality of the signal in the circuit system by using a simulation analysis method, greatly improves the design efficiency, reduces the cost and realizes the aim of correct design.
Drawings
Fig. 1 is a schematic structural diagram of a pci express signal integrity improvement method for a navigation display system according to an embodiment of the present application.
Fig. 2 is a topology structure diagram of a pci express bus link according to an embodiment of the present disclosure.
Fig. 3 is a page diagram of setting the characteristic impedance of the PCB according to the embodiment of the present application.
Fig. 4 is a topological structure diagram of a crosstalk simulation model provided in an embodiment of the present application.
Fig. 5 is a setting page diagram of a crosstalk transmission line model provided in an embodiment of the present application.
Fig. 6 is a diagram of a simulation result of crosstalk noise according to an embodiment of the present application.
Fig. 7 is a diagram of simulation results of crosstalk noise according to an embodiment of the present application.
Fig. 8 is a diagram of simulation results of crosstalk noise according to an embodiment of the present application.
Fig. 9 is a diagram of simulation results of crosstalk noise according to an embodiment of the present application.
Fig. 10 is a simulation report diagram provided in an embodiment of the present application.
Fig. 11 is a simulation report diagram provided in an embodiment of the present application.
Fig. 12 is a simulated eye diagram provided in an embodiment of the present application.
Fig. 13 is a diagram of signal overshoot values provided in an embodiment of the present application.
Fig. 14 is a technical parameter index diagram provided in an embodiment of the present application.
Fig. 15 is a technical parameter index diagram provided in an embodiment of the present application.
Fig. 16 is a technical parameter index diagram provided in an embodiment of the present application.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a pci express signal integrity improvement method for a navigation display system according to an embodiment of the present disclosure. The invention provides a method for improving the integrity of a PCI express signal of a navigation display system, which comprises the following steps: s1, setting simulation parameters of a circuit board in the navigation display system to set PCB characteristic impedance of the circuit board; s2, performing crosstalk noise simulation on the circuit board of the navigation display system after simulation parameter setting to obtain the coupling length and the distance between the differential transmission lines; and S3, performing channel analysis simulation on the circuit board of the navigation display system with the coupling length and the distance between the differential transmission lines, so as to improve the integrity of the PCI express signal. PCI express is a high speed serial computer bus that replaces the older PCI standard.
Referring to fig. 14 and fig. 15, the PCI express signal integrity improvement method of the navigation display system of the present invention utilizes PCI express industrial specification of PCI express-SIG as a design index, and uses a simulation result obtained by a Cadence simulation platform as a specific test form to solve the problem of signal integrity of a PCI express transmission link, so as to solve the problems that in the traditional PCB design, the quality of a signal cannot be guaranteed and the design efficiency is low, and the simulation process can be divided into:
(1) according to PCI express signal specification and definition of PCI-SIG, a PCI express data link is composed of two differential signal pairs (LVDS, 4 in total) with opposite transmission directions, each path is transmitted (Tx) and received (Rx), and PCI express realizes full duplex on the same data line by mixing flow control information required by one path of data with data transmitted in reverse direction. The characteristic impedance of the PCB is set according to the actual PCB laminated structure and the filling material, so that impedance matching in the transmission process is ensured, and signal reflection is eliminated.
(2) Establishing a channel crosstalk analysis model, setting the coupling length and the coupling distance between adjacent transmission links, obtaining the crosstalk noise size under different coupling lengths and distances through simulation analysis, and generating an optimal wiring rule by combining design indexes given by PCIExpress industrial specifications so that the noise size between signals after wiring can meet the requirement of crosstalk noise index. Through crosstalk simulation analysis, the optimal coupling length and coupling distance of the transmission line are determined, and crosstalk noise is greatly reduced and is improved by about 20% compared with the specified indexes.
(3) Aiming at the problem that signals are attenuated due to skin effect and dielectric loss of the signals under high-frequency transmission, a pre-emphasis technology is adopted, and parameter indexes in an eye pattern obtained through simulation are compared with technical indexes of PCIExpress industrial specifications, so that the eye pattern obtained through final simulation meets the index requirements. Through channel analysis simulation, the eye width, the eye height and the system jitter of the eye pattern all meet the specified index requirements.
The content of the pci express signal integrity improvement method of the navigation display system of the present invention is described in more detail below:
(1) firstly, planning and designing a path of a whole system signal, finishing drawing a schematic diagram and finishing primary PCB layout.
(2) And carrying out grammar detection on the IBIS model of the FPGA chip required by simulation and converting the IBIS model into a DML model.
(3) As shown in fig. 2, the topology structure of the pci express signal transmission path is extracted, and fig. 2 is composed of a driving end, a transmission line, a via hole, a connector, and a receiver.
(4) As shown in fig. 3, the PCBs are stacked, layer levels including the material, type, name, thickness, line width, and impedance information of each layer are determined, a dielectric constant value is set to 4.5, a loss factor value is 0.035, a material is FR-4, a line width of a differential pair is 5mil, a differential pitch is 6mil, and a characteristic impedance value at this time is 99.814 Ω, which reaches a predetermined 100 Ω value. The following explains the english language in fig. 3: layout cross section represents a lamination setup, subcategory Name represents a subcategory Name, TOP represents a TOP layer, GND represents a ground layer, VCC represents a power layer, SURFACE represents a SURFACE, DIEECTRIC represents a Dielectric, plane represents a power plane, connector represents a wiring layer, Thickness represents Thickness, Dielectric Constant represents a Dielectric Constant, Loss value represents a Loss Factor, Width represents a Width, neutral arm represents a restoration work, shield represents protection, Etch Factor represents a corrosion coefficient, Impedance represents Impedance, Coupling Type represents a Coupling Type, spacing represents a pitch, diffz0 represents a differential Impedance, total Thickness represents a total Thickness, layer Type represents a layer Type, and material represents a material.
(5) As shown in fig. 4, a channel crosstalk analysis model is established. In the middle of fig. 4, there is an attacked network, and on the adjacent two sides, there are attacking networks for crosstalk noise simulation.
(6) As shown in fig. 5, parameters of the coupling length and the coupling distance of the transmission line are set, and the crosstalk noise is obtained through simulation. The fixed coupling spacing was 5 mils, the start value of the coupling length was 8000 mils, the step value was 2000 mils, and the stop value was 16000 mils, and the simulation results are shown in FIG. 6. The fixed coupling spacing was 8 mils, the start value of the coupling length was 8000 mils, the step value was 2000 mils, and the stop value was 16000 mils, and the simulation results are shown in FIG. 7. The fixed coupling spacing was 12 mils, the start value of the coupling length was 8000 mils, the step value was 2000 mils, and the end value was 16000 mils, and the simulation results are shown in FIG. 8. The fixed coupling length was 10000 mils, the start of the coupling pitch was set to 5 mils, the step was 1mil, and the stop was 12 mils, and the simulation results are shown in FIG. 9. The size of crosstalk noise needs to be lower than that given by the pci express industry specification, the coupling distance between the differential pairs is set to be 8 mils, the coupling length does not exceed 12000 mils, the maximum crosstalk noise is 32.09mV, and the crosstalk noise is improved by about 20% compared with the index requirement. The following explains english in fig. 5 and 9: parameter values denote parameter values, length denotes a line length, S3, S5 denotes a spacing between a pair of transmission lines in a single differential line, S2, S4 denotes a spacing between bit-coupled differential pairs (i.e., for pairs), W denotes a line width, T denotes a thickness of the line, D1, D2 denotes a thickness of a dielectric layer, matrix denotes a matrix, and impedance denotes impedance. Driver denotes a Driver, i.e., a transmitting end, Receiver denotes a Receiver, i.e., a receiving end, FTSMode denotes a signal mode, fast, ms1.tracewidth3 and ms1.tracewidth2 denote widths of two differential lines in a differential transmission line, ms1.spacing denotes a coupling pitch of adjacent differential transmission lines, and ms1.length denotes a coupling length.
(7) And through the previous steps, the quality of the signal is improved well, and then the channel analysis simulation is carried out. The pre-emphasis is set as a default setting, a corresponding eye diagram is obtained through simulation, and a simulation report is shown in fig. 10, wherein the eye width of the eye diagram is 256ps, 160ps which exceeds the index requirement is obtained, and the performance is improved by 60%. The height of the eye pattern is 242mV, which exceeds 175mV required by the index, and the performance is improved by 38.2%. The signal jitter is 144ps to 0.36UI, which is lower than the index of 0.6UI, and the performance is improved by 40%. The pre-emphasis level is set to 3 and the re-simulation is shown in fig. 11. The simulation report is shown in fig. 11, in which the eye width of the eye diagram is 352ps, which exceeds 160ps required by the index, and the performance is improved by 120%. The height of the eye pattern is 487mV, which exceeds 175mV required by the index, and the performance is improved by 178%. The signal jitter is 48ps to 0.12UI, which is lower than the index of 0.6UI, and the performance is improved by 80%. The eye height and width were significantly increased compared to the eye pattern before and after pre-emphasis as shown in fig. 12. The low-level overshoot of the signal has a value of-285.685 mV, the dashed line is the eye diagram before the pre-emphasis is absent, and the solid line is the eye diagram after the pre-emphasis, because the main criteria for reflecting the signal quality are the eye width and the eye height of the eye diagram, i.e. the eye heightThe width and height of the eyes, the solid lines, are significantly larger than the dashed lines. As shown in fig. 13, there is no high level overshoot, which meets the requirement of the index and improves the performance by 52.3%. As shown in fig. 12, glotch represents Glitch, show pass, noismergin represents noise margin, Overshoothigh represents high level overshoot, no high level overshoot, Overshootlow represents low level overshoot value of-285.685 mV, Switchdelay represents switching delay, Propdelay represents front end delay, Settledelay represents settling delay. As shown in fig. 14 and 15, VRX-DIFFP-pminIndicating an eye height of greater than 175 mV. T isRX-EYE-MINThe minimum value representing the eye width is 0.4 UI.
(8) And (3) carrying out layout and wiring according to each constraint rule obtained by the previous simulation, carrying out post-simulation analysis on the PCIExpress bus link after the layout and wiring are finished, carrying out simulation according to the steps (1) to (7), observing whether the simulation result reaches a design index, and if not, adjusting the layout and wiring until the design index is reached or exceeded.
(9) And finally, defining a design constraint rule of the PCI express bus signals according to a simulation result, wherein under the design constraint rule, the reflection noise of the signals can be controlled under the minimum requirement, the crosstalk noise among the signals can be lower than a design index, an eye diagram of the signals can meet the PCI express industrial specification standard, and the problem of the integrity of the PCI express signals of the navigation display system is well solved.
The following explains english in fig. 16: the signal rate represents 2.5Gb/s, the signal UI has a value of 400ps, UI represents the width of one bit, which is the inverse of the baud rate, i.e. 1UI 1/(2.5Gb/s) 400ps, signal jitter UI-eye width, signal positive level, i.e. a value where the signal is above 0, maximum value cannot exceed 600mV, signal negative level, i.e. a value where the signal is below 0, minimum value cannot be below-600 mV, crosstalk noise cannot exceed 40mV, eye diagram width minimum value is 0.4UI, i.e. greater than or equal to 160ps, eye diagram height minimum value is 175 mV.
In summary, the pci express signal integrity improvement method of the navigation display system of the present invention avoids the problems of space limitation of the PCB, signal noise, signal integrity and mutual signal interference caused by the increase of the operating frequency and the increase of the bus bandwidth, and the wiring length, the setup and hold time in the system timing sequence and the electromagnetic radiation (EMI) satisfy the design.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (6)
1. A PCI express signal integrity improvement method of a navigation display system is characterized by comprising the following steps:
s1, setting simulation parameters of a circuit board in the navigation display system to set PCB characteristic impedance of the circuit board;
s2, performing crosstalk noise simulation on the circuit board of the navigation display system after simulation parameter setting to obtain the coupling length and the distance between the differential transmission lines;
and S3, performing channel analysis simulation on the circuit board of the navigation display system with the coupling length and the distance between the differential transmission lines, so as to improve the integrity of the PCI express signal.
2. The pci express signal integrity improvement method of claim 1, wherein: the setting of the simulation parameters for the circuit board in the navigation display system in step S1 refers to setting the characteristic impedance of the PCB according to the laminated structure and the filling material of the circuit board.
3. The pci express signal integrity improvement method of claim 1, wherein the step of performing crosstalk noise simulation on the circuit board of the navigation display system after the simulation parameter setting is performed to obtain the coupling length and the distance between the differential transmission lines comprises:
constructing three differential pairs under the coupling of adjacent transmission lines, wherein the middle differential pair is used as an attacked network, and the two differential pairs at the two sides are used as attacking networks;
setting transmission rate under transmission line coupling to obtain the size of crosstalk noise of an attacked network;
the attacked network is subjected to crosstalk noise to determine the coupling length and spacing between differential transmission lines.
4. The method of claim 1, wherein the step of performing channel analysis simulation on the circuit board of the navigable display system having obtained the coupling length and the distance between the differential transmission lines to improve the integrity of the pci express signal comprises:
channel analysis simulation is carried out by utilizing a pre-emphasis technology to obtain parameters of an eye pattern of a signal received by a receiving end in a circuit board from a transmitting end;
parameters of an eye diagram of a signal are made to meet index requirements of pci express industry specifications to improve the integrity of pci express signals.
5. The pci express signal integrity improvement method of claim 2, wherein: the laminated structure comprises the number of layers of a circuit board, and the number of layers of the circuit board is divided into a first layer wiring layer, a bottom layer wiring layer, a stratum and a power supply layer.
6. The pci express signal integrity improvement method of claim 2, wherein: the filling material is FR-4 material.
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