CN113608924A - Small satellite program control data fault-tolerant method - Google Patents
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Abstract
The invention provides a satellite program control data fault tolerance method, which comprises the following steps: s1, carrying out cyclic code encoding on the information part of each piece of program control data to obtain an error correction code of the program control data, wherein the information part of the program control data and the corresponding error correction code jointly form the program control data; s2, forming a plurality of encoded program control data into an upper injection program control frame, and injecting the upper injection program control frame to the house service center computer, wherein the upper injection program control frame comprises a synchronous word, a frame length, information parts of N pieces of program control data, an error correction code and a CRC (cyclic redundancy check) value, and N is more than or equal to 1; s3, after receiving the upper-note program control frame, the house keeping center computer judges whether the synchronous word, the frame length and the CRC check value are correct, and stores N pieces of program control data; otherwise, discarding the upper-injection program control frame; and S4, the house service center computer executes error detection and correction on each piece of stored program control data. The invention realizes the error detection and correction of the program control data without changing the original hardware structure and increasing hardware EDAC chips or FPGA.
Description
Technical Field
The invention relates to a low-cost satellite program control data error correction method which is used for detecting and correcting errors of small satellite program control data and overcoming the spatial single event effect.
Background
With the explosive growth of commercial satellite launching, the business requirements of commercial aerospace can not be met according to the traditional large satellite research and development period of 3-5 years. Aerospace-grade devices widely applied in spacecrafts are often prohibited to be transported, long in supply period, several times higher in price than COTS devices with the same functions, and 2-3 generations behind performance, so that a commercial current goods (COTS) product is adopted to replace an aerospace-grade product, and the aerospace-grade device becomes a main direction of commercial aerospace development. Commercial off-the-shelf products generally face the problem of Single Event Upset (SEU) caused by space radiation when applied to small satellites, and on-board program control data such as program control instructions, program control data blocks, relative program control instructions and stored load data need to be stored for a long time, so that the SEU resistance design is required. Currently, anti-SEU designs widely employ error detection and correction (EDAC) or Triple Modular Redundancy (TMR) techniques. The traditional EDAC technology is realized by a special hardware circuit or an FPGA chip, but the small satellite is developed based on a commercial goods shelf product system due to the requirements of small volume, light weight, low power consumption, low development cost and short period, industrial-grade components and even whole machine spot products are applied, and the method for realizing hardware EDAC by modifying the circuit and increasing the EDAC chip or the FPGA is not applicable. The TMR technology can resist SEU, but occupies 3 times of storage space of data to be protected, is often unacceptable when the data volume is large, and the 3-out-of-2 method fails due to the possible single event upset accumulation along with long-term on-track operation.
Disclosure of Invention
The technical problem solved by the invention is as follows: the method overcomes the defects of the prior art, provides a satellite program control data fault tolerance method, does not change the original hardware structure, does not need to increase hardware EDAC chips or FPGA, and realizes error detection and correction of program control data.
The technical solution of the invention is as follows: a satellite program control data fault tolerance method comprises the following steps:
s1, carrying out cyclic code encoding on the information part of each piece of program control data to obtain an error correction code of the program control data, wherein the information part of the program control data and the corresponding error correction code jointly form the program control data;
s2, forming a plurality of encoded program control data into an upper injection program control frame, and injecting the upper injection program control frame to the house service center computer, wherein the upper injection program control frame comprises a synchronous word, a frame length, information parts of N pieces of program control data, an error correction code and a CRC (cyclic redundancy check) value, and N is more than or equal to 1;
s3, after receiving the upper-note program control frame, the house keeping center computer judges whether the synchronous word, the frame length and the CRC check value are correct, and stores N pieces of program control data; otherwise, discarding the upper-injection program control frame;
and S4, the house service center computer executes error detection and correction on each piece of stored program control data.
The information part of the program control data in the step S1 includes program control commands, program control data blocks, relative program control commands, thermal control data, and load data.
The S1 is as follows: cyclic code encoding the information portion of the program-controlled data using a cyclic code generator polynomial of the order of xnAnd (c) an n-k degree polynomial selected from the factors of +1, wherein k is the length of the information part of the program control data, n is k + r, and r is the supervision bit length.
The step S1 is: j 0 bit is added to the high bit of the information part of the program control data, the bit number of the expanded program control data information part is n + j bit, a cyclic code generator polynomial is adopted, the expanded program control data information part is circularly encoded to generate (n + j, k + j) cyclic code, then the (n + j, k + j) cyclic code is shortened by j bit to obtain (n, k) shortened cyclic code, j is an integer, and the smaller the j is, the better the j is.
The S4 is executed before each piece of program control data is executed or according to a preset cycle.
The specific method of S4 is as follows:
s4.1, extracting information parts of the program control data stored in the satellite service center computer and corresponding error correcting codes of the information parts to form the program control data;
s4.2, converting the program control data into a code polynomial B (x), and dividing the code polynomial B (x) by a cyclic generation polynomial g (x) to obtain a syndrome polynomial r (x);
s4.3, if the syndrome polynomial r (x) is 0, the program control data is correct; if r (x) is not equal to 0 and there is an integer i, so that r (x) ximod (g (x)), i ═ 0,1,2, ┅ n-1, then the ith bit of the program data from low to high is erroneous, if r (x) is not equal to 0, but there is no integer i, so that r (x) ═ ximod (g(x))，i∈[0～n-1]Then it is assumed that a double bit error has occurred in the programmed data.
In the step S4.1, when n data bits of the program control data are d respectivelyn-1～d0The corresponding code polynomial B (x) is
B(x)＝dn-1xn-1+dn-2xn-2+...+d1x1+d0x0。
Compared with the prior art, the invention has the beneficial effects that:
(1) the invention can carry out error correction coding aiming at data with different lengths, and achieve the capability that the data with the length of kbit can detect multi-bit errors and correct 1-bit errors.
(2) The invention realizes the error detection and correction of the program control data through software, does not change the original hardware structure, does not need to increase a hardware EDAC chip or FPGA, and is suitable for being used by a low-cost satellite adopting a commercial goods shelf product system;
(3) compared with the triple modular redundancy method, the method occupies less memory and only needs to allocate storage space to the supervision bit.
(4) The invention adopts the data error detection task to operate periodically, can finish the error detection and correction of N pieces of program-controlled data per period, avoids the risk of errors caused by accumulation of two parts of the triple modular redundancy method for a long time due to the single event effect, and overcomes the failure of the triple modular redundancy method caused by the single event upset accumulation during long-term on-track operation.
Drawings
FIG. 1 is a schematic diagram of coding truncated cyclic codes for kbit data according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating framing of multiple pieces of program control data according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of multiple pieces of program control data storage according to an embodiment of the present invention;
FIG. 4 is a flowchart of the task of error detection and correction of data according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and examples.
The invention provides a low-cost satellite on-board program control data fault-tolerant method, which is characterized in that when a system is initialized or instructions are injected, each program control data information part is subjected to cyclic code coding, and when the system is verified to be correct, a satellite service center computer stores program control data (including instructions and error correction codes) together. Before each cycle or each instruction is started, error detection and correction are carried out. The method comprises the following steps:
s1, carrying out cyclic code encoding on the information part of each piece of program control data to obtain an error correction code of the program control data, wherein the information part of the program control data and the corresponding error correction code jointly form the program control data; the program control data comprises information part of task number, time and information content, wherein the information content is program control instructions, program control data blocks, relative program control instructions, thermal control data or load data.
And S2, forming an upper injection program control frame by the plurality of coded program control data, and injecting the upper injection program control frame to the house service center computer, wherein the upper injection program control frame comprises a synchronous word, a frame length, information parts of N pieces of program control data, an error correction code and a CRC (cyclic redundancy check) value, and N is more than or equal to 1.
There are two ways to perform cyclic code encoding in this step:
the first mode is as follows: cyclic code encoding the information portion of the program-controlled data using a cyclic code generator polynomial of the order of xnAnd (c) an n-k degree polynomial selected from the factors of +1, wherein k is the length of the information part of the program control data, n is k + r, and r is the supervision bit length.
The second way is: j 0 bit is added to the high bit of the information part of the program control data, the bit number of the expanded program control data information part is n + j bit, a cyclic code generator polynomial is adopted, the expanded program control data information part is circularly encoded to generate (n + j, k + j) cyclic code, then the (n + j, k + j) cyclic code is shortened by j bit to obtain (n, k) shortened cyclic code, j is an integer, and the smaller the j is, the better the j is.
S3, after receiving the upper-note program control frame, the house keeping center computer judges whether the synchronous word, the frame length and the CRC check value are correct, and stores N pieces of program control data; otherwise, discarding the upper-injection program control frame;
and S4, the house service center computer executes error detection and correction on each piece of stored program control data.
The S4 is executed before each piece of program control data is executed or according to a preset cycle, and includes the following steps:
s4.1, extracting information parts of the program control data stored in the satellite service center computer and corresponding error correcting codes of the information parts to form the program control data;
s4.2, converting the program control data into a code polynomial B (x), and dividing the code polynomial B (x) by a cyclic generation polynomial g (x) to obtain a syndrome polynomial r (x);
the method for converting the program control data into the code polynomial B (x) comprises the following steps:
when the program control data n data bits are d respectivelyn-1～d0The corresponding code polynomial B (x) is
B(x)＝dn-1xn-1+dn-2xn-2+...+d1x1+d0x0。
S4.3, if the syndrome polynomial r (x) is 0, the program control data is correct; if r (x) is not equal to 0 and there is an integer i, so that r (x) ximod (g (x)), i ═ 0,1,2, ┅ n-1, then the ith bit of the program data from low to high is erroneous, if r (x) is not equal to 0, but there is no integer i, so that r (x) ═ ximod (g(x))，i∈[0～n-1]Then it is assumed that a double bit error has occurred in the programmed data.
If the length of the data (i.e. the information part of the program control data) needing to be protected is M bytes, the invention occupies about 1.16M bytes for the case of selecting (54,48) the truncated cyclic code relative to the program control instruction, and occupies about 1.11M bytes for the case of selecting (79,72) the truncated cyclic code relative to the program control instruction. The triple modular redundancy method occupies 3N of storage space, and thousands of program control instructions, program control data blocks, relative program control instructions and load program control data are stored in the satellite service center computer, so that the storage space can be greatly saved, and the problem of shortage of internal memory can be solved.
If the method is used on the orbit for a long time, the traditional triple modular redundancy method has effective risks because the single event upset can be accumulated. The invention adopts the data error detection task to operate periodically, can finish the error detection and correction of N pieces of program-controlled data per period, and avoids the risk of errors in two parts due to the long-term accumulation of triple modular redundancy method by the single event effect.
Example (b):
the invention provides an embodiment of a low-cost satellite program control data fault tolerance method, which comprises the following specific steps:
(1) and determining the number r of the supervision bits. Assuming that the length of each program control data information part is k bits, r bits of parity bits (i.e. error correction codes) are added after error correction coding, and the length is changed to n-k + r.
To indicate n possible positions of an error code with r parity bits (i.e., error correction code), r and k satisfy the following relationship:
2r-1≥k+r
(2) and determining a cyclic code generator polynomial g (x). The generator polynomial g (x) may be selected from the (n, k) values, i.e. from xnAn n-k degree polynomial is selected as g (x) from the factor of + 1. If there is no g (x) meeting the requirement, j bits are truncated by the existing longer (n + j, k + j) cyclic code to obtain (n, k)
The cyclic code is truncated. The shortened cyclic code and the original cyclic code have the same error correction capability, and the coding method is the same as that before the shortening. The generator polynomial of the (n, k) truncated cyclic code is the generator polynomial g (x) of the cyclic code (n + j, k + j), with smaller j being better.
(3) And encoding by using a cyclic code. Firstly x is firstlyn-kMultiplying by an information code polynomial m (x), and then dividing x by a generator polynomial g (x)n-km (x), resulting in the quotient Q (x) and the remainder p (x), i.e.:
xn-km(x)/g(x)＝Q(x)+p(x)/g(x)
and finally, obtaining a code polynomial:
A(x)＝xn-km(x)+p(x)
the coefficients of the code polynomial are the encoded program control data.
(4) And framing and annotating the plurality of program control instructions according to the format of figure 2, wherein the frame for annotating comprises a synchronous word, the length of the frame, each program control instruction, an error correction code and a CRC value. After receiving the upper-injected program control frame, the house keeping center computer determines that the sync word, the frame length, and the CRC are correct, and stores a plurality of program control instructions and corresponding error correction codes, as shown in fig. 3.
And performing cyclic code encoding on the length of each program control data information part, such as 9 bytes of program control instructions, 6 bytes of relative program control instructions and 15 bytes of program control data blocks, namely each program control data contains a corresponding error correcting code.
(5) And when the program control data are initialized or injected in a program control mode, each program control data comprises a corresponding error correction code, and the information part of each program control data and the corresponding error correction code are respectively stored by the house service center computer. Before each program control data is executed or when the error is periodically detected, error detection and correction are executed on each program control data.
Before each program control data information part is used, a code polynomial B (x) is divided by a generator polynomial g (x) to obtain a remainder syndrome (syndrome) r (x)
B(x)/(g(x)＝Q(x)+r(x)/(g(x) (4)
(6) If the remainder r (x) is 0, the received data is correct, otherwise, an error code occurs. If r (x) is not equal to 0 and an integer i is present, so that r (x) ximod (g (x)), (i ═ 0,1,2, ┅ n-1), i.e. it can be found from the relation table between syndrome and single bit error position, and it is considered that the i-th bit has an error, table 1 lists the corresponding relation between (54,48) cyclic code error position and residue r (x), and its polynomial is g (x) ═ 6+ x + 1. If there is no integer i satisfying the above condition, it is considered that a double bit error occurs, as shown in fig. 4.
TABLE 1 error code position and syndrome correspondence table
(7) And the program control data error detection task runs periodically to detect the error of the m instructions, and m is determined according to the processing capacity of the processor without influencing the original task of the processor. And (4) detecting the error of each instruction according to steps (4), (5) and (6).
This embodiment was tested on a small satellite integrated electronic computer. The data targeted by fault injection comprises relative program control instructions, program control data blocks, load data and the like of the small satellites, truncated cyclic codes (79,72) are selected for a program control instruction error correction algorithm, truncated cyclic codes (54,48) are selected for a relative program control instruction error correction algorithm, and truncated cyclic codes (127,120) are selected for a program control data block. After the data are uploaded, a 1bit error and a 2bit error are generated on the data by a method of modifying the memory of the satellite service host. The fault of each data type is injected 100 times randomly, and the method can effectively detect and correct the error. The test results are shown in the following table:
table 2 error correction and detection results according to an embodiment of the present invention
The above description is only one embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Those skilled in the art will appreciate that the invention may be practiced without these specific details.
Claims (7)
1. A satellite program control data fault tolerance method is characterized by comprising the following steps:
s1, coding the information part of each program control data by a cyclic code to obtain the error correcting code of the program control data,
the information part of the program control data and the corresponding error correcting code jointly form the program control data;
s2, forming a plurality of encoded program control data into an upper injection program control frame, and injecting the upper injection program control frame to the house service center computer, wherein the upper injection program control frame comprises a synchronous word, a frame length, information parts of N pieces of program control data, an error correction code and a CRC (cyclic redundancy check) value, and N is more than or equal to 1;
s3, after receiving the upper-note program control frame, the house keeping center computer judges whether the synchronous word, the frame length and the CRC check value are correct, and stores N pieces of program control data; otherwise, discarding the upper-injection program control frame;
and S4, the house service center computer executes error detection and correction on each piece of stored program control data.
2. The satellite program control data fault tolerance method according to claim 1, wherein the information part of the program control data in step S1 includes program control commands, program control data blocks, relative program control commands, thermal control data, and payload data.
3. The method for fault tolerance of satellite program control data according to claim 1, wherein the step S1 is: cyclic code encoding the information portion of the program-controlled data using a cyclic code generator polynomial of the order of xnAnd (c) an n-k degree polynomial selected from the factors of +1, wherein k is the length of the information part of the program control data, n is k + r, and r is the supervision bit length.
4. The method for fault tolerance of satellite program control data according to claim 1, wherein the step S1 is: j 0 bit is added to the high bit of the information part of the program control data, the bit number of the expanded program control data information part is n + j bit, a cyclic code generator polynomial is adopted, the expanded program control data information part is circularly encoded to generate (n + j, k + j) cyclic code, then the (n + j, k + j) cyclic code is shortened by j bit to obtain (n, k) shortened cyclic code, j is an integer, and the smaller the j is, the better the j is.
5. The satellite program control data fault tolerance method according to claim 1, wherein the step S4 is executed before or according to a preset period of execution of each piece of program control data.
6. The satellite program control data fault tolerance method according to claim 1, wherein the specific method of S4 is as follows:
s4.1, extracting information parts of the program control data stored in the satellite service center computer and corresponding error correcting codes of the information parts to form the program control data;
s4.2, converting the program control data into a code polynomial B (x), and dividing the code polynomial B (x) by a cyclic generation polynomial g (x) to obtain a syndrome polynomial r (x);
s4.3, if the syndrome polynomial r (x) is 0, the program control data is correct; if r (x) is not equal to 0 and there is an integer i, so that r (x) ximod (g (x)), i ═ 0,1,2, ┅ n-1, then the ith bit of the program data from low to high is erroneous, if r (x) is not equal to 0, but there is no integer i, so that r (x) ═ ximod(g(x))，i∈[0～n-1]Then it is assumed that a double bit error has occurred in the programmed data.
7. The satellite program control data fault tolerance method according to claim 4, wherein in step S4.1, when n data bits of program control data are d respectivelyn-1～d0The corresponding code polynomial B (x) is
B(x)＝dn-1xn-1+dn-2xn-2+...+d1x1+d0x0。
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