CN113608019A - Multi-user comprehensive metering device - Google Patents
Multi-user comprehensive metering device Download PDFInfo
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- CN113608019A CN113608019A CN202110813184.3A CN202110813184A CN113608019A CN 113608019 A CN113608019 A CN 113608019A CN 202110813184 A CN202110813184 A CN 202110813184A CN 113608019 A CN113608019 A CN 113608019A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R22/00—Arrangements for measuring time integral of electric power or current, e.g. electricity meters
- G01R22/06—Arrangements for measuring time integral of electric power or current, e.g. electricity meters by electronic methods
- G01R22/08—Arrangements for measuring time integral of electric power or current, e.g. electricity meters by electronic methods using analogue techniques
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R22/00—Arrangements for measuring time integral of electric power or current, e.g. electricity meters
- G01R22/06—Arrangements for measuring time integral of electric power or current, e.g. electricity meters by electronic methods
- G01R22/10—Arrangements for measuring time integral of electric power or current, e.g. electricity meters by electronic methods using digital techniques
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Abstract
The invention relates to a multi-user comprehensive metering device which comprises a current mutual inductance circuit for sampling current signals of a plurality of users, a voltage mutual inductance circuit for sampling voltage signals of the plurality of users, a first multi-path analog selection switch connected with the current mutual inductance circuit to gate the current signals in a time-sharing manner, a second multi-path analog selection switch connected with the voltage mutual inductance circuit to gate the voltage signals in a time-sharing manner, a first A/D converter connected with the first multi-path analog selection switch, a second A/D converter connected with the second multi-path analog selection switch, an FPGA for gating user channels and metering electric energy of each user, a display module connected with the FPGA, a storage module connected with the FPGA, a communication module connected with the FPGA, a first multi-path analog selection switch, a second multi-path analog selection switch, a power supply circuit and a power supply circuit, The first A/D converter and the second A/D converter are respectively connected with the FPGA. The invention has simple structure, high reliability and convenient design.
Description
Technical Field
The invention relates to the field of electric energy metering, in particular to a multi-user comprehensive metering device.
Background
Currently, for the measurement of multi-user electric energy, there are two measurement schemes:
the first is a structure that the collection of each path of electric energy signal and data operation are processed by only one A/D converter and one CPU, and the voltage and current signals of multiple users are collected by a multi-path analog conversion switch, a sampling holder and an A/D converter. In the mode, the CPU continuously gates voltage and current signals of each user in a time-sharing manner, digital operation is carried out on a measured value to obtain an instantaneous power signal, and the electric energy value of a polling period is obtained by sampling for many times, averaging and multiplying the average value by the polling period. The digital data acquisition and integration system has the advantages that hardware elements of the instrument are fewer, but the work task of CPU processing is heavy, software is complex, data acquisition, calculation, integration, communication and the like are all realized by digital circuits, when system 'crash' and other faults occur, data loss is easily caused, and the reliability is difficult to guarantee.
Secondly, the electric energy of each user is measured by an independent circuit, the converted pulse signals are collected and calculated in a centralized way through the CPU, and meanwhile, the CPU also completes other data processing tasks. The scheme has the advantages that more hardware circuits are replaced by higher reliability, and various electric energy measuring integrated circuits with strong functions, small size and low price appear, so that the functions of the whole structure are greatly optimized, and the method is a more common method at present.
With the gradual maturity of the second scheme and the progress of the CPU and the memory technology, the computing power is stronger, the storage capacity is larger, and the cost of the unit computing power and the unit storage capacity is greatly reduced, so that the original defects of the first scheme are expected to be compensated, and the advantage of the relatively simple hardware structure is increasingly highlighted. Therefore, it is necessary to design a new type of electric energy metering device based on the first solution.
Disclosure of Invention
The invention aims to provide a multi-user comprehensive metering device with simple hardware structure and higher reliability.
In order to achieve the purpose, the invention adopts the technical scheme that:
a multi-user comprehensive metering device is used for metering electric energy of a plurality of users and comprises a current mutual inductance circuit for sampling current signals of the users, a voltage mutual inductance circuit for sampling voltage signals of the users, a first multi-path analog selection switch connected with the current mutual inductance circuit to gate the current signals in a time-sharing mode, a second multi-path analog selection switch connected with the voltage mutual inductance circuit to gate the voltage signals in a time-sharing mode, a first A/D converter connected with the first multi-path analog selection switch, a second A/D converter connected with the second multi-path analog selection switch, an FPGA used for gating user channels and metering electric energy of the users, a display module connected with the FPGA and used for displaying electric energy metering information of the users, a first switch, a second switch, a third switch and a fourth switch, The system comprises a storage module connected with the FPGA and used for storing electric energy metering information of each user, and a communication module connected with the FPGA and used for carrying out two-way communication, wherein the first multi-path analog selection switch, the second multi-path analog selection switch, the first A/D converter and the second A/D converter are respectively connected with the FPGA.
The FPGA comprises an Avalon bus, and a soft core CPU is embedded in the FPGA and hung on the Avalon bus.
The FPGA further comprises an A/D controller, a display controller, a storage controller and a communication controller, wherein the A/D controller, the display controller, the storage controller and the communication controller are hung on the Avalon bus, the first A/D converter and the second A/D converter are connected with the A/D controller, the display module is connected with the display controller, the storage module is connected with the storage controller, and the communication module is connected with the communication controller.
The FPGA further comprises an FFT module, a PLL module, an FIR module, a timing module, a first input and output module, an EPCS controller, an SDRAM controller, a first SPI controller, a second SPI controller, a UART module and a second input and output module which are hung on the Avalon bus.
The active electric energy metering module for realizing electric energy metering by the soft core CPU comprises a first CIC extraction filter for carrying out deceleration acquisition on the current signal, a second CIC extraction filter for carrying out deceleration acquisition on the voltage signal, a first IIR high-pass filter connected with the first CIC extraction filter, a second IIR high-pass filter connected with the second CIC extraction filter, a multiplier respectively connected with the first IIR high-pass filter and the second IIR high-pass filter so as to calculate and obtain power data, an FIR low-pass filter connected with the multiplier, and a DFC digital frequency converter connected with the FIR low-pass filter and used for filtering reactive power.
The first IIR high-pass filter and the second IIR high-pass filter are all elliptical filters.
The current mutual inductance circuit and the voltage mutual inductance circuit both comprise ultracrystalline iron cores.
The first A/D converter and the second A/D converter respectively comprise an A/D conversion chip and a first-order RC filter arranged at the input end of the A/D conversion chip.
The storage module comprises SDPAR and FLASH; the display module comprises an LCD display screen; the communication module comprises an RS485 bus.
The multi-user comprehensive metering device further comprises a power supply module.
Due to the application of the technical scheme, compared with the prior art, the invention has the following advantages: the invention has simple structure, high reliability and convenient design.
Drawings
Figure 1 is an overall architecture diagram of the multi-user integrated metering device of the present invention.
FIG. 2 is a hardware block diagram of the multi-user integrated metering device of the present invention.
Fig. 3 is a structural block diagram of an active electric energy metering module in the multi-user integrated metering device of the invention.
Detailed Description
The invention will be further described with reference to examples of embodiments shown in the drawings to which the invention is attached.
The first embodiment is as follows: as shown in fig. 1, a multi-user comprehensive metering device for metering electric energy of multiple users comprises a current mutual inductance circuit, a voltage mutual inductance circuit, a first multi-channel analog selection switch, a second multi-channel analog selection switch, a first a/D converter, a second a/D converter, an FPGA, a display module, a storage module, a communication module and a key module. The current mutual inductance circuit is connected with a plurality of users and is used for sampling current signals of the users. The voltage mutual inductance circuit is connected with a plurality of users and used for sampling voltage signals of the users. The first multi-channel analog selection switch is connected with the current mutual inductance circuit and used for time-sharing gating and outputting current signals of the required users. The second multi-channel analog selection switch is connected with the voltage mutual inductance circuit and used for time-sharing gating and outputting the voltage signals of the required users. The first A/D converter is connected with the first multi-path analog selection switch and is used for correspondingly converting the gated current signals into current digital signals. The second A/D converter is connected with the second multi-channel analog selection switch and is used for correspondingly converting the gated voltage signals into voltage digital signals. The FPGA is respectively connected with the first A/D converter, the second A/D converter, the first A/D converter and the second A/D converter, and is used for controlling the first multi-path analog selection switch and the second multi-path analog selection switch to conduct time-sharing gating, and conducting electric energy metering on each user based on the current and the voltage of the user channel which is selected to be conducted and sent by the first A/D converter and the second A/D converter. The display module is connected with the FPGA and used for displaying the electric energy metering information of each user. The storage module is connected with the FPGA and used for storing electric energy metering information of each user. The communication module is connected with the FPGA and used for carrying out two-way communication.
As shown in fig. 2, the FPGA scheme of the present invention is as follows: the FPGA is internally embedded with a soft core CPU which comprises an Avalon bus, the soft core CPU is hung on the Avalon bus, the FPGA further comprises an A/D controller hung on the Avalon bus, a display controller, a storage controller, a communication controller, an FFT module, a PLL module, an FIR module, a timing module Timer, a first input/output module, an EPCS controller, an SDRAM controller, a first SPI controller, a second SPI controller, a UART module and a second input/output module, the first A/D converter and the second A/D converter are connected with the A/D controller, the display module is connected with the display controller, the storage module is connected with the storage controller, and the communication module is connected with the communication controller. The direct transmission of data among the functional modules is realized through the Avalon bus, and different from a common bus, all devices on the Avalon bus can be used as main devices and can perform data communication with each other.
In this embodiment, the FPGA type is EP2C8Q of cycleii, which includes 8256 logic Blocks, 165KRAM and 36M 4K RAM Blocks, 18 embedded multipliers, 2 phase-locked loops PLL, 138I/O ports, and the like, and is an FPGA chip with higher integration level and higher performance.
The FPGA is designed by adopting an SOPC technology, an embedded soft core processor is a Nosi II soft core processor, the general RSIC processor adopts a pipeline technology and a Harvard structure, and the embedded FPGA is a 32-bit embedded CPU which is oriented to users and can be freely customized according to the actual requirements of the users. NosiII has obvious advantage in SOPC integration, and the interface can be selected in a flexible way, and system performance can be promoted, reduces system cost, extension system life, powerful, easy-to-use. The Avalon bus is a set of on-chip bus system developed for SOPC solution, is a bus structure for realizing the connection of Nios series soft-core processor and on-chip peripherals, optimizes the interconnection rule of the on-chip system, provides an easy-to-use interface specification, and has indispensable effect. The Avalon bus defines a series of signals and transmission modes and behaviors supported by the signals, adopts a switching bus structure, has the characteristics of simplicity, high performance, bus specification, less occupied resources, consistency of master and slave interfaces and the like, and can greatly improve the operation efficiency.
The electric energy metering analysis is completed by adopting IP Core. The advantage of FPGA is utilized to call the IP Core in FPGA to carry out operation processing on the collected digital signals, and the results of the power parameters such as voltage, current effective values, active power, reactive power and the like are obtained.
As shown in fig. 3, the active power metering module for implementing power metering in the soft core CPU includes a first CIC decimation filter for performing downshifting acquisition on a current signal, a second CIC decimation filter for performing downshifting acquisition on a voltage signal, a first IIR high-pass filter connected to the first CIC decimation filter, a second IIR high-pass filter connected to the second CIC decimation filter, a multiplier connected to the first IIR high-pass filter and the second IIR high-pass filter respectively for calculating power data, an FIR low-pass filter connected to the multiplier, and a DFC digital frequency converter connected to the FIR low-pass filter and configured to filter reactive power. And the first IIR high-pass filter and the second IIR high-pass filter are all elliptical filters. The working principle is as follows: u (t) and i (t) are digital signals converted by the data collection unit to 16bit accuracy with a sampling rate of 32 kHz. In order to accelerate the working efficiency of the FPGA within a clock frequency, a CIC (common information center) decimation filter is adopted to respectively realize u (t) and i (t) reduction of the acquisition rate, at the moment, a voltage and current signal contains partial direct current components, the generated direct current components are eliminated through an IIR (infinite impulse response) high-pass filter so as to reduce errors caused by a system, and then, the processed voltage and current data information is sent to a multiplier to be subjected to multiplication operation so as to obtain instantaneous power. The effective power is actually the dc component in the instantaneous power just calculated, and at that time, FIR low-pass filter is needed to perform low-pass filtering on the instantaneous power. Since there will be some harmonic components in the instantaneous power, but the low pass filter is not ideal, there will be a small amount of reactive power in the output power. And finally, selecting a DFC digital frequency converter to filter the reactive power, outputting pulses with the same period and inverse proportion, and calculating the active electric energy.
The current mutual inductance circuit and the voltage mutual inductance circuit at the front end are the beginning of the signal conditioning circuit, high-voltage signals can be converted into low-voltage signals through corresponding proportion, and the converted low-voltage signals are transmitted to the corresponding A/D converters. For the current mutual inductance circuit, in the design process, the possibility of the type and the number of the users accessing the electric appliances needs to be considered, and inconvenience caused by overlarge or undersize current input is avoided, so that the current mutual inductor with the model TA17 (L) -04 is selected, comprises an ultracrystalline iron core and can work in the environment of-55-85 ℃; the frequency response is 20Hz-20KHz, and has better linearity. For a voltage mutual inductance circuit, when a 220V/50Hz alternating voltage signal is input from the outside, the design selects a transformer with the model of TV19-E, and an iron core of the transformer is made of an ultracrystalline ring material, so that the transformer is fully sealed and high in reliability; the frequency response is 20-20 kHz; rated current 5mA/5 mA; the linearity is better than 0.2 percent, and the impact resistance is strong; isolation withstand voltage AC2000V/1 minute; the current ratio across the transformer is related to the turns ratio.
The A/D converter selects an AD73360 chip, because the AD73360 selects the E- Δ method, a digital decimation filter is included, filtering work can be carried out by anti-aliasing through the sampling frequency, and only a first-order RC filter is added at the input end of the A/D converter. Therefore, the first A/D converter and the second A/D converter respectively comprise an A/D conversion chip and a first-order RC filter arranged at the input end of the A/D conversion chip.
In the real-time processing of the electric energy parameters, a large amount of data needs to be stored, such as the electricity utilization information of a user, the accurate time and type of abnormal conditions occurring in the operation process of an electricity meter system, and the like. To meet the above requirements, the memory module includes SDPAR and FLASH.
The display module comprises an LCD display screen, and the current electricity utilization information, system fault information and the like of a user can be checked through the LCE display screen. And a key module connected with the FPGA can be configured to perform corresponding operations such as selection on information to be displayed.
The communication module comprises an RS485 bus, can transmit electric energy metering information to a PC (personal computer) end and the like and receive remote instructions and the like, and is convenient to manage.
The multi-user comprehensive metering device also comprises a power supply module, wherein the power supply module comprises a transformer for reducing voltage, a bridge rectifier circuit connected with the transformer, a filter circuit connected with the bridge rectifier circuit and a voltage stabilizing circuit connected with the filter circuit, so that 220V alternating current commercial power can be converted into 5V/3.3V direct current working power and supplied to required units.
In addition, the multi-user integrated metering device can also comprise a clock circuit, a configuration circuit and the like.
The basic functions of the multi-user integrated metering device of the scheme are as follows:
the metering function is as follows: the multi-channel analog switch module inputs small voltage and current signals processed by the voltage and current mutual inductance circuit into the A/D converter, and then calculates the acquired information, thereby rapidly and accurately measuring the power consumption of each user.
And (4) display function: the current power consumption information of the user can be intuitively displayed on the liquid crystal display screen. And the multi-user metering adopts a successive analogy mode to timely present the electrical parameter information of the corresponding user.
A storage function: the multi-user electric energy metering can store the electricity utilization information of different users in the configured memory respectively, and the electricity utilization information of the users can be ensured not to be lost under the condition that the system is powered off or fails.
And (4) a transmission function: in order to facilitate the statistics of the electric energy use information by the power utilization management center, the comprehensive metering device has a two-way communication function, the automatic centralized reading of the power utilization data is realized, and therefore, the timely transmission of the electric parameters can be realized through RS485 communication or wireless communication.
The above embodiments are merely illustrative of the technical ideas and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the protection scope of the present invention. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (10)
1. A multi-user integrated metering device is used for metering electric energy of a plurality of users, and is characterized in that: the multi-user comprehensive metering device comprises a current mutual inductance circuit for sampling current signals of a plurality of users, a voltage mutual inductance circuit for sampling voltage signals of the plurality of users, a first multi-path analog selection switch connected with the current mutual inductance circuit to gate the current signals in a time-sharing mode, a second multi-path analog selection switch connected with the voltage mutual inductance circuit to gate the voltage signals in a time-sharing mode, a first A/D converter connected with the first multi-path analog selection switch, a second A/D converter connected with the second multi-path analog selection switch, an FPGA for gating user channels and metering electric energy of each user, a display module connected with the FPGA and used for displaying electric energy metering information of each user, a storage module connected with the FPGA and used for storing the electric energy metering information of each user, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a sixth switch, a sixth switch, a sixth, a sixth switch, a sixth, a sixth, a sixth, a sixth, a, And the communication module is connected with the FPGA and used for carrying out bidirectional communication, and the first multi-path analog selection switch, the second multi-path analog selection switch, the first A/D converter and the second A/D converter are respectively connected with the FPGA.
2. The multi-user integrated metering device of claim 1, wherein: the FPGA comprises an Avalon bus, and a soft core CPU is embedded in the FPGA and hung on the Avalon bus.
3. The multi-user integrated metering device of claim 2, wherein: the FPGA further comprises an A/D controller, a display controller, a storage controller and a communication controller, wherein the A/D controller, the display controller, the storage controller and the communication controller are hung on the Avalon bus, the first A/D converter and the second A/D converter are connected with the A/D controller, the display module is connected with the display controller, the storage module is connected with the storage controller, and the communication module is connected with the communication controller.
4. The multi-user integrated metering device of claim 3, wherein: the FPGA further comprises an FFT module, a PLL module, an FIR module, a timing module, a first input and output module, an EPCS controller, an SDRAM controller, a first SPI controller, a second SPI controller, a UART module and a second input and output module which are hung on the Avalon bus.
5. The multi-user integrated metering device of claim 2, wherein: the active electric energy metering module for realizing electric energy metering by the soft core CPU comprises a first CIC extraction filter for carrying out deceleration acquisition on the current signal, a second CIC extraction filter for carrying out deceleration acquisition on the voltage signal, a first IIR high-pass filter connected with the first CIC extraction filter, a second IIR high-pass filter connected with the second CIC extraction filter, a multiplier respectively connected with the first IIR high-pass filter and the second IIR high-pass filter so as to calculate and obtain power data, an FIR low-pass filter connected with the multiplier, and a DFC digital frequency converter connected with the FIR low-pass filter and used for filtering reactive power.
6. The multi-user integrated metering device of claim 5, wherein: the first IIR high-pass filter and the second IIR high-pass filter are all elliptical filters.
7. The multi-user integrated metering device of claim 1, wherein: the current mutual inductance circuit and the voltage mutual inductance circuit both comprise ultracrystalline iron cores.
8. The multi-user integrated metering device of claim 1, wherein: the first A/D converter and the second A/D converter respectively comprise an A/D conversion chip and a first-order RC filter arranged at the input end of the A/D conversion chip.
9. The multi-user integrated metering device of claim 1, wherein: the storage module comprises SDPAR and FLASH; the display module comprises an LCD display screen; the communication module comprises an RS485 bus.
10. The multi-user integrated metering device of claim 1, wherein: the multi-user comprehensive metering device further comprises a power supply module.
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| CN202110813184.3A CN113608019A (en) | 2021-07-19 | 2021-07-19 | Multi-user comprehensive metering device |
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| CN202110813184.3A CN113608019A (en) | 2021-07-19 | 2021-07-19 | Multi-user comprehensive metering device |
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Citations (5)
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| CN1044344A (en) * | 1989-01-16 | 1990-08-01 | 许之端 | Intelligent electric power metering device |
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2021
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Patent Citations (5)
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| CN1044344A (en) * | 1989-01-16 | 1990-08-01 | 许之端 | Intelligent electric power metering device |
| CN2308900Y (en) * | 1997-08-05 | 1999-02-24 | 山东矿业学院 | Network multi-user watt metering device |
| CN203012013U (en) * | 2012-06-22 | 2013-06-19 | 大同电力高级技工学校 | ARM-based multi-user intelligent electric meter |
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