CN113595546B - Broadband high-speed level switching circuit and high-speed clock chip - Google Patents
Broadband high-speed level switching circuit and high-speed clock chip Download PDFInfo
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Abstract
According to the broadband high-speed level switching circuit and the high-speed clock chip, the current mirror module provides stable input current for the first NMOS transistor and the second NMOS transistor, when the resistance values of the first resistor and the second resistor are determined, the source voltages of the first NMOS transistor and the second NMOS transistor are constant, the grid voltages of the first NMOS transistor and the second NMOS transistor are the voltages of the logic signals input externally, under the condition that the source voltages and the currents are constant, the drain voltages of the first NMOS transistor and the second NMOS transistor are adjusted in a self-adaptive mode according to the voltages of the logic signals input externally, the external logic signals with large change amplitude can be adapted, meanwhile, a high-voltage protection circuit is not required to be arranged, level switching is achieved, and meanwhile circuit simplification is achieved.
Description
[ technical field ] A
The invention relates to the technical field of analog integrated circuits, in particular to a broadband high-speed level conversion circuit and a high-speed clock chip.
[ background of the invention ]
In analog integrated circuit applications, a plurality of modules, i.e., voltage domains, which do not work at a supply voltage are provided in a same integrated circuit chip, for example, a first logic signal of a first circuit, which works at a first voltage, needs to be input into a second circuit, which works at a second voltage, and the second circuit may not receive the first logic signal correctly or cannot distinguish the first logic signal correctly.
The level shift circuit in the prior art can only adapt to low-speed logic signals and cannot adapt to high-speed logic signals when performing signal conversion, and a high-voltage protection circuit for protecting low-voltage high-speed devices is arranged in the level shift circuit aiming at external high-speed logic signals with large voltage variation amplitude (for example, the peak value of an input range is 0.2V-3V), which is not beneficial to simplification of the level shift circuit.
[ summary of the invention ]
The invention aims to provide a broadband high-speed level conversion circuit, a multi-level conversion circuit and a chip, and aims to solve the technical problem that the level conversion circuit in the prior art cannot realize high adaptability and simplification at the same time.
The technical scheme of the invention is as follows: there is provided a broadband high-speed level shifter circuit comprising:
a first line connected to a current source;
the current mirror module comprises a current output end and a current input end connected with the first line;
the first interface module comprises a first NMOS transistor and a first input node coupled with the grid electrode of the first NMOS transistor, and the drain electrode of the first NMOS transistor is coupled with the current output end and is connected with a second line through a first resistor;
a second interface module including a second NMOS transistor and a second input node coupled to a gate of the second NMOS transistor, a drain of the second NMOS transistor being coupled to the current output terminal and connected to the second line via a second resistor;
a first output node arranged between the source electrode of the first NMOS transistor and the first resistor;
and a second output node disposed between the source of the second NMOS transistor and the second resistor.
Preferably, the first interface module further includes a third resistor disposed between the gate of the first NMOS transistor and the first input node.
Preferably, the second interface module further includes a fourth resistor disposed between the gate of the second NMOS transistor and the second input node.
Preferably, the current mirror module includes a first PMOS transistor and a second PMOS transistor, a source of the first PMOS transistor is coupled to the first line, a drain of the first PMOS transistor is coupled to a source of the second PMOS transistor, a drain of the second PMOS transistor is coupled to the current output terminal, and a substrate of the first PMOS transistor is connected to a substrate of the second PMOS transistor and then connected to the first line.
Preferably, the current mirror module further includes a third PMOS transistor, a source and a substrate of the third PMOS transistor are respectively connected to the first line, and a drain of the third PMOS transistor is connected to a gate of the first PMOS transistor.
Preferably, the wideband high-speed level shifter circuit further includes a fourth PMOS transistor and a fifth PMOS transistor, a source and a substrate of the fourth PMOS transistor are respectively connected to the first line, and a source and a substrate of the fifth PMOS transistor are respectively connected to the first line.
The other technical scheme of the invention is as follows: there is provided a wideband high-speed level shifter circuit comprising at least two shifter units, each of said shifter units comprising:
a current input line;
the current mirror module comprises a current output end and a current input end connected with the current input line;
the first interface module comprises a first NMOS transistor and a first input node coupled with the grid electrode of the first NMOS transistor, and the drain electrode of the first NMOS transistor is coupled with the current output end and is connected with a current input line of the next-stage conversion unit through a first resistor;
the second interface module comprises a second NMOS transistor and a second input node coupled with the grid electrode of the second NMOS transistor, and the drain electrode of the second NMOS transistor is coupled with the current output end and is connected with the current input line of the next-stage conversion unit through a second resistor;
a first output node disposed between the source of the first NMOS transistor and the first resistor;
and a second output node arranged between the source of the second NMOS transistor and the second resistor;
wherein the current input line of the conversion unit at the uppermost stage is connected to a current source.
Preferably, each of the current mirror modules includes a first PMOS transistor and a second PMOS transistor, a source of the first PMOS transistor is coupled to the current input line, a drain of the first PMOS transistor is coupled to a source of the second PMOS transistor, a drain of the second PMOS transistor is coupled to the current output terminal, and a substrate of the first PMOS transistor is connected to a substrate of the second PMOS transistor and then connected to the current input line.
The other technical scheme of the invention is as follows: the high-speed clock chip comprises at least one broadband high-speed level conversion circuit, wherein a first input node and a second input node of each broadband high-speed level conversion circuit are respectively connected with an external chip and used for receiving a group of high-speed signals sent by the external chip.
Preferably, the range of the high-speed signal sent by the external chip is 0 to a, where a is the swing amplitude in the maximum voltage interval of the external work.
The invention relates to a broadband high-speed level switching circuit and a high-speed clock chip, comprising: a first line connected to a current source; the current mirror module comprises a current output end and a current input end connected with the first circuit; the first interface module comprises a first NMOS transistor and a first input node coupled with the grid electrode of the first NMOS transistor, and the drain electrode of the first NMOS transistor is coupled with the current output end and is connected with a second line through a first resistor; a second interface module including a second NMOS transistor and a second input node coupled to a gate of the second NMOS transistor, a drain of the second NMOS transistor being coupled to the current output terminal and connected to the second line via a second resistor; a first output node disposed between the source of the first NMOS transistor and the first resistor; the current mirror module provides stable input current for the first NMOS transistor and the second NMOS transistor, when the resistance values of the first resistor and the second resistor are determined, the source voltages of the first NMOS transistor and the second NMOS transistor are constant, the gate voltages of the first NMOS transistor and the second NMOS transistor are the voltages of the logic signals input externally, under the condition that the source voltages and the currents are constant, the drain voltages of the first NMOS transistor and the second NMOS transistor are adaptively adjusted according to the voltages of the logic signals input externally, when the voltage of the logic signals input externally is low, the first NMOS transistor and the second NMOS transistor work in a saturation region, and when the voltage of the logic signals input externally is high, the first NMOS transistor and the second NMOS transistor work in a linear working region, the circuit can adapt to external logic signals with large variation amplitude, meanwhile, a high-voltage protection circuit is not required to be arranged, and the simplification of the circuit is realized while level conversion is realized.
[ description of the drawings ]
FIG. 1 is a schematic diagram of a wideband high-speed level shifter according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of a wideband high-speed level shifter according to a second embodiment of the present invention;
fig. 3 is a schematic structural diagram of a high-speed clock chip according to a third embodiment of the invention.
[ detailed description ] embodiments
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first", "second" and "third" in the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of the feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise. All directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are only used to explain the relative positional relationship between the components, the movement, and the like in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
Fig. 1 is a schematic structural diagram of a wideband high-speed level shifter circuit according to a first embodiment of the present invention, and as shown in fig. 1, the wideband high-speed level shifter circuit 100 includes a first line 11, a second line 12, a current mirror module 20, a first interface module 31, a second interface module 32, a first resistor R1, a second resistor R2, a first output node 41, and a second output node 42.
Wherein, first circuit 11 is connected with the current source, current mirror module 20 is connected with first circuit 11, current mirror module 20 includes current input 21 and current output 22, current input 21 is connected with first circuit 11, current output 22 is connected with first interface module 31 and second interface module 32 respectively, current mirror module 20 ensures that the control current of following the output of current output 22 equals with the reference current that current input 21 received, current mirror module 20 provides stable operating current for first interface module 31 and second interface module 32 are connected.
The first interface module 31 includes a first NMOS transistor Q1 and a first input node 311, a gate of the first NMOS transistor Q1 is coupled to the first input node 311, an external high-speed logic control signal is input to the first interface module 31 from the first input node 311, a drain of the first NMOS transistor Q1 is coupled to the current output terminal 22, and a source of the first NMOS transistor Q1 is connected to the second line 12 via a first resistor R1. Similarly, the second interface module 32 includes a second NMOS transistor Q2 and a second input node 321, the gate of the second NMOS transistor Q2 is coupled to the second input node 321, an external high-speed logic control signal is input to the second interface module 32 from the second input node 321, the drain of the second NMOS transistor Q2 is coupled to the current output terminal 22, and the source of the second NMOS transistor Q2 is connected to the second line 12 through a second resistor R2.
A first output node 41 is disposed between the source of the first NMOS transistor Q1 and the first resistor R1, and a second output node 42 is disposed between the source of the second NMOS transistor Q2 and the second resistor R2.
In this embodiment, the second line 12 may be grounded, or may be connected to other circuits, for example, the current of the second line 12 may be used as the bias current of the next stage of amplifying circuit.
In this embodiment, the control current flowing into the first NMOS transistor Q1 and the second NMOS transistor Q2 through the current mirror module 20 tends to be constant, when the resistance values of the first resistor R1 and the second resistor R2 are determined, the control current is divided into two paths of working currents with determined magnitudes at the current output end 22, the first path of working current passes through the first NMOS transistor Q1 and the first resistor R1, the second path of working current passes through the second NMOS transistor Q2 and the second resistor R2, the voltage of the first output node 41 is equal to the source voltage of the first NMOS transistor Q1, and when the first path of working current and the resistance value of the first resistor R1 are determined, the voltage of the first output node 41 and the source voltage of the first NMOS transistor Q1 tend to be constant; similarly, the voltage of the second output node 42 is equal to the source voltage of the second NMOS transistor Q2, and when the second operating current and the resistance value of the second resistor R2 are determined, the voltage of the second output node 42 and the source voltage of the second NMOS transistor Q2 tend to be constant.
In the present embodiment, the gate voltage of the first NMOS transistor Q1 is related to the voltage of the external high-speed logic control signal, and the drain voltage of the first NMOS transistor Q1 can be adaptively adjusted according to the voltage of the high-speed logic control signal when the first operating current flowing through the first NMOS transistor Q1 and the source voltage of the first NMOS transistor Q1 both tend to be constant. The gate voltage of the second NMOS transistor Q2 is related to the voltage of the external high-speed logic control signal, and the drain voltage of the second NMOS transistor Q2 can be adaptively adjusted according to the voltage of the high-speed logic control signal when the second operating current flowing through the second NMOS transistor Q2 and the source voltage of the second NMOS transistor Q2 both tend to be constant.
Specifically, in the use process of the broadband high-speed level shifter circuit 100 of this embodiment, the voltage of the external high-speed logic control signal is set to be higher than the threshold voltages of the first NMOS transistor Q1 and the second NMOS transistor Q2, and when the voltage of the external high-speed logic control signal is lower, for example, 0.2 to 0.5V, the first NMOS transistor Q1 and the second NMOS transistor Q2 operate in a saturation region and assume a source follower state, and the signal voltages output by the first output node 41 and the second output node 42 tend to be constant, for example, 0 to 1V; when the voltage of the external high-speed logic control signal is high, for example, 0.5 to 2.5V, the gate voltage increases, the operating current and the source voltage do not change, the drain voltage decreases, the first NMOS transistor Q1 and the second NMOS transistor Q2 enter a linear operating region, in the linear operating region, the gate signal can only reach the output through capacitive coupling, and the signal voltage output by the first output node 41 and the second output node 42 tends to be constant, for example, 0 to 1V. In this embodiment, the first NMOS transistor Q1 and the second NMOS transistor Q2 can adjust their working ranges according to the voltage of the external high-speed logic control signal, and can adapt to the external logic signal with a large variation range, without providing a high-voltage protection circuit, thereby achieving level conversion and circuit simplification.
In an alternative embodiment, with continued reference to fig. 1, the first interface module 31 further includes a third resistor R3 disposed between the gate of the first NMOS transistor Q1 and the first input node 311; the second interface module 32 further includes a fourth resistor R4 disposed between the gate of the second NMOS transistor Q2 and the second input node 321. By setting the third resistor R3, the signal voltage input to the gate of the first NMOS transistor Q1 can be adjusted; by the setting of the fourth resistor R4, the signal voltage input to the gate of the second NMOS transistor Q2 can be adjusted.
In the embodiment, the voltage of the current output terminal 22 of the current mirror module 20 is determined by the drain voltage of the first NMOS transistor Q1 and the source voltage of the second NMOS transistor Q2, and the drain voltage of the first NMOS transistor Q1 and the source voltage of the second NMOS transistor Q2 are changed along with the voltage change of the high-speed logic control signal, and the embodiment controls the channel length in the current mirror module 20 so that the current mirror module 20 needs to be as insensitive to the voltage change of the current output terminal 22, so, in the embodiment, the current mirror module 20 may adopt, but is not limited to, the following implementation manner, specifically, the current mirror module 20 includes a first PMOS transistor Q3 and a second PMOS transistor Q4, the source of the first PMOS transistor Q3 is coupled to the first line 11, the drain of the first PMOS transistor Q3 is coupled to the source of the second PMOS transistor Q4, the drain of the second PMOS transistor Q4 is coupled to the current output terminal 22, and the substrate of the first PMOS transistor Q3 is connected to the substrate of the second PMOS transistor Q4 and then to the first line 11. Further, the current mirror module 20 further includes a third PMOS transistor Q5, a source of the third PMOS transistor Q5 and a substrate of the third PMOS transistor Q5 are respectively connected to the first line 11, and a drain of the third PMOS transistor Q5 is connected to a gate of the first PMOS transistor Q3. While the above is a specific implementation manner of the current mirror module 20 in the present embodiment, it should be understood by those skilled in the art that the current mirror module 20 may also adopt other implementation manners as long as it can output stable control currents to the first interface module 31 and the second interface module 32.
In an alternative embodiment, the wideband high speed level shifter circuit 100 further includes a fourth PMOS transistor Q6 and a fifth PMOS transistor Q7, a source and a substrate of the fourth PMOS transistor Q6 are respectively connected to the first line 11, and a source and a substrate of the fifth PMOS transistor Q7 are respectively connected to the first line.
Fig. 2 is a schematic structural diagram of a broadband high-speed level shifter circuit according to a second embodiment of the present invention, as shown in fig. 2, the broadband high-speed level shifter circuit 200 includes at least two shifter units 200a, each of the shifter units 200a has a structure similar to that of the broadband high-speed level shifter circuit 100 according to the first embodiment, in fig. 2 of this embodiment, the same electrical components as those in fig. 1 are labeled by the same reference numerals, different shifter units 200a adopt a cascade mode, each shifter unit 200a includes a current input line 51, a current mirror module 20, a first interface module 31, a second interface module 32, a first resistor R1, a second resistor R2, a first output node 41, and a second output node 42, wherein the current mirror module 20 is connected to the current input line 51, the current mirror module 20 includes a current input terminal 21 and a current output terminal 22, the current input terminal 21 is connected to the current input line 51, the current output terminal 22 is connected to the first interface module 31 and the second interface module 32, respectively, the current mirror module 20 ensures that the control current output from the current output terminal 22 is equal to the reference current received by the current input terminal 21, and the current mirror module 20 provides a stable working current for the connection of the first interface module 31 and the second interface module 32.
The first interface module 31 includes a first NMOS transistor Q1 and a first input node 311, a gate of the first NMOS transistor Q1 is coupled to the first input node 311, an external high-speed logic control signal is input to the first interface module 31 from the first input node 311, a drain of the first NMOS transistor Q1 is coupled to the current output terminal 22, and a source of the first NMOS transistor Q1 is connected to the current input line 51 of the next-stage conversion unit 200a via a first resistor R1. Similarly, the second interface module 32 includes a second NMOS transistor Q2 and a second input node 321, a gate of the second NMOS transistor Q2 is coupled to the second input node 321, an external high-speed logic control signal is input to the second interface module 32 from the second input node 321, a drain of the second NMOS transistor Q2 is coupled to the current output terminal 22, and a source of the second NMOS transistor Q2 is connected to the current input line 51 of the next-stage conversion unit 200a via a second resistor R2.
In each of the converting units 200a of this embodiment, the current input line 51 of its own is equivalent to the first line 11 of the first embodiment, the current input line 51 of the converting unit 200a of the next stage is equivalent to the second line 12 of the first embodiment, the current input line 51 of the converting unit 200a of the uppermost stage is connected to a current source, and the structures and connection relationships of the current mirror module 20, the first interface module 31, the second interface module 32, the first resistor R1, the second resistor R2, the first output node 41, and the second output node 42 are specifically referred to the first embodiment, which is not repeated herein.
Fig. 3 is a schematic structural diagram of a high-speed clock chip according to a third embodiment of the present invention, and as shown in fig. 3, the high-speed clock chip 300 includes at least one wideband high-speed level shifter circuit 100, and a first input node 311 and a second input node 321 of each wideband high-speed level shifter circuit are connected to each other by an external chip and configured to receive a set of high-speed signals, where the range of the high-speed signals is 0 to a, where a is a swing amplitude in an external maximum operating voltage interval, for example, the range of the high-speed signals is 0.2V to 3V.
While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A wideband high-speed level shifter circuit, comprising:
a first line connected to a current source;
the current mirror module comprises a current output end and a current input end connected with the first circuit;
the first interface module comprises a first NMOS transistor and a first input node coupled with the grid electrode of the first NMOS transistor, the drain electrode of the first NMOS transistor is coupled with the current output end and is connected with a second line through a first resistor, the first NMOS transistor is used for controlling the voltage in the first interface module, and the first resistor is used for controlling the current output by the current output end to the first interface module;
the second interface module comprises a second NMOS transistor and a second input node coupled with the grid electrode of the second NMOS transistor, the drain electrode of the second NMOS transistor is coupled with the current output end and is connected with the second line through a second resistor, the second NMOS transistor is used for controlling the voltage in the second interface module, and the second resistor is used for controlling the current output by the current output end to the second interface module;
a first output node disposed between the source of the first NMOS transistor and the first resistor;
and a second output node disposed between the source of the second NMOS transistor and the second resistor.
2. The wideband high speed level shifter circuit of claim 1 wherein the first interface module further comprises a third resistor disposed between the gate of the first NMOS transistor and the first input node.
3. The wideband high speed level shifter circuit of claim 1, wherein the second interface module further comprises a fourth resistor disposed between the gate of the second NMOS transistor and the second input node.
4. The wideband high-speed level shifter circuit of claim 1, wherein the current mirror module comprises a first PMOS transistor and a second PMOS transistor, a source of the first PMOS transistor is coupled to the first line, a drain of the first PMOS transistor is coupled to a source of the second PMOS transistor, a drain of the second PMOS transistor is coupled to the current output, and a substrate of the first PMOS transistor is connected to a substrate of the second PMOS transistor and then to the first line.
5. The wideband high speed level shifter circuit of claim 4, wherein the current mirror module further comprises a third PMOS transistor having its source and substrate connected to the first line, respectively, and its drain connected to the gate of the first PMOS transistor.
6. The wideband high speed level shifter circuit of claim 5 further comprising a fourth PMOS transistor having its source and substrate connected to the first line, respectively, and a fifth PMOS transistor having its source and substrate connected to the first line, respectively.
7. A wideband high-speed level shifter circuit comprising at least two shifter units, each of said shifter units comprising:
a current input line;
the current mirror module comprises a current output end and a current input end connected with the current input line;
the first interface module comprises a first NMOS transistor and a first input node coupled with the grid electrode of the first NMOS transistor, the first NMOS transistor is used for controlling the voltage in the first interface module, and a first resistor is used for controlling the current output by the current output end to the first interface module;
the second interface module comprises a second NMOS transistor and a second input node coupled with the grid electrode of the second NMOS transistor, the second NMOS transistor is used for controlling the voltage in the second interface module, and the second resistor is used for controlling the current output by the current output end to the second interface module;
a first output node disposed between the source of the first NMOS transistor and the first resistor;
and a second output node arranged between the source of the second NMOS transistor and the second resistor;
wherein the current input line of the conversion unit at the uppermost stage is connected to a current source.
8. The wideband high-speed level shifter circuit of claim 7, wherein each of the current mirror modules comprises a first PMOS transistor and a second PMOS transistor, a source of the first PMOS transistor is coupled to the current input line, a drain of the first PMOS transistor is coupled to a source of the second PMOS transistor, a drain of the second PMOS transistor is coupled to the current output, and a substrate of the first PMOS transistor is connected to a substrate of the second PMOS transistor and then to the current input line.
9. A high-speed clock chip, comprising at least one wideband high-speed level shifter circuit as claimed in any one of claims 1 to 6, wherein the first input node and the second input node of each wideband high-speed level shifter circuit are connected to an external chip for receiving a set of high-speed signals transmitted from the external chip.
10. The high-speed clock chip of claim 9, wherein the high-speed signal sent by the external chip ranges from 0 to a, where a is a swing in an external operating maximum voltage interval.
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| CN102571065A (en) * | 2010-10-08 | 2012-07-11 | 索尼公司 | Level converting circuit, display device, and electronic apparatus |
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| CN109327218A (en) * | 2017-07-31 | 2019-02-12 | 深圳市中兴微电子技术有限公司 | A kind of level shift circuit and IC chip |
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| CN113595546A (en) | 2021-11-02 |
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Address after: 518000, Building 4, 1001, Shenzhen New Generation Industrial Park, No. 136 Zhongkang Road, Meidu Community, Meilin Street, Futian District, Shenzhen City, Guangdong Province Patentee after: Shenzhen Huixin Communication Technology Co.,Ltd. Address before: 518000 2701, building T2, Shenye Shangcheng (South District), No. 5001, Huanggang Road, Lianhua Yicun community, Huafu street, Futian District, Shenzhen, Guangdong Province Patentee before: Shenzhen Huixin Communication Technology Co.,Ltd. |