CN113590520B - Control method for automatically writing data in SPI system and SPI system - Google Patents
Control method for automatically writing data in SPI system and SPI system Download PDFInfo
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Abstract
The invention discloses a control method for automatically writing data in an SPI system and the SPI system, wherein the method comprises the following steps: the SPI system starts to write the data of the data buffer into the TX FIFO according to the enabling signal, and sends the data in the TX FIFO; the SPI system determines whether to send out the refreshing interrupt of the data buffer zone according to the relation between the total amount of written data and the capacity of the data buffer zone and the refreshing interrupt frequency of the data buffer zone, the CPU responds to the refreshing interrupt of the data buffer zone and fills the next batch of data to be sent into the data buffer zone, and the SPI system continues to execute the flow after receiving the signal of the refreshing completion interrupt of the CPU; or the SPI system writes the data in the data buffer area into the TX FIFO, and finishes the work after the data in the TX FIFO is sent. In the whole data writing process, the CPU only needs to respond to the refresh interrupt of the data buffer area with lower interrupt frequency, thereby greatly reducing the occupancy rate of the CPU.
Description
Technical Field
The invention relates to the technical field of data transmission, in particular to a control method for automatically writing data in an SPI system and the SPI system.
Background
The SPI protocol is used as a peripheral interface protocol with wide application, and is applied to reading/writing Flash device data, gyroscope device data, data exchange between master SPI chips and slave SPI chips and the like. Different from other applications, the corresponding data amount is huge and the consumed hardware resources are the largest in the process of reading/writing the Flash device data.
In the existing Flash device, after the CPU responds to the interrupt bit of the SPI controller, the data is written into the TX FIFO or the DMA controller is operated to write the data into the TX FIFO, and the command to be sent and the data to be written are written into the TX FIFO together. The disadvantage of this approach is apparent in that when the amount of data to be written into the Flash device is very large, but the TX FIFO depth of the SPI controller is limited, the CPU or dma will frequently respond to the state interrupt of the SPI controller to carry the data, which will greatly lose the efficiency of the system.
Disclosure of Invention
In order to solve the problems, the invention discloses a control method for automatically writing data in an SPI system and the SPI system, and the data to be written in the SPI system is cached by setting a data cache region, so that a CPU only needs to respond to the refresh interrupt of the data cache region with lower interrupt frequency in the whole data writing process, and the occupancy rate of the CPU is greatly reduced. The specific technical scheme is as follows:
A control method for automatically writing data in an SPI system comprises the following steps: s1: the SPI system starts to write the data of the data buffer into the TX FIFO according to the enabling signal, records the total amount of the written data, then sends the data in the TX FIFO, and enters step S2; s2: the SPI system determines whether to send out the data buffer refreshing interrupt according to the relation between the total amount of the written data and the capacity of the data buffer and the number of times of sending out the data buffer refreshing interrupt, if the data buffer refreshing interrupt meets the requirement, the step S3 is entered, and if the data refreshing interrupt does not meet the requirement, the step S4 is entered; s3: the SPI system sends out refreshing interrupt of the data cache area, so that the CPU responds to the refreshing interrupt of the data cache area, data is filled into the data cache area, and the SPI system enters step S1 after receiving a signal that the CPU finishes refreshing completion interrupt; s4: if the data does not meet the requirements, the SPI system writes the data in the data cache area into the TX FIFO, and finishes the work after the data in the TX FIFO is sent.
Compared with the prior art, the SPI system of the scheme continuously carries the data to be transmitted from the data buffer area to the TX FIFO in the data transmission process, and the capacity of the data buffer area can greatly exceed the depth of the TX FIFO of the SPI system, so that the CPU only needs to respond to the refresh interrupt of the data buffer area with lower interrupt frequency in the whole data writing process, the occupation rate of the CPU is greatly reduced, the load of the CPU is reduced, and the running efficiency of the system is improved.
Further, before the SPI system starts writing data, the CPU divides the data buffer area, fills the data to be sent into the data buffer area, and configures the data reading initial address, the data buffer area capacity and the data buffer area required refreshing times of the SPI system through the ahb slave module, and then configures the SPI system to enable. The data buffer area is divided by the CPU before the SPI system starts working, the size of the data buffer area can be changed according to actual conditions, and the flexibility is high.
Further, the CPU fills the data to be transmitted into the data cache area and configures the number of times of refreshing the data cache area of the SPI system according to the relation between the total amount of the data to be transmitted and the capacity of the data cache area.
Further, in step S1, the control module in the SPI system starts ahb master the enabling module according to the enabling signal, so that ahb master reads the data in the data buffer according to the data start address, and then writes the data into the TX FIFO, and records the total amount of the written data.
Further, in steps S1 and S4, during the process of transmitting the data in the TX FIFO, if the remaining data in the TX FIFO is less than or equal to the set value, the TX FIFO sends a water level trigger interrupt to trigger ahb master the module to continuously write the data in the data buffer into the TX FIFO. When the residual data in the TX FIFO is at a set value, a water level trigger interrupt is sent out, so that the SPI system writes data into the TX FIFO again, the situation that the capacity in the TX FIFO is small, all effective data read by a ahb master module cannot be received, and the effective data is lost is avoided.
Further, the SPI system completes the transmission by SPI INTERFACE module converting the data in the TX FIFO into a corresponding SPI protocol stimulus.
Further, in step S2, when the total amount of the read data is equal to the capacity of the data buffer, the SPI system determines that the relationship between the number of times of refreshing and interrupting the data buffer has been sent out, and if the number of times of refreshing and interrupting the data buffer has been sent out is smaller than the number of times of refreshing and interrupting the data buffer, the step S3 is entered; if the number of times of sending the data buffer refresh interrupt is equal to the number of times of the data buffer refresh interrupt, step S4 is entered.
Further, in step S3, after receiving the signal of finishing the refresh completion interrupt from the CPU, the SPI system sets the total amount of data read by the ahb master module to zero, and then proceeds to step S1.
The SPI system executes the control method for automatically writing data in the SPI system, and comprises SPI controllers, a CPU and a data cache area which are connected in pairs, wherein the SPI controllers are used for converting data in the data cache area into excitation meeting an SPI protocol, the CPU is used for filling the data to be written into the data cache area, and the data cache area is used for storing the data. The SPI system is used for caching the data to be written in by setting the data cache region, so that the CPU only needs to respond to the refresh interrupt of the data cache region with lower interrupt frequency in the whole data writing process, the occupancy rate of the CPU is greatly reduced, and the running efficiency of the system is improved.
Further, the SPI controller includes: the control module, the ahb master module, the SPI INTERFACE module, the TX FIFO, the RX FIFO and the ahb slave module, wherein the control module is connected with the ahb master module and the ahb slave module and is used for controlling the SPI controller to read data of the cache area; the ahb master module is connected with the control module and the TX FIFO and is used for reading the data of the data cache area and writing the data into the TX FIFO; the ahb slave module is connected with the control module, the SPI INTERFACE module, the TX FIFO and the RX FIFO and is used for configuring an internal register of the SPI system; the SPI INTERFACE module is connected with the ahb slave module, the TX FIFO and the RX FIFO and is used for converting data in the TX FIFO into corresponding SPI protocol excitation and storing data received by the SPI INTERFACE module in the RX FIFO; the TX FIFO is used for storing data to be transmitted; the RX FIFO is used to store accepted data.
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FIG. 1 is a flow chart of a control method for automatically writing data by an SPI system according to one embodiment of the present invention;
FIG. 2 is a diagram showing the effect of the SPI system automatically writing data according to one embodiment of the present invention;
Fig. 3 is a schematic diagram of an SPI controller according to an embodiment of the present invention.
Detailed Description
The present application will be described and illustrated with reference to the accompanying drawings and examples in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application. All other embodiments, which can be made by a person of ordinary skill in the art based on the embodiments provided by the present application without making any inventive effort, are intended to fall within the scope of the present application.
SPI is an abbreviation for serial peripheral interface (SERIAL PERIPHERAL INTERFACE). SPI is a high-speed, full duplex, synchronous communication bus to only occupy four lines on the pin of chip, practiced thrift the pin of chip, save space for the overall arrangement of PCB simultaneously, provide convenience. The communication principle of SPI is simple and works in master-slave mode, which usually has one master and one or more slaves, requiring at least 4 wires, in fact 3 (in unidirectional transmission). Also common to all SPI-based devices, they are MISO (master data in), MOSI (master data out), SCLK (clock), CS (chip select). MISO-Master Input Slave Output, master device data input, slave device data output; MOSI-Master Output Slave Input, master device data out, slave device data in; SCLK-Serial Clock, clock signal, generated by the master device; CS-CHIP SELECT, slave enable signal, controlled by the master. The CS is a control signal indicating whether the slave chip is selected by the master chip, that is, the master chip is effective for the operation of the slave chip only when the chip selection signal is a predetermined enable signal (high potential or low potential). This makes it possible to connect multiple SPI devices on the same bus. The data transfer between SPI devices is also called data exchange because the SPI protocol specifies that an SPI device cannot function as only a "sender" or "Receiver" during data communication. In each Clock cycle, the SPI device will send and receive one bit size data, which corresponds to the device having one bit size data being swapped. The FIFO is an abbreviation of english FIRST IN FIRST Out, which is a first-in first-Out data buffer, and is different from a normal memory in that there is no external read-write address line, so that the use is very simple, but the disadvantage is that only data can be written in sequentially, data can be read Out sequentially, the data address is completed by automatically adding 1 by an internal read-write pointer, and a specified address cannot be read or written in by the address line as in the normal memory. TX FIFO is a transmit FIFO, RX FIFO is a receive FIFO.
As shown in fig. 1, a control method for automatically writing data in an SPI system includes the steps of: s1: the SPI system starts to write the data of the data buffer into the TX FIFO according to the enabling signal, records the total amount of the written data, then sends the data in the TX FIFO, and enters step S2; s2: the SPI system determines whether to send out the data buffer refreshing interrupt according to the relation between the total amount of the written data and the capacity of the data buffer and the number of times of sending out the data buffer refreshing interrupt, if the data buffer refreshing interrupt meets the requirement, the step S3 is entered, and if the data refreshing interrupt does not meet the requirement, the step S4 is entered; s3: the SPI system sends out refreshing interrupt of the data cache area, the CPU responds to the refreshing interrupt of the data cache area and fills the next batch of data to be sent into the data cache area, and the SPI system enters step S1 after receiving a signal that the CPU finishes refreshing completion interrupt; s4: if the data does not meet the requirements, the SPI system writes the data in the data cache area into the TX FIFO, and finishes the work after the data in the TX FIFO is sent. Compared with the prior art, the SPI system of the scheme is characterized in that data to be transmitted is continuously taken out from the data buffer area for writing and transmitting, and the capacity of the data buffer area can greatly exceed the TX FIFO depth of the SPI system, so that a CPU only needs to respond to the refreshing interrupt of the data buffer area with lower interrupt frequency in the whole data writing process, the occupation rate of the CPU is greatly reduced, the load of the CPU is reduced, and the running efficiency of the system is improved.
Further, before the SPI system starts writing data, the CPU divides the data buffer area, fills the data to be sent into the data buffer area, and configures the data reading initial address, the data buffer area capacity and the number of times that the data buffer area needs to be refreshed of the SPI system through the ahb slave module, and then configures the SPI system to enable. The data buffer area is divided by the CPU before the SPI system starts working, the size of the data buffer area can be changed according to actual conditions, and the flexibility is high. And the CPU fills the data to be transmitted into the data cache area and configures the refreshing times of the data cache area of the SPI system according to the relation between the total amount of the data to be transmitted and the capacity of the data cache area.
In one embodiment, in step S1, the control module in the SPI system starts ahb master the enabling module according to the enabling signal, so that ahb master reads the data in the data buffer according to the data start address, writes the data into the TX FIFO, and records the total amount of the written data. In steps S1 and S4, during the process of transmitting the data in the TX FIFO, if the remaining data in the TX FIFO is less than or equal to the set value, the TX FIFO sends out a water level trigger interrupt to make the SPI system continuously write the data in the data buffer into the TX FIFO. When the residual data in the TX FIFO is at a set value, a water level trigger interrupt is sent out, so that the SPI system writes data into the TX FIFO again, the situation that the capacity in the TX FIFO is small, all effective data read by a ahb master module cannot be received, and the effective data is lost is avoided. The SPI system converts the data in the TX FIFO to the corresponding SPI protocol stimulus via the SPI INTERFACE module to complete the transmission.
In step S2, when the total amount of written data is equal to the capacity of the data buffer, the SPI system determines that the number of data buffer refresh interrupts has been sent, and if the number of data buffer refresh interrupts is less than the number of data buffer refresh interrupts, the step S3 is entered; if the number of times of sending out the data buffer refresh interrupt is greater than or equal to the number of times of the data buffer refresh interrupt, the step S4 is entered. In step S3, after receiving the signal that the CPU completes the refresh completion interrupt, the SPI system sets the total amount of data that has been read by the ahb master module to zero, and then proceeds to step S1. In step S4, the SPI system may determine that the data in the data buffer has been read when the total amount of the written data is equal to the capacity of the data buffer, or may determine whether the data in the data buffer has been read according to whether the SPI system can read the data from the data buffer.
The SPI system executes the control method for automatically writing data in the SPI system, the SPI system comprises SPI controllers, a CPU and a data cache region which are connected in pairs, the SPI controllers are used for converting data in the data cache region into excitation conforming to an SPI protocol, the CPU is used for filling the data to be written into the data cache region, the data cache region is used for storing the data, and the CPU opens up and refreshes a larger storage region from a ddr or sram region to serve as the data cache region. The SPI system is used for caching the data to be written in by setting the data cache region, so that the CPU only needs to respond to the refresh interrupt of the data cache region with lower interrupt frequency in the whole data writing process, the occupancy rate of the CPU is greatly reduced, and the running efficiency of the system is improved. The SPI controller includes: the control module, the ahb master module, the SPI INTERFACE module, the TX FIFO, the RX FIFO and the ahb slave module, wherein the control module is connected with the ahb master module and the ahb slave module and is used for controlling the SPI controller to read data in a cache area; the ahb master module is connected with the control module and the TX FIFO and is used for reading the data of the data cache area and writing the data into the TX FIFO; the ahb slave module is connected with the control module, the SPI INTERFACE module, the TX FIFO and the RX FIFO and is used for configuring an internal register of the SPI system; the SPI INTERFACE module is connected with the ahb slave module, the TX FIFO and the RX FIFO and is used for converting data in the TX FIFO into corresponding SPI protocol excitation and storing data received by SPI INTERFACE in the RX FIFO; the TX FIFO is used for storing data to be transmitted; the RX FIFO is used to store accepted data.
As shown in fig. 2, taking TX FIFO depth of 64 layers as an example, the total amount of data to be transmitted is 4K. Assuming that the data to be written by the SPI system is 4K and the capacity of the data buffer is 2K, the number of interrupts required to be refreshed by the CPU in response to the data buffer is 4/2=1 times during the data writing process. Before starting writing data, a CPU in the SPI system fills 2K in 4K data to be written into a data buffer area, then configures three variables of a read data starting address, data buffer area capacity and data buffer area refreshing frequency of the SPI system, configures a water level trigger value of a TX FIFO as 32, and then starts SPI enabling. Firstly, a control module in the SPI system starts ahb master to enable, a ahb master module reads the first 64 data of the data buffer area according to the data starting address and writes the data into the TX FIFO, and then starts SPI INTERFACE to enable, so that a SPI INTERFACE module converts the 64 data in the TX FIFO into corresponding SPI protocol excitation according to a clock signal. When the control module determines ahb master that the total amount of data read from the data buffer is not equal to the capacity of the data buffer, it indicates ahb master that the control module has not read all the data in the data buffer, and at this time, the control module responds to the water level trigger interrupt sent by the TX FIFO to enable the ahb master module to read 32 data from the data buffer and write the 32 data into the TX FIFO. When the control module determines ahb master that the total amount of data read from the data buffer area by the module is equal to the capacity of the data buffer area, it indicates ahb master that the module has already read all data of the data buffer area, at this time, the control module may determine whether the number of times the data buffer area has been refreshed is equal to the number of times the configured data buffer area needs to be refreshed, if the number of times the data buffer area has not reached the number of times the configured data buffer area needs to be refreshed, that is, the CPU needs to respond to the number of times the data buffer area needs to be refreshed, the control module may control ahb master module to issue a data buffer area refresh request interrupt, clear ahb master the total amount counter of data read or written in the module to enter the next cycle determination, and increment the current number of times of data buffer area refresh by 1, after all data in the TX FIFO is converted by SPI INTERFACE module, wait for the CPU to respond to the data buffer area refresh interrupt. After receiving the interruption of the data cache refreshing request, the CPU fills the remaining 2K data into the data cache and sends the interruption of the data cache refreshing completion to the SPI controller. The SPI automatically enters the data writing cycle of the next round after receiving the interrupt. When the control module determines that the number of times the data buffer is refreshed is equal to the number of times the configured data buffer is refreshed, it indicates that the data to be transmitted is all loaded into the data buffer, and the remaining data in the TX FIFO is the last data to be transmitted. The control module waits SPI INTERFACE for the last data to be sent, and then turns off the enabling of ahb master module and SPI INTERFACE module, and the automatic writing process is finished.
As shown in fig. 3, the ahb slave module is used for the CPU to configure internal registers of the SPI system, such as a read data start address, a data buffer capacity, and a data buffer refresh number in the control module. The control module is used for judging whether the ahb master module reads the complete data cache area and whether the current refreshing frequency of the data cache area reaches the configured refreshing frequency required when the TX FIFO water level trigger interrupt is generated, and controlling ahb master module to read data from the data cache area or send out the data cache area refreshing interrupt or end the process to close each module to enable according to the two judging results; the SPI INTERFACE module translates the data in the TX FIFO into corresponding SPI protocol stimulus according to the configuration values in the ahb slave module.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing embodiments are merely representative of several embodiments of the application, which are described in more detail and are not to be construed as limiting the scope of the application. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application.
Claims (9)
1. The control method for automatically writing data in the SPI system is characterized by comprising the following steps:
S1: the SPI system starts to write the data of the data buffer into the TX FIFO according to the enabling signal, records the total amount of the written data, then sends the data in the TX FIFO, and enters step S2;
S2: the SPI system determines whether to send out the data buffer refreshing interrupt according to the relation between the total amount of the written data and the capacity of the data buffer and the number of times of sending out the data buffer refreshing interrupt, if the data buffer refreshing interrupt meets the requirement, the step S3 is entered, and if the data refreshing interrupt does not meet the requirement, the step S4 is entered;
s3: the SPI system sends out refreshing interrupt of the data cache area, so that the CPU responds to the refreshing interrupt of the data cache area, data is filled into the data cache area, and the SPI system enters step S1 after receiving a signal that the CPU finishes refreshing completion interrupt;
S4: if the data is not in accordance with the requirements, the SPI system writes the data in the data cache area into the TX FIFO, and finishes the work after the data in the TX FIFO is transmitted;
In the step S2, when the total amount of the read data is equal to the capacity of the data buffer, the SPI system determines that the relationship between the number of times of refreshing and interrupting the data buffer has been sent out, and if the number of times of refreshing and interrupting the data buffer has been sent out is smaller than the number of times of refreshing and interrupting the data buffer, the step S3 is entered; if the number of times of sending the data buffer refresh interrupt is equal to the number of times of the data buffer refresh interrupt, step S4 is entered.
2. The method for automatically writing data in an SPI system according to claim 1, wherein the CPU divides the data buffer before the SPI system starts writing data, fills the data to be transmitted into the data buffer, and configures the SPI system to enable after the data buffer is configured with a read data start address, a data buffer capacity, and a number of times the data buffer needs to be refreshed by means of ahb slave.
3. The control method for automatically writing data in an SPI system according to claim 2, wherein the CPU fills data to be transmitted into the data buffer and configures the number of times the data buffer of the SPI system needs to be refreshed according to a relationship between the total amount of data to be transmitted and the capacity of the data buffer.
4. The method according to claim 1, wherein in step S1, the control module in the SPI system starts ahb master the enabling module according to the enabling signal, and causes ahb master to read the data in the data buffer according to the data start address, then write the data into the TX FIFO, and record the total amount of the written data.
5. The method according to claim 1, wherein in steps S1 and S4, if the remaining data in the TX FIFO is less than or equal to the set value during the process of transmitting the data in the TX FIFO, the TX FIFO sends a water level trigger interrupt to trigger ahb master the module to continuously write the data in the data buffer into the TX FIFO.
6. The method for automatically writing data to an SPI system of claim 5, wherein the SPI system performs the transmitting by means of SPIINTERFACE module converting the data in the TX FIFO into a corresponding SPI protocol stimulus.
7. The method for controlling automatic data writing in an SPI system according to claim 1, wherein in step S3, after receiving a signal indicating that the CPU completes the refresh completion interrupt, the SPI system resets the total amount of data that has been read by the ahb master module, and then proceeds to step S1.
8. An SPI system performing the control method of automatically writing data by the SPI system according to any one of claims 1 to 7, said SPI system comprising: the SPI controller is used for converting data in the data cache area into excitation meeting SPI protocol, the CPU is used for filling data to be written into the data cache area, and the data cache area is used for storing the data.
9. The SPI system of claim 8, wherein the SPI controller comprises: control module, ahb master module, SPIINTERFACE module, TX FIFO, RX FIFO and ahb slave module, wherein,
The control module is connected with the ahb master module and the ahb slave module and is used for controlling the SPI controller to read data of the cache area;
The ahb master module is connected with the control module and the TX FIFO and is used for reading the data of the data cache area and writing the data into the TX FIFO;
the ahb slave module is connected with the control module, the SPIINTERFACE module, the TX FIFO and the RX FIFO and is used for configuring an internal register of the SPI system;
The SPIINTERFACE module is connected with the ahb slave module, the TX FIFO and the RX FIFO and is used for converting data in the TX FIFO into corresponding SPI protocol excitation and storing data received by the SPIINTERFACE module in the RX FIFO;
the TX FIFO is used for storing data to be transmitted;
the RX FIFO is used to store the received data.
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