CN113590517A - Computer supporting remote control - Google Patents

Computer supporting remote control Download PDF

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Publication number
CN113590517A
CN113590517A CN202110875950.9A CN202110875950A CN113590517A CN 113590517 A CN113590517 A CN 113590517A CN 202110875950 A CN202110875950 A CN 202110875950A CN 113590517 A CN113590517 A CN 113590517A
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China
Prior art keywords
processor
module
computer
interface
debugging
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CN202110875950.9A
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Chinese (zh)
Inventor
公健
梁记斌
夏伟强
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Xian Chaoyue Shentai Information Technology Co Ltd
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Xian Chaoyue Shentai Information Technology Co Ltd
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Priority to CN202110875950.9A priority Critical patent/CN113590517A/en
Publication of CN113590517A publication Critical patent/CN113590517A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0042—Universal serial bus [USB]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Debugging And Monitoring (AREA)

Abstract

A computer supporting remote control, comprising a processor, a debugging module, wherein: the debugging module is connected with the processor through a JTAG debugging interface, and is configured to acquire the instruction type executed in the processor and execute the operation management of the processor based on the instruction type. According to the computer supporting remote control, the debugging module is additionally arranged on the hardware layer to monitor the running of the CPU, and the running working mode of the CPU is changed based on the monitored running state of the CPU so as to reduce the power consumption of the CPU, further optimize the heating accumulation of the CPU and improve the running stability of the CPU.

Description

Computer supporting remote control
Technical Field
The invention belongs to the field of computers, and particularly relates to a computer supporting remote control.
Background
The existing all-in-one machines on the market generally adopt an Intel processor or an AMD processor of an X86 architecture. There are few integrated machines that use domestic processors. The Shenwei 421 processor is a high-performance general processor with 64-bit word length RISC architecture developed by China independently, and 4 isomorphic new generation Shenwei Core3A cores, 8MB three-level shared Cache, two paths of 64-bit DDR3 storage controllers, two paths of third generation standard PCI-E interfaces, a maintenance interface supporting debugging and management and a test interface conforming to IEEE1149.1 standard are integrated in a single chip.
However, since the domestic chip is in the initial stage, there are many schemes for optimizing the CPU of the x86 architecture, which cannot be adapted or transplanted to the processor platform of the shenwei 421 for use due to the difference of the architecture. Without being able to tune the performance of the explain 421 processor platform to a reliable and good condition. Due to the performance difference of the domestic CPU, the use scene is less, the hardware ecology and the software ecology are imperfect, a series of problems such as poor user experience (serious heating, system blockage caused by insufficient compatibility optimization when a domestic operating system is matched) and the like are caused, the development and popularization construction of the domestic CPU and the operating system are seriously influenced, and the problem that the CPU runs slowly due to frequency reduction caused by heating is mostly caused.
Therefore, a solution that can optimize the processor platform of the claim 421 or the claim 421 processor is needed.
Disclosure of Invention
In order to solve the above problems, the present invention provides a computer supporting remote control, including a processor and a debugging module, wherein:
the debugging module is connected with the processor through a JTAG debugging interface, and is configured to acquire the instruction type executed in the processor and execute the operation management of the processor based on the instruction type.
In some embodiments of the present invention, the debugging module includes a USB interface, and the USB interface is connected to the USB interface of the computer and configured to send and/or receive debugging information of the processor and program information executed by the computer to an operating system in the computer.
In some embodiments of the invention, the debugging module further comprises a network communication interface configured to send debugging information of the processor and/or program information run by the computer to a remote analysis server.
In some embodiments of the invention, the debug module is configured to send a deep sleep instruction to an idle or low usage core of the processor based on debug information of the processor and/or program information run by the computer.
In some embodiments of the invention, the debug module is further configured to send a light sleep instruction to an idle or low usage core of the processor based on debug information of the processor and/or program information run by the computer.
In some embodiments of the invention, the debugging module is further configured to shut down components of the processor according to debugging information of the processor and/or program information run by the computer.
In some embodiments of the invention, the debugging module is further configured to reduce the instruction processing speed of the processor according to debugging information of the processor and/or program information executed by the computer.
In some embodiments of the present invention, the system further comprises a memory module, the memory module being connected to the processor via a DIMM interface; and
the processor passes through I2And the C interface is connected with the memory module and is used for acquiring the frequency, the voltage and the time sequence of the memory.
In some embodiments of the present invention, the mobile terminal further includes a PCIE expansion module, where the PCIE expansion module is configured to:
the system is connected with the processor through an 8Lane PCIE interface and is used for realizing communication with the processor;
the display card is connected with an HD7450 display card through an 8Lane PCIE interface;
the storage module is connected with the storage module through a 2Lane PCIE interface, and the storage module provides an HDD (hard disk drive) disk interface and a MiNi SATA (serial advanced technology attachment) interface for the outside;
the network communication module is connected through a 2Lane PCIE interface, and the communication module provides a 1000M RJ45 interface;
the USB conversion module is connected with the USB conversion module through one path of 2Lane PCIE interface, and the USB conversion module provides a plurality of USB interface supports for the outside.
In some embodiments of the present invention, the apparatus further includes a UART serial port module, and the UART serial port module is connected to the USB conversion module and configured to provide UART serial port support.
According to the computer supporting remote control, the debugging module is additionally arranged on the hardware layer to monitor the running of the CPU, and the running working mode of the CPU is changed based on the monitored running state of the CPU so as to reduce the power consumption of the CPU, further optimize the heating accumulation of the CPU and improve the running stability of the CPU.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a diagram of a computer architecture according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
As shown in fig. 1, to solve the above problem, the present invention provides a computer supporting remote control, including a processor and a debugging module, wherein:
the debugging module is connected with the processor through a JTAG debugging interface, and is configured to acquire the instruction type executed in the processor and execute the operation management of the processor based on the instruction type.
In this embodiment, the processor used by the computer supporting remote control provided by the present invention is a shenwei 421 processor, the shenwei 421 processor is a high-performance general processor with a 64-bit word length RISC architecture, and 4 homogeneous cores of a new generation shenwei Core3A Core, an 8MB three-level shared Cache, two 64-bit DDR3 memory controllers, two third-generation standard PCI-E interfaces, a maintenance interface supporting debugging and management, and a test interface conforming to the IEEE1149.1 standard are integrated in a single chip. The maintenance interface based on the Shenwei 421 processor supports debugging and management, so that the regulation and control of the processor are possible.
Specifically, as shown in the structure diagram of fig. 1, the debugging module 1 is connected to the process 2 through the JTAG debugging interface, and the debugging module 1 can obtain the instruction executed in the processor 2 in real time through the JTAG debugging interface when the processor 2 runs (i.e., debugging information, which is obtained through the JTAG debugging interface, not only the executed instruction, but also a lot of other information, such as whether an error occurs during instruction execution or not, is caused by some reason to block execution. And obtains the operating state of each core of the processor. Further, according to the obtained instruction type executed by the processor 2 and the working state of each core of the processor 2, a corresponding instruction is sent to the processor 2.
In some embodiments of the present invention, the debugging module includes a USB interface, and the USB interface is connected to a USB interface of the computer and configured to send debugging information to an operating system in the computer and/or receive program information executed by the computer by the processor.
In this embodiment, in order to facilitate communication with an operating system in a computer, a USB interface is further provided in the debugging module, the debugging module is connected to the USB interface on the computer through the USB interface, and by installing a corresponding control program in the operating system, the type of the instruction executed by the processor 2, which is acquired by the debugging module 1 through the JTAG, can be sent to the control program of the operating system, so that the operating system can execute a corresponding power management plan. Meanwhile, the operating system can send the process information of all programs under the operating system and the detailed information of the program being executed to the debugging module 1 through the USB interface. The debug module may formulate a corresponding command governing the operation of the processor 2 based on the program being run in the operating system.
In some embodiments of the present invention, the debugging module 2 further comprises a network communication interface configured to send debugging information of the processor and/or program information run by the computer to a remote analysis server.
In this embodiment, the debugging module 1 is further provided with a network communication interface. In order to more accurately manage the operating state of the processor 2, the debugging module 1 needs to continuously update the corresponding management policy for the processor 2, and also needs to count the types of instructions executed by the processor 2 and acquired by the debugging module 1 and send the executed program information acquired from the operating system to the control policy analysis center of the remote server through the network communication interface. The control policy analysis center makes a corresponding policy for managing and controlling the processor 2 according to the type of the instruction executed by the collection processor and the program running in the operating system.
In some embodiments of the invention, the debug module is configured to send a deep sleep instruction to an idle or low usage core of the processor based on debug information of the processor and/or program information run by the computer.
In this embodiment, when it is detected that the number of instructions executed by the processor 2 in a unit time in the debug information is small or the usage amount of the CPU core in the running program transmitted from the operating system is small, the deep sleep instruction may be transmitted to the idle or low usage core.
Specifically, the processor 2 used in the present invention is a Shenwei 421 processor, which has 4 cores, and when detecting that the total number of instructions executed by the current computer is lower than 1/4 of the average peak instruction number of a single core, sends a deep sleep instruction to the other three cores. The Shenwei 421 processor contains 4 identical cores, and some of the cores should be put to sleep if they are in a no-load state. The core or external system may issue a sleep interrupt to any core via a maintenance command so that these unloaded cores are in a sleep state. The core in the sleep state is in the reset state and maintains a lower clock frequency (only one eighth of the maintenance clock frequency). Once the core needing to be asleep recovers the working state, the non-asleep core or the external system can send a wake-up interrupt to the sleep core, so that the sleeping core can recover the normal working frequency, the reset is finished, the initialization is carried out again, the operating system is guided, and the normal working state is recovered. The core of the sleep state has little dynamic power consumption.
In some embodiments of the invention, the debug module is further configured to send a light sleep instruction to an idle or low usage core of the processor based on debug information of the processor and/or program information run by the computer.
In the present embodiment, the total number of instructions executed in the processor 2 in the debug information acquired by the debug module 1 through the JTAG debug interface is higher than 1/4 of the average peak instruction number but lower than the average peak instruction number of a single core, and at the same time, the operation speed (mainly, the instruction number) of the processor 2 is not stable within 5 minutes, in which case the debug module may send a light sleep instruction to an idle processor, in which case each pipeline inside the core of the processor 2 is in a stalled state, and thus, there is only a small amount of clock dynamic power consumption. Any interrupt sent to the core that is sleeping light can quickly bring it back to working.
In addition, the setting of the deep sleep and the light sleep of the idle core needs to consider the influence of programs in the operating system, and if a program requiring the use of multiple processes is encountered, whether a deep sleep instruction or a light sleep instruction needs to be sent to the idle core needs to be measured according to the number of the processes. For example, when a Python-like program starts multiple processes, the instructions executed by the multiple processes may be very few, but the processes are required to maintain the normal operation of some functions of the program, and any sleep instructions are prohibited from being issued in this state.
In some embodiments of the invention, the debugging module is further configured to shut down components of the processor according to debugging information of the processor and/or program information run by the computer.
In this embodiment, since the floating point unit and the SIMD unit in the core of the Shenwei 421 processor can be separately turned off, when the program run by the core does not need the floating point or SIMD function, the floating point unit or the SIMD unit can be turned off to save the running power consumption. And the floating point unit and SIMD unit may be dynamically turned on and off.
Specifically, the debugging module 1 acquires an instruction running in the processor 2 and an instruction to be executed in a register in real time through the JTAG interface, and opens the floating point unit or the SIMD unit before the instruction to be executed is executed if the instruction to be executed is found to have an instruction that needs to be executed by the floating point unit or the SIMD unit. The floating point or SIMD unit is turned off again after execution. The process sends a corresponding interrupt instruction to a floating point unit or a SIMD unit of a core of a processor through a JTAG interface by means of the debugging module 1 to turn on or off the corresponding floating point unit or SIMD unit. Since the debugging module 1 is an independent debugging control system, the time granularity of the instructions can be extremely small, and the normal execution of the processor 2 is hardly influenced.
In addition, because the UBS interface of the debugging module 1 communicates with the operating system, the UBS interface acquires program information in the operating system and sends the program information and instruction information in the debugging information to the control policy analysis center of the remote analysis server, the control policy analysis center has certain learning capability, and can analyze the large running data (the running of some programs causes the number of some instructions to increase or some instructions to appear) of the programs in a plurality of computers with the debugging module 1, and give instruction set information related to the running of the corresponding programs and send the instruction set information to the debugging module 1 located in each computer, and the debugging module 1 receives the instruction set related to the corresponding programs and establishes the comparison relation list. And summarizing the executed instructions when each program is executed to establish a one-to-many mapping relation. When the corresponding application program is acquired from the operating system, whether the program relates to a floating point instruction or an instruction relating to a SIMD unit can be immediately known, and whether the monitoring of the floating point unit or the SIMD unit is started or not is judged based on the result.
Specifically, after obtaining the running program from the USB interface, the obtained running program is matched with the received list of application programs, and it is further determined whether the instructions related to the program running in the current computer operating system include using a floating point unit or a SIMD unit, and if the program running in the current computer operating system does not include the program related to the floating point unit or the SIMD unit, the debugging module 1 does not need to monitor the floating point instructions or the instructions related to the SIMD unit in the processor in real time. To reduce the amount of tasks of the debug module 1.
Further, when there is an unknown or unmatched application in the list of applications acquired from the operating system of the current computer (the application has not been analyzed by the control policy analysis center). I.e., it is not yet known whether the application is executing using a floating point unit or a SIMD unit. The debug module 1 needs to monitor the instruction executed by the processor 2 when the unknown program runs, and temporarily record the instruction in an instruction list related to the running of the unknown program when the instruction which is not included in the known program exists. And sends the type of instructions executed in the processor 2 when the unknown program is running to a policy analysis center in a remote analysis server for analysis. To analyze whether the execution of the unknown program involves the use of floating point units or SIMD units.
Further, since the unknown program is running, there may be other programs that need to use floating point units or SIMD units. The network interface benefiting from the debugging module may send instructions running in the various cores of the processor 1 and a list of programs in the operating system to the policy analysis center. The policy analysis center can quickly analyze whether the operation of the unknown program needs the floating point component or the SIMD component from the debugging information and the operating program information sent by a plurality of different debugging modules 1.
Specifically, in the policy analysis, received instructions and program information are analyzed, if all known programs do not include floating point instructions or instructions related to a SIMD unit, and the instructions executed by the processor are found to include floating point instructions or instructions related to the SIMD unit, and if the unknown program is related to the floating point unit or the SIMD unit, then floating point instructions or instructions related to SIMD are added to an instruction list of the program.
In some embodiments of the invention, to save execution speed in debug mode, when a program related to floating point instructions or instructions of a SIMD unit generates its instruction set, other instructions or other programs are directly ignored, and only the program related to floating point instructions or instructions of the SIMD unit is described. Therefore, when the debugging module 1 receives the program list from the operating system, if there is no program corresponding to the instruction related to the floating point instruction or the SIMD unit in the program list, it can directly recognize that the program running in the current operating system does not use the floating point unit and the SIMD unit. Thus, the floating point and SIMD components of each core in processor 2 may be turned off directly to reduce the dynamic power consumption of the processor. By simplifying the way in which all programs and their operating instruction sets are recorded to only record programs relating to the use of floating point units and/or SIMD units, the operating efficiency of the debugging module 1 may be greatly reduced in some cases.
In some embodiments of the present invention, perhaps because the execution of the program does not involve a flow that requires a floating point unit and/or a SIMD unit, a floating point instruction or an instruction that involves SIMD may suddenly appear during the execution of the program classified as not requiring a floating point unit and/or a SIMD unit, which may cause the program to run incorrectly, at which point the debug mode deletes the instruction that has made the mistake by an interrupt command, and monitors the program running error information from the operating system, and adds a floating point instruction or an instruction that involves a SIMD unit to the execution instruction list corresponding to the program that has made the mistake.
In some embodiments of the invention, the debugging module is further configured to reduce the instruction processing speed of the processor according to debugging information of the processor and/or program information executed by the computer.
In this embodiment, when the debug module 1 detects that the number of instructions to be executed by the running program of the current computer is not higher than 80% of the average peak instruction number of a single core, and there are a plurality of programs in the program that need independent processes, but the utilization rate of the plurality of processes of the program for the core is not high, the debug module may send an instruction for reducing the instruction processing speed to the processor 2. Reducing the instruction pipeline processing speed of the processor 2. Thereby reducing the dynamic operation power consumption of the core.
In some embodiments of the present invention, the system further comprises a memory module, the memory module being connected to the processor via a DIMM interface; and
the processor passes through I2And the C interface is connected with the memory module and is used for acquiring the frequency, the voltage and the time sequence of the memory.
In this embodiment, as shown in fig. 1, a processor adopted by a computer supporting remote control according to the present invention is a charpy 421 processor, and can pass through I of the charpy 421 processor2The C interface obtains information stored in the SPD of the memory disposed in the DIMM slot. I is2The C interface is embedded in the DIMM slot, and the SPD of the memory can be connected without other jumper wires.
In some embodiments of the present invention, the apparatus further includes a PCIE expansion module 3, where the PCIE expansion module 3 is configured to:
the system is connected with the processor 2 through an 8Lane PCIE interface and used for realizing communication with the processor 2;
the display card is connected with the HD7450 display card 8 through an 8Lane PCIE interface;
the storage module 6 is connected with a path of 2Lane PCIE interface, and the storage module 6 provides an HDD (hard disk drive) disk interface and a MiNi SATA (serial advanced technology attachment) interface for the outside;
the network communication module 7 is connected through a 2Lane PCIE interface, and the communication module provides a 1000M RJ45 interface;
the USB conversion module 4 is connected through a path of 2Lane PCIE interface, and the USB conversion module 4 provides a plurality of USB interface supports for the outside.
In this embodiment, the PCIE expansion module 3 uses a PEX8632 chip to support an uplink PCIE x8 signal, a downlink PCIE x8 signal, 2 PCIE x2 signals, and 1 PCIE x4 signal. Downstream PCIE signals: one PCIEx8 signal is connected with the HD7450 video card slot; one path of PCIEx2 signal is connected to a storage module, the chip of the storage module is 88SE9215 and is respectively connected to an HDD hard disk slot and a MiNi SATA hard disk slot through the chip expansion; one path of PCIEx1 signal is connected to the network communication module 7, and the network communication module 7 adopts an Intel 82574 network card and is connected to an RJ45 network port; one path of the pcie x2 signal is connected to the USB conversion module 4, the USB conversion module 4 uses a UDP720201 chip to externally provide USB serial port support, and is connected to a USB3.0 connection to externally provide a plurality of USB interfaces, a USB camera module, and a microphone audio module, and receives and sends an audio signal to a multimedia device outside the computer.
In some embodiments of the present invention, the apparatus further includes a UART serial port module, and the UART serial port module is connected to the USB conversion module and configured to provide UART serial port support.
In this embodiment, the computer supporting remote control provided by the present invention further extends a UART serial port to support the UART serial port function, and is implemented by the UART serial port module 8 connected to the USB conversion module 4, and the UART serial port module 8 is implemented by an FT4232 chip, which can convert a USB serial interface into a UART serial interface.
According to the computer supporting remote control, the debugging module is additionally arranged on the hardware layer to monitor the running of the CPU, and the running working mode of the CPU is changed based on the monitored running state of the CPU so as to reduce the power consumption of the CPU, further optimize the heating accumulation of the CPU and improve the running stability of the CPU.
In addition, the debugging module disclosed by the invention realizes the accurate regulation and control of the operation of the Shenwei 421 processor by combining the operation state of the Shenwei 421 processor and the operation program in the operating system, thereby effectively reducing the phenomena of power waste and heating caused by that a plurality of cores of the processor are in a normal working mode or certain components with low use rate and high power consumption are in an open state along with the working state of the cores of the processor for a long time when the Shenwei 421 processor operates. The thermal stability of the Shenwei 421 processor is improved.

Claims (10)

1. A computer supporting remote control, comprising a processor, a debugging module, wherein:
the debugging module is connected with the processor through a JTAG debugging interface, and is configured to acquire the instruction type executed in the processor and execute the operation management of the processor based on the instruction type.
2. The computer of claim 1, wherein the debugging module comprises a USB interface, and the USB interface is connected to the USB interface of the computer and configured to send debugging information of the processor to an operating system in the computer and/or receive program information executed by the computer.
3. The computer of claim 2, wherein the debugging module further comprises a network communication interface configured to send debugging information of the processor and/or program information executed by the computer to a remote analysis server.
4. The computer of claim 3, wherein the debug module is configured to send a deep sleep instruction to an idle or low usage core of the processor according to debug information of the processor and/or program information executed by the computer.
5. The computer of claim 3, wherein the debug module is further configured to send a light sleep instruction to an idle or low usage core of the processor according to debug information of the processor and/or program information executed by the computer.
6. The computer of claim 3, wherein the debugging module is further configured to shut down components of the processor according to debugging information of the processor and/or program information executed by the computer.
7. The computer of claim 3, wherein the debugging module is further configured to reduce the instruction processing speed of the processor according to debugging information of the processor and/or program information executed by the computer.
8. The computer of claim 1, further comprising a memory module coupled to the processor via a DIMM interface; and
the processor passes through I2And the C interface is connected with the memory module and is used for acquiring the frequency, the voltage and the time sequence of the memory.
9. The computer of claim 1, further comprising a PCIE expansion module configured to:
the system is connected with the processor through an 8Lane PCIE interface and is used for realizing communication with the processor;
the display card is connected with an HD7450 display card through an 8Lane PCIE interface;
the storage module is connected with the storage module through a 2Lane PCIE interface, and the storage module provides an HDD (hard disk drive) disk interface and a MiNi SATA (serial advanced technology attachment) interface for the outside;
the network communication module is connected through a 2Lane PCIE interface, and the communication module provides a 1000M RJ45 interface;
the USB conversion module is connected with the USB conversion module through one path of 2Lane PCIE interface, and the USB conversion module provides a plurality of USB interface supports for the outside.
10. The computer of claim 9, further comprising a UART serial module, the UART serial module being coupled to the USB conversion module and configured to provide UART serial support.
CN202110875950.9A 2021-07-30 2021-07-30 Computer supporting remote control Pending CN113590517A (en)

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JPH02120919A (en) * 1988-10-31 1990-05-08 Nec Home Electron Ltd Sleep mode circuit for personal computer
JPH07306800A (en) * 1994-05-13 1995-11-21 Mitsubishi Electric Corp Debugging system
CN101241390A (en) * 2007-02-07 2008-08-13 华硕电脑股份有限公司 Multi- core processor efficiency regulation method
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