CN113576479A

CN113576479A - Emotion detection and regulation system based on electroencephalogram

Info

Publication number: CN113576479A
Application number: CN202110741425.8A
Authority: CN
Inventors: 刘铁军; 郜东瑞; 史许倩; 来丹维; 林书宇; 王钰潇; 应少飞; 王林; 秦云; 尧德中
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2021-07-01
Filing date: 2021-07-01
Publication date: 2021-11-02

Abstract

The invention discloses an emotion detection and regulation system based on electroencephalogram, which comprises a Power.Schdoc power supply module, an ADC.Schdoc front-end analog signal acquisition module, an ARM system control module, an FPGA.Schdoc signal processing module and a Music _ Player.Schdoc module, wherein the Power.Schdoc power supply module is electrically connected with an isolation power supply circuit, the isolation power supply circuit is electrically connected with an isolation chip, the Power.Schdoc power supply module is electrically connected with a voltage reduction circuit, and the ADC.Schdoc front-end analog signal acquisition module is electrically connected with an analog front-end signal amplification filter circuit; the invention is a set of customized complete embedded equipment and has the advantages of portability, small volume, simple operation and the like; the invention adopts the FPGA chip to process data, thereby having very high real-time performance; the invention adopts the dry electrode cap to collect the brain electricity, avoids electrode paste before use, and is very convenient to use. The invention has a friendly UI interface, and the user can customize and regulate the personalized emotion.

Description

Emotion detection and regulation system based on electroencephalogram

Technical Field

The invention relates to the technical field of medical instruments, in particular to an electroencephalogram-based emotion detection and regulation system.

Background

In recent years, the leapfrog event of students in colleges and universities in China frequently occurs, more and more people in society begin to see psychologists, and the psychological diseases gradually become very common diseases. Most of the psychological diseases of people are caused by the fact that the emotional disorder of people is not perceived, and the people are in negative emotion for a long time and are not regulated in time. Therefore, it is necessary to produce a device that can monitor changes in mood in real time and can perform mood adjustments.

The brain is one of the most important and complex organs of the human body, is the most advanced part of the nervous system, and governs all the advanced nerve activities of the human body. The brain electrical signal is a signal which is generated by the brain and can reflect the brain activity in real time and objectively. The brain electrical signal is used as a biological electrical signal which is generated by the human brain and can reflect the activity characteristics of the brain, and the brain activity information contained in the brain electrical signal is very rich.

In order to better prevent psychological diseases, the invention designs a system for collecting electroencephalogram and detecting emotion according to the electroencephalogram. Meanwhile, in order to better regulate the negative emotion of people, the music player plays corresponding music according to the emotion detection result to induce positive emotion.

Disclosure of Invention

The invention aims to provide an electroencephalogram-based emotion detection and adjustment system to solve the problems in the background art.

In order to achieve the purpose, the invention provides the following technical scheme:

the utility model provides an emotion detection and governing system based on brain electricity, includes power.Schdoc power module, ADC.Schdoc front end analog signal collection module, ARM system control module, FPGA.Schdoc signal processing module and Music _ Player.Schdoc module, the inside electric connection of power.Schdoc power module has isolation power supply circuit, the inside electric connection of isolation power supply circuit has isolation chip, the inside electric connection of power.Schdoc power module has step-down circuit, the inside electric connection of ADC.Schdoc front end analog signal collection module has analog front end signal amplification filter circuit, the inside electric connection of ADC.Schdoc front end analog signal collection module has signal analog-to-digital conversion circuit, the inside electric connection of FPGA.Schdoc signal processing module has the FPGA chip.

As a further scheme of the invention: the isolation power supply circuit is a 3.3V isolation power supply circuit, and the isolation chip has four channels in total.

As a still further scheme of the invention: the voltage reduction circuit is a voltage reduction circuit for converting 5V into 3.3V, 2.5V and 1.2V.

As a still further scheme of the invention: the analog front-end signal amplification filter circuit is composed of a chip U15, a resistor R56, a resistor R61, a resistor R65, a capacitor C51, a capacitor C55, a chip U16B, a resistor R59, a resistor R64, a capacitor C56, a chip U16A, a resistor R54, a resistor R55, a resistor R60, a capacitor C50, a capacitor C53, a capacitor C54, a capacitor C58, a chip U14, a resistor R53, a resistor R57, a resistor R58, a resistor R62, a resistor R66, a capacitor C48, a capacitor C49, a capacitor C52, a capacitor C57, a capacitor C59, a chip U53, a resistor R174, a capacitor C180, a resistor R181, a capacitor R176, a capacitor C182, a resistor R177 and a capacitor C183.

As a still further scheme of the invention: the signal analog-to-digital conversion circuit is composed of a chip ADS 1299.

As a still further scheme of the invention: ARM control module internal electrical connection has the ARM chip, the ARM chip is STM32F103, and crystal oscillator Y3, electric capacity C298, electric capacity C300 constitute the master control chip.

Compared with the prior art, the invention has the beneficial effects that:

1. the invention is a set of customized complete embedded equipment and has the advantages of portability, small volume, simple operation and the like;

2. the invention adopts the FPGA chip to process data, thereby having very high real-time performance;

3. the invention adopts the dry electrode cap to collect the brain electricity, avoids electrode paste before use, and is very convenient to use.

4. The invention has a friendly UI interface, and the user can customize and regulate the personalized emotion.

Drawings

FIG. 1 is a block diagram of the system of the present invention;

FIG. 2 is a schematic diagram of a 5V isolated power supply circuit of the present invention;

FIG. 3 is a schematic diagram of a 5V to 3.3V, 2.5V, 1.2V circuit of the present invention;

FIG. 4 is a schematic diagram of an analog front end signal amplification filter circuit of the present invention;

FIG. 5 is a schematic diagram of a signal analog-to-digital conversion circuit of the present invention;

FIG. 6 is a schematic circuit diagram of a portion of the FPGA signal processing of the present invention;

FIG. 7 is a schematic diagram of an ARM control portion of the present invention;

FIG. 8 is a block diagram illustrating the structure of the present invention;

FIG. 9 is a flow chart of EEG signal processing according to the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1 to 9, in an embodiment of the present invention, an emotion detecting and adjusting system based on electroencephalogram includes a power.schdoc power module, an adc.schdoc front-end analog signal acquisition module, an ARM system control module, an fpga.schdoc signal processing module, and a Music _ player.schdoc module, where the power.schdoc power module is electrically connected to an isolation power circuit, the isolation power circuit is electrically connected to an isolation chip, the power.schdoc power module is electrically connected to a voltage reduction circuit, the adc.schdoc front-end analog signal acquisition module is electrically connected to an analog front-end signal amplification filter circuit, the adc.schdoc front-end analog signal acquisition module is electrically connected to a signal analog-to-digital conversion circuit, and the fpga.schdoc signal processing module is electrically connected to an FPGA chip.

The working principle of the invention is as follows: as shown in the first figure, the power.schdoc power module supplies power to the whole system; the SchDoc front-end analog signal acquisition module is used for amplifying and filtering signals and converting analog signals into digital signals; the ARM system control module is responsible for logic control of the whole system, digital signals collected by the ADC are sent to the FPGA for operation, and the operated data are used for emotion classification and determining whether emotion adjustment is performed or not; the Schdoc signal processing module is responsible for receiving electroencephalogram signals sent by the ARM through the USB, processing the signals, extracting features and sending results back to the ARM; the Music _ player.schdoc module is responsible for receiving the Music electric signals transmitted by the ARM module, converting the Music electric signals into Music sound signals and adjusting the tone colors.

As shown in fig. 2, in the 3.3V isolated power supply circuit, the total four channels of the isolated chip, pin 1 and pin 8 correspond to each other, and respectively correspond to 3.3V of the digital part and 3.3V of the analog part, and capacitors with a size of 0.1uf are selected for filtering for C1 and C2; the No. 2 pin and the No. 7 pin correspond to a chip pin of the USB DM and an interface pin of the USB DM respectively, wherein the USB DM is connected with a pull-up resistor of 1K, so that the USB equipment works in a high-speed mode; the No. 3 pin corresponds to the No. 6 pin and corresponds to a chip pin of the USB DP and an interface pin of the USB DP respectively; pin No. 4 and pin No. 5 correspond to digital ground and analog ground, respectively.

As shown in fig. 3, the voltage step-down circuit for 5V to 3.3V, 2.5V, and 1.2V, wherein the chip 1, the capacitors C3, C4, C5, C6, the resistors R2, R3, and the inductor L1 together form a circuit for 5V to 3.3V; the chip U2 and the capacitors C7, C8 and C9 form a circuit of converting 5V into 2.5V; the chip 2, the chip U3, the resistor R-1, the capacitor C10, the capacitor C11, the capacitor C12, the capacitor C13, the capacitor C14 and the capacitor C15 form a 5V-to-2.5V circuit; the chip U4, the resistor R4, the capacitors C16, C17, C18 and C19 jointly form a circuit converting 5V to 1.2V; two inductors of 3.3nH, L2 and L3, are respectively connected to AGND, PGND and DGND for filtering.

As shown in fig. 4, in the analog front-end signal amplifying and filtering circuit, a chip U15, resistors R56, R61, R65, capacitors C51, and C55 jointly form a front-end differential-to-single-end amplifying circuit, the amplification factor is determined by R61, and the circuit subtracts a moving electrode from a reference electrode and amplifies the difference; the chip U16B, the resistors R59 and R64 and the capacitor C56 form an integrating circuit, the effect of a high-pass filter is achieved, and low-frequency noise of signals is filtered; the chip U16A, the resistors R54, R55 and R60, the capacitors C50, C53, C54 and C58 form a low-pass filter together, and high-frequency noise in signals is filtered; the chip U14 and the resistors R53, R57, R58, R62, R66, the capacitors C48, C49, C52, C57 and C59 jointly form a single-ended-to-differential circuit, and single-ended signals after signal processing are converted into differential signals for analog-to-digital conversion of selected ADCs. As in fig. 4, chip U53 is used for ESD and overvoltage protection, R174 and C180, R175 and C181, R176 and C182, and R177 and C183 all constitute low pass filters.

As shown in fig. 5, the signal analog-to-digital conversion circuit is mainly composed of a chip ADS1299, and eight differential analog input signals: IN1N-IN 1P-IN 8N-IN8P, the front end of each channel forms a low-pass filter by a resistor and a capacitor; the digital part of the chip is powered by 3.3V, and the analog part of the chip is powered by a +/-2.5V double power supply; the pins VREFP and VREFN jointly determine the reference voltage of the chip, and 2.5V reference voltage is selected in the invention; the pins SCLK, DIN, DOUT and CS jointly form four signal pins of an SPI protocol, and the four signal pins are connected with four corresponding pins of an ARM, so that the ARM main control chip can configure the ADC chip ADS1299 and read electroencephalogram data; the pins START and RESET form a control part of the ADS1299, and control whether the ADS1299 STARTs working or not and whether the operation is RESET or not; the DRDY pin is a ready signal pin and is responsible for informing the main control chip that data conversion is finished and reading data, and the pin is connected with an R73 resistor of a resistor 10K and is responsible for pulling up a signal because the ready signal is a falling edge; in the figure, the capacitors C74, C83, C87, C88, C95, C174, C175, C176, C180, C181, C198, C201, C202 and C203 are all filter capacitors.

As shown in fig. 6, the FPGA chip in the FPGA signal processing circuit transmits data with the ARM control part through the TX-FPGA, the RX-FPGA; the FPGA programming uses a Verlog-HDL language to realize the further processing of the electroencephalogram data and the extraction of emotional characteristics.

As shown in fig. 7, an ARM chip in the ARM control part circuit selects STM32F103, a crystal oscillator Y3, capacitors C298 and C300 to form a clock circuit of a main control chip; the whole chip is powered by 3.3V; the ARM control part is mainly responsible for logic control of the whole system and generation of time sequences of an external ADC chip, so that electroencephalogram data are read from the external high-precision ADC, and the electroencephalogram data are processed by the FPGA and then processed by the ARM control part.

As shown in fig. 8, the user performs personalized custom setting through the human-computer interaction module, and turns on or off the whole system. After the electrode cap is worn by a user, personalized setting can be carried out, and after the personalized setting is finished, the system can be selected to be started. At the moment, an electroencephalogram signal is collected by an electroencephalogram signal collecting module, the electroencephalogram signal collecting module mainly comprises a front-end analog circuit and a high-precision ADC, the electroencephalogram signal is amplified and filtered by the front-end analog circuit and then enters the high-precision ADC for analog-to-digital conversion, the digitized electroencephalogram signal is sent to an electroencephalogram signal processing module by a main control module, the electroencephalogram signal processing module mainly comprises an FPGA chip, the FPGA chip calculates features of emotion in the electroencephalogram through a series of algorithms, then the data are sent to an emotion classification and emotion detection module for emotion classification and detection, and finally, according to the result, the emotion adjustment module performs emotion adjustment.

As shown in fig. 9, the electroencephalogram signals are sent out by the brain of a person and are amplified by the instrumentation operational amplifier, because the original electroencephalogram signals are very weak and can be collected only by amplification, the instrumentation operational amplifier not only realizes the signal amplification function, but also converts the differential signals into single-ended signals. The amplified EEG signal is filtered by a filter circuit on hardware, and the filter circuit mainly comprises a high-pass filter and a low-pass filter which form a band-pass filter. Because the high-precision ADC chip selected by the invention needs to be differentially input, the electroencephalogram signal also needs to be differentially driven, the previous single-ended signal is converted into a differential signal and is sent to the high-precision analog-to-digital converter, then the digitized electroencephalogram signal is sent to the signal processing module for software filtering, then the emotional characteristics are extracted according to the related algorithm, and the emotional classification is carried out according to the extraction result of the characteristics, mainly the FISHER LDA algorithm, FISHER LDA converts the two-dimensional characteristics into the one-dimensional characteristics and then carries out the classification. And judging whether the emotion of the user needs to be adjusted at the moment according to the emotion classification result, and adjusting the emotion if the emotion needs to be adjusted.

It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

The invention comprises an electroencephalogram amplifier, a data processing module and an audio stimulation module, wherein the electroencephalogram amplifier signal acquisition equipment comprises an analog circuit and a digital circuit. The analog circuit comprises amplification, filtering, digitization and electrical isolation of signals, and has the characteristics of high input impedance, low noise, high sampling rate and electrical isolation safety. The digital circuit adopts an ARM chip to control data conversion, data real-time USB transmission, display screen refreshing and system overall logic control. The data processing module adopts FPGA, the FPGA receives the electroencephalogram data sent by the ARM chip through the USB, and the calculated result is sent to the ARM chip through the USB after data processing means such as data preprocessing, filtering and feature extraction are carried out on the FPGA. The audio stimulation module comprises a filter circuit, a power amplification circuit and an audio decoding module and is responsible for realizing music stimulation to adjust emotion.

Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims

1. The utility model provides an emotion detection and governing system based on brain electricity, a serial communication port, including power.Schdoc power module, ADC.Schdoc front end analog signal collection module, ARM system control module, FPGA.Schdoc signal processing module and Music _ Player.Schdoc module, power.Schdoc power module inside electric connection has isolation power supply circuit, the inside electric connection of isolation power supply circuit has the isolation chip, the inside electric connection of power.Schdoc power module has the step-down circuit, ADC.Schdoc front end analog signal collection module inside electric connection has analog front end signal amplification filter circuit, ADC.Schdoc front end analog signal collection module inside electric connection has signal analog-to-digital conversion circuit, FPGA.Schdoc signal processing module inside electric connection has the FPGA chip.

2. The electroencephalogram-based emotion detection and adjustment system according to claim 1, wherein the isolation power supply circuit is a 3.3V isolation power supply circuit, and the isolation chip has four channels in total.

3. The electroencephalogram-based emotion detection and adjustment system according to claim 1, wherein the voltage reduction circuit is a 5V to 3.3V, 2.5V, 1.2V voltage reduction circuit.

4. The electroencephalogram-based emotion detection and adjustment system according to claim 1, wherein the analog front-end signal amplification filter circuit is composed of a chip U15, a resistor R56, a resistor R61, a resistor R65, a capacitor C51, a capacitor C55, a chip U16B, a resistor R59, a resistor R64, a capacitor C56, a chip U16A, a resistor R54, a resistor R55, a resistor R60, a capacitor C50, a capacitor C53, a capacitor C54, a capacitor C58, a chip U14, a resistor R53, a resistor R57, a resistor R58, a resistor R62, a resistor R66, a capacitor C48, a capacitor C49, a capacitor C52, a capacitor C57, a capacitor C59, a chip U53, a resistor R174, a capacitor C180, a resistor R175R 176, a capacitor C181, a resistor R176, a capacitor C182, a resistor R177, and a capacitor C183.

5. The electroencephalogram-based emotion detection and adjustment system according to claim 1, wherein the signal analog-to-digital conversion circuit is constituted by a chip ADS 1299.

6. The electroencephalogram-based emotion detecting and adjusting system according to claim 1, wherein an ARM chip is electrically connected inside the ARM control module, the ARM chip is an STM32F103, and a crystal oscillator Y3, a capacitor C298 and a capacitor C300 form a main control chip.