CN113573000A - Displayport HBR3 signal conversion device based on FPGA - Google Patents
Displayport HBR3 signal conversion device based on FPGA Download PDFInfo
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- CN113573000A CN113573000A CN202110850971.5A CN202110850971A CN113573000A CN 113573000 A CN113573000 A CN 113573000A CN 202110850971 A CN202110850971 A CN 202110850971A CN 113573000 A CN113573000 A CN 113573000A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0127—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter
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- H—ELECTRICITY
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- H—ELECTRICITY
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- H04N17/00—Diagnosis, testing or measuring for television systems or their details
- H04N17/02—Diagnosis, testing or measuring for television systems or their details for colour television signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
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Abstract
The invention discloses a Displayport HBR3 signal conversion device based on FPGA, which comprises an image data receiving module and an image data frame rate adjusting module; the image data receiving module is used for receiving external serial image data and decoding the external serial image data into parallel data in an RGB format; the image data frame rate adjusting module stores the parallel data in the RGB format, performs frame rate adjustment according to the Displayport module to be detected and then outputs the parallel data, acquires Displayport signal rate according to rate information required by the Displayport module to be detected, and converts the parallel data in the RGB format into a serial signal of Displayport matched with the Displayport module signal rate.
Description
Technical Field
The invention relates to the technical Field of display and test of liquid crystal modules, in particular to a Displayport HBR3 (High Bit Rate 3, 8.1 Gbps/lane) graphic signal conversion device and method based on an FPGA (Field-Programmable Gate Array).
Background
The LCD (Liquid Crystal Display) has the advantages of lightness, thinness, low power consumption, small radiation, no flicker on the screen, rich color and the like; the LCD module is a key component of the LCD, and the traditional LCD module usually uses an LVDS (Low-Voltage Differential Signaling) interface for interconnection signals, but the LVDS interface can only support a Low resolution. To meet the increasing demand for display resolution, Displayport interfaces are emerging on the market. The Displayport interface can support ultrahigh resolution and refresh rate, can directly drive the panel, has better electromagnetic compatibility and anti-interference performance, and the liquid crystal module with the Displayport interface is widely applied to large-size electronic equipment in modern tablet computers, notebook computers, desktop displays and the like at present, and especially a large number of Displayport liquid crystal modules with ultrahigh refresh rate appear in recent years.
However, the conventional testing device has the following defects when testing the liquid crystal module:
(1) there are a lot of testing devices without Displayport interface on the production line of liquid crystal module producer, but do not want to eliminate the existing equipment to purchase special Displayport testing device or purchase expensive testing device with various image signal interfaces including Displayport interface.
(2) At present, a Displayport testing device based on an FPGA on the market mostly only meets the protocol standard of Displayport v1.2, only meets three fixed rates specified by Displayport v1.2 protocol, and the highest Rate only supports HBR2 (High Bit Rate 2, 5.4 Gbps/lane) and cannot meet the special Rate and the custom Rate for low-power-consumption equipment in EDP (embedded Displayport) protocol; however, a large number of ultra-High resolution and ultra-High refresh Rate liquid crystal modules are already available in the market, the Rate is required to meet Displayport v1.4a and support edp (embedded Displayport) v1.4b protocol standard, the Rate is the highest Rate of HBR3 (High Bit Rate 3, 8.1 Gbps/lane), and the device only meeting the protocol standard of Displayport v1.2 cannot meet the requirement.
(3) Therefore, a Displayport HBR3 (High Bit Rate 3, 8.1 Gbps/lane) signal conversion device based on the FPGA needs to be researched, LVDS image signals with low refresh Rate can be converted into Displayport High-speed image signals with High refresh Rate, a test device without Displayport interfaces on a production line of a liquid crystal module manufacturer can be used for testing Displayport liquid crystal modules with ultra-High resolution and ultra-High refresh Rate, and cost is reduced.
Disclosure of Invention
Aiming at the defects in the prior art, the embodiments of the present invention provide a Displayport HBR3 signal conversion device based on an FPGA, which can convert any low-resolution image data into Displayport high-speed image data with a high refresh rate, and provide the functions of Vcom adjustment, EDID burning and the like, all the functions are realized in one FPGA, the integration level of a liquid crystal module testing device is high, the testing cost is saved, the testing efficiency and the testing reliability are improved, and the production efficiency and the product qualification rate of enterprises are improved.
In order to achieve the purpose, the invention provides the following technical scheme:
a Displayport HBR3 signal conversion device based on FPGA comprises an image data receiving module and an image data frame rate adjusting module; the image data receiving module is used for receiving external serial image data and decoding the external serial image data into parallel data in an RGB format; the image data frame rate adjusting module stores the parallel data in the RGB format, performs frame rate adjustment according to the Displayport module to be detected and then outputs the parallel data, acquires Displayport signal rate according to rate information required by the Displayport module to be detected, and converts the parallel data in the RGB format into a serial signal of Displayport matched with the Displayport module signal rate.
As a further scheme of the present invention, the present invention further includes a Displayport signal protocol layer coding module, where the Displayport signal protocol layer coding module includes an AUX module, and is connected to the Displayport module to be tested to obtain the rate information of the Displayport module to be tested.
As a further scheme of the present invention, the Displayport signal protocol layer encoding module is connected to a Displayport physical layer transmitting module, and the Displayport physical layer transmitting module includes a high-speed serializer and a serialization rate configuration unit.
As a further scheme of the present invention, the present invention further comprises a register configuration module, an image timing sequence generation module, a central processing unit module, an image parameter receiving module, and an image data frame rate adjustment module, wherein the central processing unit module controls to receive and store each image parameter transmitted by an external device in a cache of the central processing unit module, and then controls the register configuration module to perform configuration.
As a further aspect of the present invention, the image data receiving module decodes the received LVDS image data into RGB image data according to the register configuration module; the image data frame rate adjusting module receives RGB data with a low frame rate and stores the RGB data into plug-in DDR SDRAM storage particles, and the image time sequence generating module receives register generation time sequence control signals which are received by the register configuration module and correspond to the resolution type of the Displayport module.
As a further scheme of the present invention, the image data frame rate adjustment module takes out the received RGB data from the DDR SDRAM storage particles according to the timing control signal output by the image timing generation module to complete the frame rate adjustment processing operation, and then transmits the frame rate adjustment processing operation to the Displayport signal protocol layer encoding module.
As a further solution of the present invention, the Displayport signal protocol layer encoding module encodes the received RGB data and the timing control signal into a packet in Displayport protocol format, and the Displayport physical layer transmitting module receives the packet in Displayport protocol format output by the Displayport signal protocol layer encoding module, and generates a Displayport serial signal with matched rate according to the number of channels and rate information obtained by the AUX communication interface in the Displayport signal protocol layer encoding module, thereby completing a Displayport module display image picture test.
As a further scheme of the present invention, the cpu module controls the image parameter receiving module to receive and store various image parameters transmitted by the external device in a cache of the cpu module, and controls the AUX communication module in the Displayport signal protocol layer coding module to perform VCOM adjustment and EDID burning of the Displayport module.
The method comprises the steps that an AUX communication interface in a Displayport signal protocol layer coding module is controlled by a central processing unit module to communicate with a module to obtain data bit width, channel number and rate information of the module to be tested; the Displayport physical layer sending module receives a Displayport protocol format data packet output by the Displayport signal protocol layer coding module, generates a Displayport serial signal with matched Rate according to the number of channels and Rate information obtained by an AUX communication interface in the Displayport signal protocol layer coding module, and has the highest serialization Rate which can be configured to the Rate of HBR3 (High Bit Rate 3, 8.1 Gbps/lane), thereby completing the Displayport module display image picture test.
To more clearly illustrate the structural features and effects of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
Description of the drawings:
fig. 1 is a schematic structural diagram of a Displayport HBR3 signal conversion device based on an FPGA.
The specific implementation mode is as follows:
the invention will be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown.
Referring to fig. 1, an FPGA-based Displayport HBR3 signal conversion apparatus includes an image data receiving module 2, an image data frame rate adjusting module 3; the image data receiving module 2 is used for receiving external serial image data and decoding the external serial image data into parallel data in an RGB format; the image data frame rate adjusting module 3 stores the parallel data of the RGB format, performs frame rate adjustment according to the Displayport module 9 to be detected and then outputs the parallel data, acquires Displayport signal rate according to the rate information required by the Displayport module 9 to be detected, converts the parallel data of the RGB format into a serial signal of Displayport matched with the Displayport module 9 signal rate, can convert the image data of any low resolution into Displayport high-speed image data of high refresh rate, and provides functions of Vcom adjustment, EDID burning and the like, all the functions are realized in one FPGA, the liquid crystal module testing device has high integration level, the testing cost is saved, the testing efficiency and the testing reliability are improved, and the production efficiency and the product qualification rate of enterprises are improved.
Wherein, still include Displayport signal protocol layer coding module 7, Displayport signal protocol layer coding module 7 includes the AUX module, connects the speed information that awaits measuring Displayport module in order to acquire the Displayport module that awaits measuring. Therefore, the number of channels and the speed information of the module to be tested are obtained through the communication between the AUX interface and the module.
It is further preferable that the Displayport signal protocol layer encoding module 7 is connected with a Displayport physical layer transmission module 8, and the Displayport physical layer transmission module 8 includes a High-speed serializer and a serialization Rate configuration unit, wherein the serialization Rate is configurable up to the Rate of HBR3 (High Bit Rate 3, 8.1 Gbps/lane). Therefore, the reference clock and the serialization Rate of the phase-locked loop in the High-speed serializer of each channel are dynamically configured through the serialization Rate configuration unit according to the Rate information, so that the High-speed serializer is matched with the Displayport signal Rate required by the module to be tested, and the highest serialization Rate can be configured to be the Rate of HBR3 (High Bit Rate 3, 8.1 Gbps/lane). And converting the parallel data of the Displayport codes of all the channels into serial Displayport signals with corresponding rates through a configured high-speed serializer coding module.
Further preferably, the image parameter configuration system further comprises a register configuration module 1, an image timing sequence generation module 4, a central processor module 5 and an image parameter receiving module 6, wherein the central processor module 5 controls to receive and store various image parameters transmitted by external equipment in a cache of the central processor module 5, and then controls the register configuration module 1 to perform configuration.
In the invention, an image data receiving module 2 decodes received LVDS image data into RGB image data according to a register configuration module 1; the image data frame rate adjusting module 3 receives RGB data with a low frame rate and stores the RGB data into the plug-in DDR SDRAM storage particles, and the image time sequence generating module 4 receives register generation time sequence control signals corresponding to the resolution type of the Displayport module received by the register configuration 1 module.
In the invention, the frame rate adjusting module 3 of image data takes out the received RGB data from DDR SDRAM storage particles according to the time sequence control signal output by the image time sequence generating module 4 to complete the frame rate adjusting processing operation, and then transmits the RGB data to the Displayport signal protocol layer coding module 7; the Displayport signal protocol layer coding module 7 codes the received RGB data and the time sequence control signal into a data packet in a Displayport protocol format, the Displayport physical layer sending module 8 receives the data packet in the Displayport protocol format output by the Displayport signal protocol layer coding module 7, and generates a Displayport serial signal with matched rate according to the number of channels and rate information obtained by an AUX communication interface in the Displayport signal protocol layer coding module, thereby completing the Displayport module display image picture test; the central processor module 5 controls the image parameter receiving module 6 to receive various image parameters transmitted by the external device and store the image parameters in the cache of the central processor module 5, and controls the AUX communication module in the Displayport signal protocol layer coding module to perform VCOM adjustment and EDID burning of the Displayport module. In the invention, the RGB image data and parameters of each channel are coded according to the Displayport protocol to obtain the parallel data of Displayport codes.
The following provides a specific embodiment of the present invention
Example 1
Referring to fig. 1, the present invention includes a register configuration module 1, an image data receiving module 2, an image data frame rate adjusting module 3, an image timing sequence generating module 4, a central processor module 5, an image parameter receiving module 6, a Displayport signal protocol layer coding module 7, and a Displayport physical layer transmitting module 8.
The image data receiving module 2 is configured to receive serial image data sent by an external LVDS (Low-Voltage Differential Signaling) image interface and decode the serial image data into parallel data in an RGB format; the image data frame Rate adjusting module 3 stores the parallel data in the RGB format with the low frame Rate, performs frame Rate adjustment according to a Displayport module to be detected, then outputs the parallel data, acquires Displayport signal Rate according to Rate information required by the Displayport module to be detected, converts the parallel data into a serial signal of Displayport matched with the Displayport module signal Rate, and has the highest serialization Rate which can be configured as the Rate of HBR3 (High Bit Rate 3, 8.1 Gbps/lane);
in this embodiment, the Displayport signal protocol layer encoding module 7 further includes an AUX communication processing unit, which is connected to the Displayport module to be tested to obtain the rate information of the Displayport module to be tested; the Displayport physical layer transmission module 8 further comprises a High-speed serializer and a serialization Rate configuration unit, wherein the serialization Rate is configurable to be the Rate of HBR3 (High Bit Rate 3, 8.1 Gbps/lane) at the highest; the method comprises the steps that an AUX interface is communicated with a module to obtain the channel number and speed information of the module to be detected, RGB image data and parameters of each channel are coded according to a Displayport protocol, and parallel data of Displayport codes are obtained; then, according to the Rate information, a reference clock and a serialization Rate of a phase-locked loop in the High-speed serializer of each channel are dynamically configured through a serialization Rate configuration unit, so that the High-speed serializer is matched with the Rate of a Displayport signal required by a module to be tested, the serialization Rate can be configured to be the Rate of HBR3 (High Bit Rate 3, 8.1 Gbps/lane) at the highest, and parallel data coded by Displayport of each channel is converted into a serial Displayport signal with the corresponding Rate through a configured High-speed serializer coding module.
The method specifically comprises the following steps: the central processing unit module 5 controls the image parameter receiving module 6 to receive various image parameters transmitted by external equipment and store the image parameters in a cache of the central processing unit module, then controls the register configuration module 1 to configure the modules, and the image data receiving module 2 decodes the received LVDS image data into RGB image data according to the register configuration module 1; the image data frame rate adjusting module 3 receives the RGB data of the low frame rate and stores the RGB data in a plug-in DDR SDRAM (double data rate synchronous dynamic random access memory) memory particle; the image time sequence generating module 4 receives the register generation time sequence control signal of the resolution type of the corresponding Displayport module received by the register configuration module 1;
the image data frame rate adjusting module 3 takes out the received RGB data from DDR SDRAM (double data synchronous dynamic random access memory) storage particles according to the time sequence control signal output by the image time sequence generating module to complete the frame rate adjusting processing operation, and then sends the RGB data to the Displayport signal protocol layer coding module together; the central processing unit module 5 controls an AUX communication interface in the Displayport signal protocol layer coding module 7 to communicate with the module to obtain the data bit width, the channel number and the rate information of the module to be tested; the Displayport signal protocol layer coding module 7 codes the received RGB data and the time sequence control signal into a data packet in a Displayport protocol format; the Displayport physical layer sending module 8 receives a Displayport protocol format data packet output by the Displayport signal protocol layer coding module 7, generates a Displayport serial signal with matched Rate according to the number of channels and Rate information obtained by an AUX communication interface in the Displayport signal protocol layer coding module 7, and has the highest serialization Rate which can be configured to be the Rate of HBR3 (High Bit Rate 3, 8.1 Gbps/lane), thereby completing the Displayport module display image picture test; the central processing unit controls the image parameter receiving module to receive various image parameters transmitted by the external equipment, stores the image parameters in a cache of the central processing unit, and controls the AUX communication module in the Displayport signal protocol layer coding module to carry out VCOM adjustment and EDID burning of the Displayport module. The invention can convert any low-resolution image data into Displayport high-speed image data with high refresh rate, provides the functions of Vcom adjustment, EDID burning and the like, realizes all the functions in one FPGA, has high integration level of the liquid crystal module testing device, saves the testing cost, improves the testing efficiency and the testing reliability, and improves the production efficiency and the product qualification rate of enterprises.
The technical principle of the present invention has been described above with reference to specific embodiments, which are merely preferred embodiments of the present invention. The protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. Other embodiments of the invention will occur to those skilled in the art without the exercise of inventive faculty, and such will fall within the scope of the invention.
Claims (8)
1. A Displayport HBR3 signal conversion device based on FPGA is characterized by comprising an image data receiving module and an image data frame rate adjusting module; the image data receiving module is used for receiving external serial image data and decoding the external serial image data into parallel data in an RGB format; the image data frame rate adjusting module stores the parallel data in the RGB format, performs frame rate adjustment according to the Displayport module to be detected and then outputs the parallel data, acquires Displayport signal rate according to rate information required by the Displayport module to be detected, and converts the parallel data in the RGB format into a serial signal of Displayport matched with the Displayport module signal rate.
2. The FPGA-based Displayport HBR3 signal conversion device of claim 1, further comprising a Displayport signal protocol layer encoding module, wherein the Displayport signal protocol layer encoding module comprises an AUX module, and is connected to the Displayport module to be tested to obtain rate information of the Displayport module to be tested.
3. The FPGA-based Displayport HBR3 signal conversion device of claim 2, wherein the Displayport signal protocol layer encoding module is connected to a Displayport physical layer transmission module, the Displayport physical layer transmission module comprising a high speed serializer and a serialization rate configuration unit.
4. The FPGA-based Displayport HBR3 signal conversion device of claim 1, further comprising a register configuration module, an image timing generation module, a central processing unit module, and an image parameter receiving module, wherein the central processing unit module controls to receive and store image parameters transmitted by an external device in a cache of the central processing unit module, and then controls the register configuration module to perform configuration.
5. The FPGA-based Displayport HBR3 signal conversion device of claim 4, wherein the image data receiving module decodes the received LVDS image data into RGB image data according to the register configuration module; the image data frame rate adjusting module receives RGB data with a low frame rate and stores the RGB data into plug-in DDR SDRAM storage particles, and the image time sequence generating module receives register generation time sequence control signals which are received by the register configuration module and correspond to the resolution type of the Displayport module.
6. The FPGA-based Displayport HBR3 signal conversion apparatus of claim 5, wherein the image data frame rate adjustment module takes out the received RGB data from the DDR SDRAM memory granules according to the timing control signal outputted by the image timing generation module to complete the frame rate adjustment processing operation, and then transmits the RGB data to the Displayport signal protocol layer encoding module.
7. The FPGA-based Displayport HBR3 signal conversion apparatus of claim 6, wherein the Displayport signal protocol layer encoding module encodes the received RGB data and the timing control signal into a packet of Displayport protocol format, the Displayport physical layer transmitting module receives the packet of Displayport protocol format output by the Displayport signal protocol layer encoding module, and generates a rate-matched Displayport serial signal according to the number of channels and rate information obtained by the AUX communication interface in the Displayport signal protocol layer encoding module, thereby completing the Displayport module display image picture test.
8. The FPGA-based Displayport HBR3 signal conversion device of claim 7, wherein the cpu module controls the image parameter receiving module to receive and store image parameters transmitted from an external device in a buffer of the cpu module, and controls the AUX communication module in the Displayport signal protocol layer coding module to perform VCOM adjustment and EDID burning of the Displayport module.
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