CN113571480B - Substrate and packaging structure thereof - Google Patents
Substrate and packaging structure thereof Download PDFInfo
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- CN113571480B CN113571480B CN202110956893.7A CN202110956893A CN113571480B CN 113571480 B CN113571480 B CN 113571480B CN 202110956893 A CN202110956893 A CN 202110956893A CN 113571480 B CN113571480 B CN 113571480B
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- solder balls
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- 239000000758 substrate Substances 0.000 title claims abstract description 57
- 238000004806 packaging method and process Methods 0.000 title abstract description 13
- 229910000679 solder Inorganic materials 0.000 claims abstract description 153
- 230000008054 signal transmission Effects 0.000 claims abstract description 25
- 239000011159 matrix material Substances 0.000 claims description 7
- 239000003990 capacitor Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 5
- 230000009471 action Effects 0.000 description 3
- 238000004891 communication Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 238000009434 installation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1301—Shape
- H01L2224/13016—Shape in side view
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The application provides a substrate and a packaging structure thereof, wherein the substrate comprises a first area and a second area, the second area is arranged around the first area, a plurality of solder balls are arranged in the first area and the second area, a first interval is arranged between the solder balls in the first area, and a second interval smaller than the first interval is arranged between the solder balls in the second area; the solder balls in the first area are provided with through holes so as to realize signal transmission through the through holes; the solder balls in the second region are led out through the leads to realize signal transmission through the leads. The substrate provided by the application can be used for arranging more solder balls relative to the substrate with the solder balls arranged at the unique interval, so that the miniaturization of the substrate is realized.
Description
Technical Field
The application relates to the technical field of chip packaging, in particular to a substrate and a packaging structure thereof.
Background
In chip packaging design, the solder ball arrays on the back of the chip are all equidistant, so that the solder balls are conveniently welded on a circuit board. However, the equally spaced solder ball arrays limit the number of solder balls of the chip and limit the number of solder ball arrangements more.
In the prior art, the arrangement requirement of multiple signals is met by increasing the size of the package, but the increase of the package size can increase the package cost or the substrate cannot be placed in the package.
Disclosure of Invention
The present application provides a substrate and a package structure thereof, which solve the above-mentioned problems by arranging solder balls in different areas at unequal intervals.
In a first aspect, the present invention provides a substrate, the substrate including a first region and a second region, the second region being disposed around the first region, the first region and the second region each having a plurality of solder balls disposed therein, wherein a first pitch is provided between the solder balls in the first region, and a second pitch smaller than the first pitch is provided between the solder balls in the second region; the solder balls in the first area are provided with through holes so as to realize signal transmission through the through holes; and the solder balls in the second area are led out through the lead wires so as to realize signal transmission through the lead wires.
According to the substrate designed in the above way, through designing the first area and the second area and designing the second space between the solder balls in the second area to be smaller than the first space between the solder balls in the first area, more solder balls can be arranged on the designed substrate in a mode of arranging the first space relatively, and the technical problems that in the prior art, the packaging size is increased due to the increase of the substrate, the packaging cost is increased, or the substrate is adopted for realizing corresponding functions, and the substrate cannot be placed in packaging are solved; in addition, by adopting the technical scheme that the solder balls in the second area are led out through the lead wires, the solder balls in the first area realize signal transmission through the through holes, the wiring layer number of the circuit board is reduced, and the purpose of saving cost is achieved.
In an optional implementation manner of the first aspect, a plurality of through holes are disposed in the first area, each through hole is disposed in the first space, and a lead of the solder ball in the first area is connected with other circuit layers of the circuit board through the corresponding through hole, so as to realize signal transmission between the signal in the first area and the other circuit layers.
In an alternative implementation manner of the first aspect, a plurality of passive elements are disposed in the first area, and the passive elements are spaced from the solder balls.
In an optional implementation manner of the first aspect, the substrate further includes a third area disposed around the second area, and a plurality of solder balls are disposed in the third area, where a pitch between the solder balls in the third area is greater than or equal to the second pitch; the third area further comprises a plurality of lead gaps, the lead gaps are formed by the distances between the solder balls in the third area being larger than the second distances, and the leads of the solder balls in the second area are led out through the lead gaps so as to realize signal transmission in the second area.
In the above-described embodiment, the first area, the second area, and the third area are designed, and the second pitch between the solder balls in the second area is designed to be smaller than the first pitch between the solder balls in the first area, and the third pitch between some solder balls in the third area is larger than the second pitch, and the pitch between other solder balls is equal to the second pitch, so that more solder balls can be arranged on the designed substrate in a manner of arranging the solder balls at the first pitch; in addition, the lead wires of the solder balls in the second area are led out through lead wire gaps formed in the third area, the solder balls in the third area are led out directly through the lead wires, and the solder balls in the first area realize signal transmission through the through holes, so that the purpose of reducing the wiring layer number of the circuit board is achieved, and the cost of the circuit board is reduced; furthermore, the lead of the solder ball in the second area is led out through the lead gap formed by the third area, so that the lead of the second area has enough lead-out space, and wiring or installation problems caused by the defects of lead volume or space retention are avoided.
In an optional implementation manner of the first aspect, the solder balls in the third area, which are close to each other, form a pair of solder balls, and the solder balls in the pair of solder balls are led out through a lead, so that signal transmission in the third area is realized through the lead.
In an alternative embodiment of the first aspect, a pitch between the solder balls in the pair of solder balls in the third area is equal to the second pitch, to facilitate molding of the substrate.
In an alternative implementation manner of the first aspect, the solder ball pairs in the third area are arranged in a first direction, and the wire slits are formed between the plurality of solder ball pairs in a second direction, wherein the first direction is perpendicular to the second direction.
In an alternative embodiment of the first aspect, the leads in the second and third regions extend away from the first region in the second direction.
In an alternative embodiment of the first aspect, the solder balls in the first region, the second region and the third region are symmetrically arranged.
In an alternative embodiment of the first aspect, the solder balls in the first area are arranged in a matrix.
In a second aspect, the present invention provides a package structure, the package structure comprising: a package, a substrate according to any one of the preceding embodiments, and a circuit element on the substrate.
The above-mentioned design package structure, because it includes the base plate designed in the first aspect of the invention, therefore, the design package structure can arrange more solder balls relative to the arrangement mode of the first interval, solve the technical problem that the increase of the package size in the prior art can cause the increase of the package cost or the base plate can not be placed in the package. In addition, the solder balls in the second area are led out through the lead wires, and the solder balls in the first area realize signal transmission through the through holes, so that the wiring layer number of the circuit board is reduced, and the aim of saving cost is achieved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic view of a first structure of a substrate according to an embodiment of the present application;
Fig. 2 is a first schematic structural diagram of a via layout according to an embodiment of the present application;
Fig. 3 is a second schematic structural diagram of a via layout according to an embodiment of the present application;
fig. 4 is a schematic diagram of a second structure of a substrate according to an embodiment of the present application;
fig. 5 is a schematic view of a third structure of a substrate according to an embodiment of the present application;
fig. 6 is a schematic diagram of a fourth structure of a substrate according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of a package structure according to an embodiment of the present application.
Icon: 1-packaging structure; 10-a substrate; 101-a first region; 1011-passive elements; 102-a second region; 103-a third region; 1031-a lead gap; 1032—a second lead; 20-solder balls; 201-a through hole; 202-a first lead; 203-solder ball pairs; 50-packaging; 60-circuit elements; l1-a first pitch; l2-a second pitch; l3-third interval.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.
First embodiment
The embodiment of the application provides a substrate 10, where the substrate 10 is used for chip packaging, as shown in fig. 1, the substrate 10 includes a first area 101 and a second area 102, the second area 102 is disposed around the first area 101, a plurality of solder balls 20 are disposed in the first area 101 and the second area 102, a first spacing L1 is between the solder balls 20 in the first area 101, a second spacing L2 is between the solder balls 20 in the second area 102, and the second spacing L2 is smaller than the first spacing L1. For example, the first spacing L1 between each solder ball 20 in the first region 101 may be 0.65mm and the second spacing L2 between each solder ball 20 in the second region 102 may be less than 0.65mm, such as specifically 0.4mm.
In the substrate with the above structural design, through holes 201 are arranged in the first region 101 corresponding to the solder balls 20, so that signal transmission is realized through the through holes; the solder balls 20 in the second region 102 may be routed through the first leads 202 to enable signal transmission through the leads.
According to the substrate with the structural design, the first area 101 and the second area 102 are designed, and the second space between the solder balls 20 in the second area 102 is smaller than the first space between the solder balls 20 in the first area, so that more solder balls can be arranged on the substrate with the same space arrangement mode of the first space, and different circuit functions can be given to the first area 101 and the second area 102 according to different areas. In addition, the solder balls 20 in the second area 102 are led out through the lead wires, and the solder balls 20 in the first area 101 realize signal transmission through the through holes, so that the wiring layer number of the circuit board is reduced, and the purpose of saving cost is achieved.
In the designed embodiment, each through hole 201 in the first area 101 is disposed in the first space L1, and the lead wire of each solder ball 20 is connected with other circuit layers of the circuit board through the corresponding through hole 201, so as to realize signal transmission between the signal in the first area 101 and the other circuit layers, thereby reducing the number of wiring layers of the circuit board and reducing the design cost of the circuit board.
As a possible implementation, as shown in fig. 2, 4 solder balls in the first region 101 may share one through hole 201, so that the leads of the 4 solder balls may be connected to other layers through the same through hole 201; as another possible embodiment, as shown in fig. 3, in the first area 101, 2 solder balls may share one through hole 201, so that the leads of the 2 solder balls may be connected to other layers of the circuit board through the same through hole 201, thereby avoiding mutual contact between the leads. In addition, each solder ball 20 may be provided with a through hole 201 individually, so that the lead of each solder ball 20 is connected to other layers of the circuit board through the corresponding through hole 201.
In an alternative implementation of the present embodiment, as shown in fig. 1, the solder balls 20 in the first area 101 and the solder balls 20 in the second area 102 are symmetrically arranged, where the symmetrical arrangement is that the arrangement structure of the solder balls in the first area 101 and the solder balls 20 in the second area 102 is symmetrical left and right, and up and down; as a possible implementation, the solder balls 20 in the first region 101 may be arranged in a matrix as shown in fig. 1.
In an alternative implementation manner of this embodiment, the solder balls disposed in the first area 101 may not be completely arranged in a matrix, in addition to the matrix symmetrical arrangement in the above manner, and the solder balls may be removed as required; in addition to removing a portion of the solder balls, as shown in fig. 4, a plurality of passive elements 1011 may be disposed in the first area 101, where the passive elements 1011 and the solder balls 20 are disposed at intervals, and the passive elements 1011 may be components such as capacitors or resistors. By arranging the passive element 1011 on the substrate, the gain function required by the PCB can be realized through the passive element 1011 of the substrate, for example, the passive element 1011 provides power gain for the PCB, and the like, so that the designed substrate has low cost and stronger function.
Second embodiment
The present embodiment provides another substrate 10, where the substrate 10 is also used for chip packaging, as shown in fig. 5, the substrate 10 includes a first region 101, a second region 102, and a third region 103, where the second region 102 is disposed around the first region 101, and the third region 103 is disposed around the second region 102.
The solder balls 20 in the first area 101 have a first spacing L1 therebetween, the solder balls 20 in the second area 102 have a second spacing L2 therebetween, and the solder balls 20 in the third area 103 have a third spacing L3 therebetween, wherein the second spacing L2 is smaller than the first spacing L1, and the third spacing L3 is greater than or equal to the second spacing L2. For example, the first pitch L1 between the solder balls 20 in the first region 101 may be 0.65mm, the second pitch L2 between the solder balls 20 in the second region 102 may be 0.4mm, and the third pitch L3 between the solder balls in the third region 103 may be equal to the second pitch L2, that is, 0.4mm, or may be greater than the second pitch L2, for example, 0.8mm; the solder balls in the third region 103 may further have a third pitch L3 between a portion of the solder balls 20 equal to the second pitch L2, that is, 0.4mm; the third pitch L3 between the other portion of the solder balls 20 is larger than the second pitch L2, for example, 0.8mm.
The third area 103 further includes a plurality of lead slits 1031, where the plurality of lead slits 1031 are formed by a pitch larger than the second pitch L2 between the solder balls in the third area, for example, the third pitch L3 is a pitch of 0.8mm, that is, the lead slits 1031 are formed; the first leads 202 of the solder balls 20 in the second region 102 are led out through the lead slots 1031 to effect signal transmission in the second region 102.
The solder balls in the third area 103 are directly led out through the second lead 1032, so that the transmission of signals in the third area 103 is realized; the solder balls 20 in the first area 101 are connected to other layers of the circuit board through the through holes 201, so as to realize signal transmission in the first area 101, where the layout of the through holes 201 may be identical to the layout of fig. 2 and 3 in the first embodiment, and will not be described herein.
In the above-designed substrate, by designing the first region 101, the second region 102 and the third region 103, and designing the second spacing L2 between the solder balls 20 in the second region 102 to be smaller than the first spacing L1 between the solder balls 20 in the first region 101, the third spacing L3 of part of the solder balls in the third region is larger than the second spacing L2, and the spacing of the other part of the solder balls is equal to the second spacing L2, so that more solder balls can be arranged on the designed substrate in an equidistant arrangement mode with respect to the first spacing; in addition, the lead wires of the solder balls 20 in the second area 102 are led out through the lead wire gaps formed by the third area 103, the solder balls 20 in the third area 103 are led out directly through the lead wires, and the solder balls 20 in the first area 101 realize signal transmission through the through holes, so that the purpose of reducing the wiring layer number of the circuit board is achieved, and the cost of the circuit board is reduced; furthermore, since the lead of the solder ball 20 in the second region 102 is led out through the lead gap formed by the third region 103, the lead of the second region 102 has enough lead-out space, and the installation problem caused by the lead volume is avoided.
In an alternative implementation of this embodiment, as shown in fig. 5, the solder balls 20 in the third area 103 with close distances form a solder ball pair 203, and the solder balls 20 in the solder ball pair 203 are led out through the second lead 1032, so as to implement signal transmission through the second lead 1032 in the third area 103. It should be noted that the number of solder balls in the pair of solder balls 203 may be other than 2 as shown in fig. 5, for example, 3 solder balls 20 may form one pair of solder balls 203.
As one possible implementation, the pitch between the solder balls 20 in the pair of solder balls 203 is equal to the second pitch, and the pitch between each two pairs of solder balls 203 is greater than the second pitch L2, for example, the pitch between the solder balls 20 in the pair of solder balls 203 is 0.4mm, the pitch between each two pairs of solder balls 203 is 0.8mm, and thus a lead gap 1031 is formed between each two pairs of solder balls 203.
In an alternative implementation of the present embodiment, as shown in fig. 5, the solder ball pairs 203 of the third area 103 are arranged in a first direction, and the wire slits 1031 are formed between the plurality of solder ball pairs 203 in a second direction, where the first direction is perpendicular to the second direction. As can be seen from the example of fig. 5, the solder ball pairs 203 are arranged in the horizontal direction, and the wire slits 1031 are formed between the two solder ball pairs 203 in the vertical direction.
In an alternative implementation of the present embodiment, as shown in fig. 5, the leads of the second region 102 and the third region 103 extend away from the first region 101 in the second direction, that is, the leads of the second region 102 and the third region 103 are each directly led to the outside of the substrate 10.
In an alternative implementation manner of the present embodiment, as shown in fig. 5, the solder balls 20 in the first area 101, the second area 102, and the solder balls 20 in the third area 103 are symmetrically arranged, where the arrangement structure of the solder balls in the first area 101, the second area 102, and the solder balls 20 in the third area 103 is symmetrical left-right, and up-down; as a possible embodiment, the solder balls 20 in the first area 101 are arranged in a matrix as shown in fig. 5. In addition, in addition to the matrix arrangement shown in fig. 5, a manner in which part of the solder balls in the first region shown in fig. 6 are replaced with passive elements 1011 may be also presented.
Third embodiment
The present application provides a package structure 1, as shown in fig. 7, where the package structure 1 includes a substrate 10, a package body 50, and a circuit element 60 on the substrate 10, and the circuit element 60 is disposed in the package body 50, which is described in any of the alternative embodiments of the first embodiment or the second embodiment.
The above-mentioned package structure includes the substrate 10 according to the first embodiment or the second embodiment, so that more solder balls 20 can be arranged in the package structure 1 according to the first embodiment; in addition, the solder balls 20 in the second area 102 are led out through the lead wires, and the solder balls 20 in the first area 101 realize signal transmission through the through holes 201, so that the wiring layer number of the circuit board is reduced, and the purpose of saving cost is achieved.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
Further, the units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Furthermore, functional modules in various embodiments of the present application may be integrated together to form a single portion, or each module may exist alone, or two or more modules may be integrated to form a single portion.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (9)
1. A substrate, wherein the substrate comprises a first region and a second region, the second region is arranged around the first region, a plurality of solder balls are arranged in the first region and the second region, a first interval is arranged between the solder balls in the first region, and a second interval smaller than the first interval is arranged between the solder balls in the second region;
the solder balls in the first area are provided with through holes so as to realize signal transmission through the through holes;
the solder balls in the second area are led out through leads so as to realize signal transmission through the leads;
A plurality of through holes are formed in the first area, each through hole is arranged in the first interval, and leads of solder balls in the first area are connected with other circuit layers of the circuit board through corresponding through holes so as to realize signal transmission between signals in the first area and the other circuit layers;
A plurality of passive elements are arranged in the first area, and the passive elements are arranged at intervals with the solder balls; wherein the passive element comprises a capacitor or resistor element for providing a power gain to the substrate.
2. The substrate of claim 1, further comprising a third region disposed about the second region, the third region having a plurality of solder balls disposed therein, wherein a pitch between the solder balls in the third region is greater than or equal to the second pitch;
the third area further comprises a plurality of lead gaps, the lead gaps are formed by the distances between the solder balls in the third area being larger than the second distances, and the leads of the solder balls in the second area are led out through the lead gaps so as to realize signal transmission in the second area.
3. The substrate of claim 2, wherein the solder balls in the third region are closely spaced apart to form a pair of solder balls, the solder balls in the pair of solder balls being routed through a lead to effect transmission of signals in the third region through the lead.
4. A substrate according to claim 3, wherein the pitch between the solder balls in the pair of solder balls in the third region is equal to the second pitch.
5. The substrate of claim 3, wherein the pairs of solder balls in the third region are arranged in a first direction, and the wire slits are formed between the pairs of solder balls in a second direction, wherein the first direction is perpendicular to the second direction.
6. The substrate of claim 5, wherein the leads in the second and third regions extend away from the first region in the second direction.
7. The substrate of claim 2, wherein the solder balls in the first, second and third regions are symmetrically arranged.
8. The substrate of claim 7, wherein the solder balls in the first region are arranged in a matrix.
9. A package structure, the package structure comprising: a package, a substrate according to any one of claims 1 to 8, and a circuit element on the substrate.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110956893.7A CN113571480B (en) | 2021-08-19 | 2021-08-19 | Substrate and packaging structure thereof |
| PCT/CN2021/137816 WO2023019824A1 (en) | 2021-08-19 | 2021-12-14 | Substrate and packaging structure thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110956893.7A CN113571480B (en) | 2021-08-19 | 2021-08-19 | Substrate and packaging structure thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113571480A CN113571480A (en) | 2021-10-29 |
| CN113571480B true CN113571480B (en) | 2024-05-31 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110956893.7A Active CN113571480B (en) | 2021-08-19 | 2021-08-19 | Substrate and packaging structure thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN113571480B (en) |
| WO (1) | WO2023019824A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113571480B (en) * | 2021-08-19 | 2024-05-31 | 北京爱芯科技有限公司 | Substrate and packaging structure thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6373139B1 (en) * | 1999-10-06 | 2002-04-16 | Motorola, Inc. | Layout for a ball grid array |
| CN107333387A (en) * | 2017-06-22 | 2017-11-07 | 上海兆芯集成电路有限公司 | Printed circuit board and semiconductor packaging structure |
| CN109801895A (en) * | 2018-12-29 | 2019-05-24 | 晶晨半导体（深圳）有限公司 | Welded ball array encapsulates chip and printed circuit board |
| CN215988713U (en) * | 2021-08-19 | 2022-03-08 | 北京爱芯科技有限公司 | Substrate and packaging structure thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6689634B1 (en) * | 1999-09-22 | 2004-02-10 | Texas Instruments Incorporated | Modeling technique for selectively depopulating electrical contacts from a foot print of a grid array (BGA or LGA) package to increase device reliability |
| TWI686113B (en) * | 2017-06-22 | 2020-02-21 | 上海兆芯集成電路有限公司 | Printed circuit board and semiconductor package structure |
| CN113571480B (en) * | 2021-08-19 | 2024-05-31 | 北京爱芯科技有限公司 | Substrate and packaging structure thereof |
-
2021
- 2021-08-19 CN CN202110956893.7A patent/CN113571480B/en active Active
- 2021-12-14 WO PCT/CN2021/137816 patent/WO2023019824A1/en unknown
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6373139B1 (en) * | 1999-10-06 | 2002-04-16 | Motorola, Inc. | Layout for a ball grid array |
| CN107333387A (en) * | 2017-06-22 | 2017-11-07 | 上海兆芯集成电路有限公司 | Printed circuit board and semiconductor packaging structure |
| CN109801895A (en) * | 2018-12-29 | 2019-05-24 | 晶晨半导体（深圳）有限公司 | Welded ball array encapsulates chip and printed circuit board |
| CN215988713U (en) * | 2021-08-19 | 2022-03-08 | 北京爱芯科技有限公司 | Substrate and packaging structure thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113571480A (en) | 2021-10-29 |
| WO2023019824A1 (en) | 2023-02-23 |
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