CN113555057A - Implementation method for expanding solid state disk mapping table unit - Google Patents
Implementation method for expanding solid state disk mapping table unit Download PDFInfo
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
Abstract
The invention discloses a realization method for expanding a mapping table unit of a solid state disk, which comprises a memory DDR corresponding to the solid state disk, wherein the DDR comprises a mapping table and an error correction code ECC, and when the address space of the mapping table is increased, the bit width of each mapping table unit is increased by using a method of embedding the error correction code ECC. The invention uses ECC check, combines multiple mapping table units into a mapping table combination for the characteristic that the data/check ratio can be improved after the data bit number is improved, and uses the method of embedded check bit for the combination, thereby more efficiently using the check interval of the traditional mapping table cache, enlarging the size of the physical address and improving the supported flash mapping table by multiple times. Moreover, the solid state disk mostly supports the design of merging a plurality of continuous LBAs and searching a mapping table, and no extra hardware/firmware overhead is added.
Description
Technical Field
The invention relates to the technical field of data storage, in particular to a method for realizing expansion of a mapping table unit of a solid state disk.
Background
The mapping table for the solid state disk is a lookup table for looking up a physical address in a flash memory device (NAND) of a computer according to a logical address in a master control. Where the logical address is translated from the logical address of the host data, typically a translation of namespace and Logical Block Address (LBA). And the physical address refers to addressing of the NAND flash memory. Because the NAND flash memory needs to be erased and written in blocks, the same logical address may be placed at any physical address, so a mapping table from the logical address to the physical address needs to be established.
In the enterprise-level solid state disk master control, a full mapping mode is usually adopted, and a mapping table is placed in a cache region of an off-chip DDR (double data rate) to meet the requirements of low delay and high stability in reading data. And because the error rate of DDR can not meet the requirement of the enterprise-level solid state disk, ECC protection is added during the read-write of DDR.
In an enterprise-level solid state disk, a mapping table is a lookup table that locates the physical address of a flash memory by the logical address of a host. In order to ensure the stability of reading data, a full mapping method is usually used, that is, a physical address corresponding to a logical address can be found according to the logical address by one-time query. While the lookup table size and flash memory size are typically 1: 1000, so if it is a 4TB hard disk, the mapping table size will reach 4GB, typically stored in the off-chip DDR; when the mapping table is stored, in order to ensure the accuracy, an error correction code is usually added to the accessed data, so that the error correction code occupies the storage space of the DDR, and the storage space of the mapping table becomes smaller, therefore, how to increase the storage space of the mapping table is a problem to be solved.
Disclosure of Invention
The invention aims to provide a method for expanding a mapping table unit of a solid state disk, aiming at the defects of the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
the method for realizing the expansion of the mapping table unit of the solid state disk comprises a memory DDR corresponding to the solid state disk, wherein the DDR comprises a mapping table and an error correction code ECC, and when the address space of the mapping table is enlarged, the bit width of each mapping table unit is increased by using a method of embedding the error correction code ECC.
Further, the method for using the embedded check bits increases the bit width of each mapping table unit by reducing the size of the error correction code ECC.
Further, the reduction of the size of the error correction code ECC is achieved by program control.
Furthermore, the method also comprises the step of combining a plurality of mapping table units into one mapping table combination, and using an error correction code ECC for protection for each mapping table combination.
Compared with the prior art, the invention combines a plurality of mapping table units into a mapping table combination for the characteristic that the data/check ratio can be improved after the data bit number is improved when ECC check is utilized, adopts a method of embedding check bits for the combination, more efficiently utilizes the check interval of the traditional mapping table cache, enlarges the size of a physical address, and improves the supported flash memory mapping table by multiple times. For example, only 4TB flash memory mapping table solid state disk master control can be supported, and after the method is adopted, 32TB (70 bit wide DDR interface) or 1PB (40 bit wide DDR interface) can be supported. Meanwhile, due to the access characteristic of DDR, most solid state disks support the design of merging and searching mapping tables of a plurality of continuous LBAs, and no extra hardware/firmware overhead is increased.
Drawings
FIG. 1 is a diagram illustrating the updating of a mapping table provided in the second embodiment;
FIG. 2 is an ECC protection diagram of a mapping table according to the second embodiment;
fig. 3 is a schematic diagram of an extended ECC group mapping table according to the second embodiment.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
The invention aims to provide a method for expanding a mapping table unit of a solid state disk, aiming at the defects of the prior art.
Example one
The embodiment provides an implementation method for expanding mapping table units of a solid state disk, which comprises a memory DDR corresponding to the solid state disk, wherein the DDR comprises a mapping table and an error correction code ECC, and when an address space of the mapping table is enlarged, the bit width of each mapping table unit is increased by using a method of embedding the error correction code ECC.
In an enterprise-level solid state drive, the mapping table is a lookup table that locates the Flash Physical Address (FPA) by the host's logical address (LBA). In order to ensure the stability of reading data, a full mapping method is usually used, that is, a physical address corresponding to a logical address can be found according to the logical address by one-time query. While the lookup table size and flash memory size are typically 1: 1000, e.g. a 4TB hard disk, the mapping table size will reach 4GB, and for the convenience of organizing the lookup table, the FPA is typically 32 bits wide, so the mapping table is typically stored in an off-chip DDR (double data rate synchronous dynamic random access memory).
When storing the mapping table, in order to ensure the correct rate, it is usually necessary to add error correction codes to the accessed data, i.e. add ECC (error checking and correcting) to the mapping table. However, in the actual use process, it is desired to expand the address space of the mapping table, and this embodiment provides a method of using an embedded error correction code ECC (inline ECC), that is, reducing the size of the ECC, and further increasing the bit width of each mapping table unit, so as to achieve the purpose of increasing the address space of the mapping table.
DDR is usually 64bit (8B) data +8bit (1B) ECC check, embedded ECC is that data and check bits are distinguished without being on a data bus of DDR, and embedded ECC is that ECC is embedded in data.
In this embodiment, the method of reducing ECC can be controlled by a program, such as RS-ECC, and how much the ECC is reduced is controlled according to the actual situation.
For example, the following steps are carried out:
the data of 9 bits by 8 bits is made into ECC together with the data of 72 bits, under the normal condition, the data of the mapping table is 64 bits, the check bit of the ECC is 8 bits, when the data of the mapping table is required to be expanded, the check bit of the ECC is reduced to 2 bits, at this time, the data of the mapping table is 70 bits, and therefore the purpose of expanding the address space of the mapping table is achieved.
When the space address of the mapping table is enlarged, the size of the hard disk correspondingly supported is also enlarged, specifically:
the bit number of the mapping table unit is in corresponding relation with the size of the hard disk, wherein each address corresponds to 4 KB;
under normal conditions, if a single mapping unit is a 32-bit address space, the address space of 32 bits can correspond to the indexed hard disk address of 4G, and if one hard disk address corresponds to 4KB, the hard disk address of 4G can support a hard disk of 16 TB.
In this embodiment, by reducing the check bits of the ECC, a single mapping unit can be changed from a 32-bit address space to a 35-bit address space, the 35-bit address space can correspond to the indexed hard disk address of 32G, and if one hard disk address corresponds to 4KB, the hard disk address of 32G can support a 128TB hard disk.
The technical scheme of the embodiment realizes the expansion of the address space of the mapping table, originally, a mapping table unit 32bit is expanded to a mapping table unit 35bit, and the size of the supported hard disk is expanded from 16TB to 128 TB. However, if the size of the error correction code continues to be reduced, the size of the hard disk can continue to be increased.
For the scheme of this embodiment, when the size of the ECC is reduced, the accuracy of the access data in the mapping table is not reduced, because the solid state disk stores the mapping table periodically and also has a method for recovering the mapping table, the effective data rate of encoding can be increased, and the size of the error correction code is reduced. Where the effective data rate refers to the ratio of data bits/(data + parity bits) bits.
In the embodiment, the position used for storing the ECC is used as an extended area of the data, a plurality of mapping table units are combined into one mapping table combination, and ECC protection is used for each combination.
In this embodiment, since a plurality of mapping table units are combined, reading and writing of any unit therein becomes reading and writing of the whole combination, which increases complexity. However, the read-write length for DDR is usually several bytes, for example 64 bytes, so that the hardware overhead is not increased in real condition. On the contrary, since in the solid state disk master, a plurality of consecutive LBAs (e.g. 16 LBAs) are usually combined into one operation, in this case, just corresponding to the mapping table combination, no additional overhead is added.
Example two
The implementation method for expanding the solid state disk mapping table unit provided by the embodiment is different from the first embodiment in that:
the present embodiment is illustrated by specific examples.
Because the solid state disk can only be erased and written according to pages, the data of the logical address cannot be directly written in an overlaying mode. To solve this problem, a mapping table is introduced to correspond to the relationship between the logical address of the host and the physical address in the flash memory. As shown in fig. 1, when the host writes data to the logical address LBA of 0x4 for the first time, the data is written to the physical address FPA of 0x 3000. When the host continues writing the logical address LBA equal to 0x4 for the second time, the data cannot overwrite the location where FPA is 0x3000 again, and can only be written into FPA equal to 0x 3001.
Generally, for the convenience of CPU management and maintenance, the maximum FPA is 32 bits of data, and thus corresponds to a space of 4G LBAs at most, and if one LBA corresponds to a logical block of 4K bytes, the maximum FPA of 32 bytes corresponds to a flash hard disk of 16TB bytes. Since the mapping table data is relatively large, it is generally stored in the off-chip DDR, and usually, in order to ensure the correctness of the data, protection of ECC is added, as shown in fig. 2. Each buffer unit is 64 bits, two physical addresses can be put in, and then 8 bytes of ECC is used for protection.
However, with the improvement of flash memory technology, the capacity of a single hard disk is also getting larger and larger, and a 16TB hard disk cannot meet the capacity requirement of the single hard disk, wherein the solution includes:
1. enlarging the logical block size for a single LBA, for example, up to 8KB or 16 KB;
2. the number of bits of the FPA is increased, and for convenience of calculation, one byte is usually added, that is, one FPA is 40 bits, so that the FPA can correspond to the size of a 4PB hard disk, and the requirement is far met.
However, corresponding to scheme 1, the upper layer driver is required to change the size of a single logic block to 8KB/16KB, which wastes system memory, and some systems need to run under the size of 512B logic blocks, so that each time the flash memory is read and written 512, the 16KB read-change overlay process corresponding to the flash memory is performed, and the performance of the solid state disk is reduced.
Corresponding to the scheme 2, the cache size of the solid state disk is increased, and the logic complexity of the address searching is increased because the 5-byte physical address is not the power of 2.
In the method, the physical address (FPA) is extended by using the check bits of the DDR data, as shown in fig. 3, each physical address is extended from 32 bytes to 35 bytes, and then the maximum capacity of the corresponding hard disk is increased from 16TB bytes to 128TB bytes. Can completely meet the requirement of the current hard disk capacity. And two physical addresses are used as an ECC group for checking and expanded to 16 physical addresses used as an ECC group for checking, so that the requirements of partial ECC and DDR read-write are increased. But still meets the requirements of reliability and high performance.
For reliability, the error rate of DDR is not increased by adopting the scheme of 16-bit ECC protection 560 bits. For example, DDR has a single bit error rate of 10e-9If so, then the probability of the method for a 2bit error is 560x10e-18＝5.6e-16. Each mapping table modification corresponds to 4 kbytes of data, so that the error rate corresponding to the data is 5.6e-16560/(4096 × 8) is about 0.96e-17The error rate requirement of the enterprise-level solid state disk can be met. Secondly, the error of the mapping table can be repaired by the method of recovering the mapping table, and the error of the data can not be really caused.
For high performance requirements, this can be done with hardware support for mapping tables. In the enterprise-level solid state disk solution, the update and reading of the mapping table must be accelerated using hardware logic to meet the performance requirements. The logic of the modification is not so much.
Compared with the prior art, the invention combines a plurality of mapping table units into a mapping table combination for the characteristic that the data/check ratio can be improved after the data bit number is improved when ECC check is utilized, adopts a method of embedding check bits for the combination, more efficiently utilizes the check interval of the traditional mapping table cache, enlarges the size of a physical address, and improves the supported flash memory mapping table by multiple times. For example, only 4TB flash memory mapping table solid state disk master control can be supported, and after the method is adopted, 32TB (70 bit wide DDR interface) or 1PB (40 bit wide DDR interface) can be supported. Meanwhile, due to the access characteristic of DDR, most solid state disks support the design of merging and searching mapping tables of a plurality of continuous LBAs, and no extra hardware/firmware overhead is increased.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (4)
1. The method for realizing the expansion of the mapping table unit of the solid state disk comprises a memory DDR corresponding to the solid state disk, and is characterized in that the DDR comprises a mapping table and an error correction code ECC, and when the address space of the mapping table is enlarged, the bit width of each mapping table unit is increased by using a method of embedding the error correction code ECC.
2. The method of claim 1, wherein the bit width of each mapping table unit is increased by reducing the size of an Error Correction Code (ECC) by using the embedded check bits.
3. The method of claim 2, wherein the reduction of the size of the Error Correction Code (ECC) is achieved by program control.
4. The method of claim 3, further comprising combining multiple mapping table units into one mapping table combination, and using error correction code ECC for protection for each mapping table combination.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114707478A (en) * | 2022-06-06 | 2022-07-05 | 飞腾信息技术有限公司 | Mapping table generation method, device, equipment and storage medium |
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