CN113541491B - Multi-mode switching low-dynamic-interference 4-tube synchronous control buck-boost conversion circuit - Google Patents

Multi-mode switching low-dynamic-interference 4-tube synchronous control buck-boost conversion circuit Download PDF

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CN113541491B
CN113541491B CN202110814161.4A CN202110814161A CN113541491B CN 113541491 B CN113541491 B CN 113541491B CN 202110814161 A CN202110814161 A CN 202110814161A CN 113541491 B CN113541491 B CN 113541491B
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electrode
nmos transistor
drain electrode
pmos transistor
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CN113541491A (en
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方建平
谢瑞
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Tuoer Microelectronics Co ltd
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Tuoer Microelectronics Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H02M3/1582—Buck-boost converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention discloses a multi-mode switching low-dynamic-interference 4-transistor synchronous control buck-boost conversion circuit which comprises a power level transmission circuit, a current sampling circuit, an oscillator, a ramp generator, a pulse modulation circuit, an error amplifier, a sequential control logic circuit, a hysteresis mode selection circuit and a direct-current offset voltage circuit. The time sequence control logic circuit controls the 4-tube switch by designing time sequence in a split mode. The hysteretic mode selection circuit reduces output voltage ripple degradation through the hysteretic comparator. The direct current offset voltage circuit is used for reducing dynamic interference generated during mode switching. The 4-tube synchronous control buck-boost conversion circuit provided by the invention can solve the problems of output voltage ripple deterioration and large dynamic interference caused by frequent switching of the working modes of the existing buck-boost conversion circuit on the premise of providing reliable output voltage.

Description

Multi-mode switching low-dynamic-interference 4-tube synchronous control buck-boost conversion circuit
Technical Field
The invention belongs to the technical field of microelectronics, and further relates to a multi-mode switching low-dynamic-interference 4-tube synchronous control buck-boost conversion circuit in the technical field of integrated circuits. The invention can be used for controlling the switching of multiple working modes of the power supply module of the electronic equipment in the integrated circuit.
Background
In recent years, boost-buck converters are widely used in battery-powered electronic devices, and how to prolong the operating time of a battery power supply under the same battery capacity becomes a primary problem in the field of power management. The buck-boost converter can continue to work under the condition of lower input voltage when supplying power to the electronic equipment by increasing the range of the input voltage, so that the service time of the battery power supply can be prolonged. However, due to the characteristic of phase inversion between the input voltage and the output voltage of the conventional buck-boost converter, a negative reference voltage generally needs to be realized inside the circuit, and meanwhile, an inverter circuit needs to be added between the output end and the electronic device to be powered, which undoubtedly increases the difficulty of circuit design and also limits application conditions. In order to stabilize the output voltage when the power supply mode is flexibly selected by the electronic device, the buck-boost converter control circuit has to automatically switch the mode according to the input and output voltages, and the output voltage ripple cannot be disordered due to mode switching and can be smoothly transited.
The patent technology owned by Nanjing aerospace university 'a cascade type buck-boost converter control circuit and a control method thereof' (application number 200910026525.1, no. CN 104242286B, no. 2011.02.16) provides a synchronous 4-tube buck-boost converter based on cascade type control. The converter structurally comprises an output voltage sampling circuit, two error amplifiers, a triangular wave generating circuit, a comparator circuit, a driving circuit and a voltage setting circuit. The converter is formed by cascading a boost converter and a buck converter, the circuit is simple, only one path of triangular wave is needed to control the two-stage circuit, and the conversion efficiency is high. The buck-boost converter effectively overcomes the defect of the basic synchronous 4-tube buck-boost converter in efficiency, but the buck-boost converter still has the defect that the duty ratio of the buck-boost converter cannot continuously and stably change during mode switching, so that the output voltage generates a large dynamic effect during mode switching, and the stability and the reliability of the converter are influenced.
The patent document of shanghai south core semiconductor technology limited in its application "a buck-boost converter control circuit with mode switching" (application number 202110451038.0, application publication number CN 112994452A) proposes a four-mode 4-tube synchronous buck-boost converter. The buck-boost converter structurally comprises a differential processing module, a double-track current sampling module, a ramp signal generating module and a logic control module, wherein an output signal is generated by the difference value of sampling values of a signal output by the differential processing module and a signal at a switch node, and a pulse width modulation signal for boost control and buck control is obtained by comparing the output signal with a buck ramp signal and a boost ramp signal respectively, wherein the ramp signal generating module is used for generating the buck ramp signal and the boost ramp signal with an overlapped interval, and finally, the logic control module generates control signals of four switch tubes in the buck-boost converter. The buck ramp signal and the boost ramp signal are obtained through the ramp signal generation module, the discontinuous duty ratio of the buck-boost converter during mode switching is relieved, however, the buck-boost converter still has the defects that the design difficulty of circuit control logic is large and the cost of circuit design is high in order to generate control driving signals of four switching tubes.
Disclosure of Invention
The invention aims to provide a multi-mode switching low-dynamic-interference 4-transistor synchronous control buck-boost conversion circuit aiming at solving the problems of output voltage ripple deterioration and large dynamic interference caused by frequent switching of the working modes of a buck-boost converter on the premise of providing stable power supply voltage for electronic equipment.
In order to achieve the above purpose, the idea of the present invention is to perform a segmented control according to an input voltage value through a hysteresis mode selection circuit, output a comparison signal between an input voltage and an output voltage through a comparator, control a converter to switch frequently between a buck mode, a buck-boost mode, and a boost mode, and design the comparator to have a hysteresis function, so as to avoid output voltage ripple deterioration caused by frequent switching between the modes. Through the direct current offset voltage circuit, dynamic interference generated during mode switching is reduced, and output voltage is stabilized. Through the sequential control logic circuit, the action times of the switching tubes of the converter at high input voltage and low input voltage are reduced, and 4 power switching tubes work simultaneously in one switching period only when the converter realizes the voltage boosting and reducing function, so that the efficiency of the converter is improved.
The 4-transistor synchronous control buck-boost conversion circuit comprises an input voltage port VIN, an output voltage port VOUT, a power level transmission circuit, a current sampling circuit, an oscillator, a ramp generator, a pulse modulation circuit, an error amplifier, a time sequence control logic circuit, a hysteresis mode selection circuit and a direct current offset voltage circuit. The input port pwm of the time sequence control logic circuit is connected with the output port of the pulse modulation, the input port clk is connected with the output port ramp of the oscillator and the ramp generator, the input port mode is connected with the output port of the hysteresis mode selection circuit, the output port 1 is connected with the port TG1 of the power level transmission circuit, the output port 2 is connected with the port BG1 of the power level transmission circuit, the output port 3 is connected with the port BG2 of the power level transmission circuit, and the output port 4 is connected with the port TG2 of the power level transmission circuit; an input end 1 of the hysteresis mode selection circuit is connected with an output voltage port VIN, an input end 2 of the hysteresis mode selection circuit is connected with an output voltage port VOUT, and output ports of the hysteresis mode selection circuit are respectively connected with an input end of the direct-current offset voltage circuit and an input port of the sequential control logic circuit mode; the positive input port of the pulse modulation circuit is respectively connected with the current sampling circuit, the oscillator, the ramp generator output port ramp and the direct-current offset voltage circuit output port, the negative input port is connected with the error amplifier output port, and the output port is connected with the sequential control logic circuit pwm input port; the input end of the direct current offset voltage circuit is connected with the output end of the hysteresis mode selection circuit, and the output end of the direct current offset voltage circuit is connected with the positive input end of the pulse modulation; the output port ramp of the oscillator and the ramp generator is connected with the output port of the current sampling circuit; the positive input port of the current sampling circuit is connected with a port SENS + of the power level transmission circuit, the negative input port of the current sampling circuit is connected with a port SENS-, and the output port of the current sampling circuit is connected with the positive input end of the pulse modulation circuit; a positive input port REF of the error amplifier is connected with a 1V reference voltage, and a negative input port is connected with a port FB of the power level transmission circuit; the input port of the power level transmission circuit is connected with an input voltage port VIN, an output voltage port is connected with an output voltage port VOUT, a SENS + port is connected with a positive input port of a current sampling circuit, a SENS-port is connected with a negative input port of the current sampling circuit, a TG1 port is connected with a first input port of a sequential control logic circuit, a BG1 port is connected with a second input port of the sequential control logic circuit, a BG2 port is connected with a third input port of the sequential control logic circuit, a TG2 port is connected with a fourth input port of the sequential control logic circuit, and an FB port is connected with a negative input port of an error amplifier.
Compared with the prior art, the invention has the following advantages:
firstly, because the invention designs a logic sequence module, generates control logics of three working modes through digital logics, generates a main clock signal by an oscillator, sets a clock falling edge as an initial moment of a switching period, and inputs enable signals en _ buck, en _ boost and en _ buck _ boost of the three working modes by a hysteresis mode selector, the problems of high design difficulty and high circuit design cost of a switching tube control logic mode in the prior art are solved, and the invention has the advantages of visual digital control logics and simple driving control of the switching tube.
Secondly, because the hysteresis control and direct-current offset voltage module is added between each mode, the problems of output voltage ripple deterioration and large dynamic interference caused by frequent switching between the modes in the prior art are solved, and the invention has more stable output voltage.
Drawings
FIG. 1 is a schematic diagram of the overall circuit of the present invention;
FIG. 2 is an electrical schematic of the DC offset voltage circuit of the present invention;
FIG. 3 is an electrical schematic of the hysteresis mode selection circuit of the present invention;
FIG. 4 is an electrical schematic of the timing control logic of the present invention;
FIG. 5 is an electrical schematic of the oscillator circuit of the present invention;
FIG. 6 is an electrical schematic of the ramp generating circuit of the present invention;
FIG. 7 is an electrical schematic of the pulse modulation circuit of the present invention;
fig. 8 is an electrical schematic of the error amplifier of the present invention.
FIG. 9 is a logic timing diagram of the conditions for entering three modes of operation and outputting signals that drive the switch tube according to the present invention.
The specific implementation mode is as follows:
the present invention will be described in further detail with reference to the accompanying drawings.
Referring to fig. 1, the 4-transistor synchronous control buck-boost conversion circuit of the present invention is further described in detail.
The 4-transistor synchronous control buck-boost conversion circuit comprises an input voltage port VIN, an output voltage port VOUT, a power level transmission circuit, a current sampling circuit, an oscillator, a ramp generator, a pulse modulation circuit, an error amplifier, a time sequence control logic circuit, a hysteresis mode selection circuit and a direct current offset voltage circuit. The input port pwm of the time sequence control logic circuit is connected with the output port of the pulse modulation, the input port clk is connected with the output port ramp of the oscillator and the ramp generator, the input port mode is connected with the output port of the hysteresis mode selection circuit, the output port 1 is connected with the port TG1 of the power level transmission circuit, the output port 2 is connected with the port BG1 of the power level transmission circuit, the output port 3 is connected with the port BG2 of the power level transmission circuit, and the output port 4 is connected with the port TG2 of the power level transmission circuit; an input end 1 of the hysteresis mode selection circuit is connected with an output voltage port VIN, an input end 2 of the hysteresis mode selection circuit is connected with an output voltage port VOUT, and an output end of the hysteresis mode selection circuit is respectively connected with an input end of the direct current offset voltage circuit and an input port of the sequential control logic circuit mode. The positive input port of the pulse modulation circuit is respectively connected with the current sampling circuit, the oscillator, the ramp generator output port ramp and the direct current offset voltage circuit output port, the negative input port is connected with the error amplifier output port, and the output port is connected with the sequential control logic circuit pwm input port. The input end of the direct current offset voltage circuit is connected with the output end of the hysteresis mode selection circuit, and the output end of the direct current offset voltage circuit is connected with the positive input end of the pulse modulation. And the output port ramp of the oscillator and the ramp generator is connected with the output port of the current sampling circuit. The positive input port of the current sampling circuit is connected with a port SENS + of the power level transmission circuit, the negative input port of the current sampling circuit is connected with a port SENS-, and the output port of the current sampling circuit is connected with the positive input end of the pulse modulation circuit. A positive input port REF of the error amplifier is connected with a 1V reference voltage, and a negative input port is connected with a port FB of the power level transmission circuit; the input port of the power level transmission circuit is connected with an input voltage port VIN, an output voltage port is connected with an output voltage port VOUT, a SENS + port is connected with a positive input port of a current sampling circuit, a SENS-port is connected with a negative input port of the current sampling circuit, a TG1 port is connected with a first input port of a sequential control logic circuit, a BG1 port is connected with a second input port of the sequential control logic circuit, a BG2 port is connected with a third input port of the sequential control logic circuit, a TG2 port is connected with a fourth input port of the sequential control logic circuit, and an FB port is connected with a negative input port of an error amplifier.
The power level transmission circuit comprises a current sampling resistor Rsense, an NMOS transistor K1b, an inductor L, an NMOS transistor K2b, a divider resistor R1, a divider resistor R2, an output capacitor Cout and a load resistor Rout. The current sampling resistor Rsense is connected between the positive input end SENS + of the current sampling circuit and the negative input end SENS-of the current sampling circuit in a bridge mode. The drain electrode of the NMOS transistor K1 is connected with one end of a current sampling resistor Rsense, the source electrode is connected with one end SW1 of an inductor L, and the grid electrode is connected with a drive control output TG 1. The drain electrode of the NMOS transistor K1b is connected with one end SW1 of the inductor L, the source electrode is connected with the ground end, and the grid electrode is connected with the sequential control logic output BG 1. The inductor L is connected between the source electrode of the NMOS transistor K1 and the drain electrode of the NMOS transistor K2 in a bridging mode. And the drain electrode of the NMOS transistor K2 is connected with the SW2 end of the inductor L, the source electrode of the NMOS transistor K2 is connected with the ground end, and the grid electrode of the NMOS transistor K2 is connected with the sequential control logic output BG 2. The drain electrode of the NMOS transistor K2b is connected with one end of the divider resistor R1, the source electrode is connected with the SW2 end of the inductor L, and the grid electrode is connected with the sequential control logic output TG 2. The voltage dividing resistor R1 is connected between the drain electrode of the NMOS transistor K2b and the voltage dividing resistor R2 in a bridge mode. The voltage dividing resistor R2 is bridged between the ground end and the voltage dividing resistor R1. The output capacitor Cout is connected across the drain of the NMOS transistor K2b and ground. One end of the load resistor Rout is connected with the drain electrode of the NMOS transistor K2b, and the other end of the load resistor Rout is connected with the ground end. And the output end of the oscillator is connected with the ramp generator and the second input end of the time sequence control logic. The input end of the slope generator is connected with the output end of the oscillator, and the output end of the slope generator is connected to the positive input end of the pulse modulation after being added with the signal of the current sampling output end. The positive input end of the pulse modulation circuit is connected with the output end of the direct-current offset voltage circuit, the negative input end of the pulse modulation circuit is connected with the output end of the error amplifier, and the output end pwm of the pulse modulation circuit is connected with the first input port of the logic time sequence module. The positive input port of the error amplifier is connected with a 1V reference voltage REF, the negative input port FB is connected with one end of a divider resistor R2, and the output port is connected with the pulse modulation negative input port.
Referring to fig. 2, the dc offset voltage circuit of the present invention will be described in further detail.
The direct-current offset voltage circuit comprises a power supply port Vdd, a ground port GND, PMOS transistors M1, M2, M3, M4 and M5, a current source IDC, a boost mode enabling signal en _ boost input port, resistors R1 and R2, a current sampling input signal Vsen and a direct-current output offset signal Vramp. The source electrode of the PMOS transistor M1 is connected with a power supply port Vdd, the grid electrode of the PMOS transistor M1 is connected with the grid electrode of the PMOS transistor M2, and the drain electrode of the PMOS transistor M3 is connected with the source electrode of the PMOS transistor M3. The source electrode of the PMOS transistor M2 is connected with a power supply port Vdd, the grid electrode of the PMOS transistor M2 is connected with the grid electrode of the PMOS transistor M1, and the drain electrode of the PMOS transistor M2 is connected with the source electrode of the PMOS transistor M4. And the source electrode of the PMOS transistor M3 is connected with the drain electrode of the M1, the grid electrode of the PMOS transistor M3 is connected with the grid electrode of the M4, and the drain electrode of the PMOS transistor M is connected with the current source IDC. And the source electrode of the PMOS transistor M4 is connected with the drain electrode of the M2, the grid electrode of the PMOS transistor M4 is connected with the grid electrode of the M3, and the drain electrode of the PMOS transistor M4 is connected with the source electrode of the M5. The source electrode of the PMOS transistor M5 is connected with the source electrode of the PMOS transistor M4, the grid electrode of the PMOS transistor M5 is connected with the boost mode enabling signal en _ boost input port, and the drain electrode of the PMOS transistor M is connected with the resistor R1. The resistor R1 is connected across the current sampling input signal Vsen and the dc output offset signal Vramp. The resistor R2 is connected across the current sample input signal Vsen and the ground port GND.
The hysteresis mode selection circuit of the present invention is described in further detail with reference to fig. 3.
The hysteresis mode selection circuit comprises a power supply port Vdd, a ground port GND, a mode selection enabling port SEL _ en, a mode enabling output port en, an input voltage port Vin, an output voltage port Vout, PMOS transistors M1-M3, NMOS transistors M4-M9, resistors R1-R5, current sources IDC1 and IDC2 and an inverter INV1. The source electrode of the PMOS transistor M1 is connected with a power supply port Vdd, the grid electrode of the PMOS transistor M1 is connected with a mode selection enabling port SEL _ en, and the drain electrode of the PMOS transistor M1 is connected with a current source IDC 1. The source electrode of the PMOS transistor M2 is connected with the current source IDC1, the grid electrode of the PMOS transistor M2 is connected with one end of the resistor R4, and the drain electrode of the PMOS transistor M2 is connected with the drain electrode of the NMOS transistor M5. The source electrode of the PMOS transistor M3 is connected with a current source IDC1, the grid electrode of the PMOS transistor M3 is connected with one end of a resistor R1, and the drain electrode of the PMOS transistor M3 is connected with the drain electrode of an NMOS transistor M7. The gate of the NMOS transistor M4 is connected to the mode enable output port en, the drain is connected to one end of the resistor R2, and the source is connected to the ground port GND. And the grid electrode of the NMOS transistor M5 is connected with the grid electrode of the M7, the drain electrode of the NMOS transistor M2 is connected with the drain electrode of the M2, and the source electrode of the NMOS transistor M5 is connected with a ground port GND. The gate of the NMOS transistor M6 is connected with a mode selection enabling port SEL _ en, the drain is connected with the gate of the NMOS transistor M5, and the source is connected with a ground port GND. And the grid electrode of the NMOS transistor M7 is connected with the drain electrode of the M6, the drain electrode of the NMOS transistor M is connected with the grid electrode of the M8, and the source electrode of the NMOS transistor M is connected with a ground port GND. And the grid electrode of the NMOS transistor M8 is connected with the drain electrode of the M7, the drain electrode of the NMOS transistor M is connected with the current source IDC2, and the source electrode of the NMOS transistor M is connected with the ground port GND. The gate of the NMOS transistor M9 is connected to the mode selection enable port SEL _ en, the drain is connected to the current source IDC2, and the source is connected to the ground port GND. The upper end of the current source IDC1 is connected with a power supply port Vdd, and the lower end of the current source IDC1 is connected with a source electrode of the M2. The upper end of the current source IDC2 is connected with a power supply port Vdd, and the lower end of the current source IDC is connected with an M8 source electrode. The input end of the inverter INV1 is connected with the drain electrode of the M8, and the output end is the mode enabling output port en.
Referring to fig. 4, the timing control logic module of the present invention is described in further detail.
The sequential control logic module comprises an input voltage Vin port, an output voltage Vout port, a Mode selection port SEL _ en, an input clock port clk, a buck Mode output control signal en _ buck, a buck-boost Mode output control signal en _ buck-boost, a boost Mode output control signal en _ boost, a logic error signal error, a first hysteresis Mode selector Mode _ Sel _1, a second hysteresis Mode selector Mode _ Sel _2, a first D trigger, a second D trigger and a two-wire decoder. The output port of the hysteresis Mode selector Mode _ Sel _1 is connected with the input port of the first D flip-flop. The output port of the hysteresis Mode selector Mode _ Sel _2 is connected with the input port of the second D flip-flop. The output port of the first D flip-flop is connected with the input port of the two-four-wire decoder. And the output port of the second D flip-flop is connected with the input port of the two-four-wire decoder.
The oscillator module of the present invention is described in further detail with reference to fig. 5.
The oscillator module comprises a power supply port Vdd, a ground port GND, a 0.9V reference voltage input port, current sources IDC 1-IDC 3, an NMOS transistor M1, an NMOS transistor M4, an NMOS transistor M5, an NMOS transistor M6, a PMOS transistor M2, a PMOS transistor M3, a capacitor C1, inverters INV1 AND INV2 AND an AND gate AND 1. The upper end of the current source IDC1 is connected with a power supply port Vdd, and the lower end of the current source IDC1 is connected with the grid electrode of the PMOS transistor M2. The upper end of the current source IDC2 is connected with a power supply port Vdd, and the lower end of the current source IDC2 is connected with the source electrode of the PMOS transistor M2. The upper end of the current source IDC3 is connected with a power supply port Vdd, and the lower end of the current source IDC is connected with the drain electrode of the NMOS transistor M4. The grid electrode of the NMOS transistor M1 is connected with the output of the inverter INV1, the drain electrode of the NMOS transistor M1 is connected with the source electrode of the PMOS transistor M2, and the source electrode of the NMOS transistor M1 is connected with the ground port GND. And the grid electrode of the NMOS transistor M4 is connected with the drain electrode of the PMOS transistor M3, the drain electrode is connected with the upper end of the current source IDC3, and the source electrode is connected with a ground port GND. The grid electrode of the NMOS transistor M5 is connected with the grid electrode of the NMOS transistor M6, the drain electrode of the NMOS transistor M2 is connected with the drain electrode of the NMOS transistor M2, and the source electrode of the NMOS transistor M is connected with the ground port GND. The grid electrode of the NMOS transistor M6 is connected with the grid electrode of the NMOS transistor M5, the drain electrode of the NMOS transistor M3 is connected with the drain electrode of the NMOS transistor M3, and the source electrode of the NMOS transistor M6 is connected with a ground port GND; and the upper polar plate of the capacitor C1 is connected with the grid of the M2, and the lower polar plate is connected with a ground port GND. The input of the inverter INV1 is connected with the output of an OR gate AND1, AND the output of the inverter INV1 is connected with the grid electrode of M1; the input of the inverter INV2 is connected with the drain electrode of the M4, AND the output of the inverter INV2 is connected with the input of an OR gate AND1; the first input end of the OR gate is connected with the input of the inverter INV1, the second input end of the OR gate is connected with the output of the inverter INV1, and the output end of the OR gate is connected with the input of the inverter INV1.
The ramp generator of the present invention is described in further detail with reference to fig. 6.
The slope generator comprises a power supply port Vdd, a ground port GND, a clock input port clk, a slope output port Vramp, a current source IDC1, inverters INV1 and INV2, a capacitor C1, a resistor R1, NMOS transistors M1-M4, an NMOS transistor M9 and PMOS transistors M5-M8. The upper end of the current source IDC1 is connected with a power supply port Vdd, and the lower end of the current source IDC1 is connected with the source electrode of the NMOS transistor M1. The input end of the inverter INV1 is connected to the clock input port clk, and the output end is connected to the input end of the inverter INV 2. The input end of the inverter INV2 is connected with the output end of the inverter INV1, and the output end of the inverter INV2 is connected with the grid electrode of the NMOS transistor M2. And the upper polar plate of the capacitor C1 is connected with the source electrode of the NMOS transistor M3, and the lower polar plate is connected with a ground port GND. The resistor R1 is connected between the source electrode of the NMOS transistor M9 and the ground port GND in a bridging mode. The grid electrode of the NMOS transistor M1 is connected with the output end of the inverter INV1, the source electrode of the NMOS transistor M1 is connected with the upper end of the current source IDC1, and the drain electrode of the NMOS transistor M1 is connected with the source electrode of the M2. The grid electrode of the NMOS transistor M2 is connected with the output end of the inverter INV2, the source electrode of the NMOS transistor M2 is connected with the drain electrode of the M1, and the drain electrode of the NMOS transistor M2 is connected with the source electrode of the M1. And the grid electrode of the NMOS transistor M3 is connected with the source electrode of the M1, the source electrode is connected with the upper polar plate of the capacitor C1, and the drain electrode is connected with a ground port GND. And the grid electrode of the NMOS transistor M4 is connected with the grid electrode of the M1, the drain electrode of the NMOS transistor M4 is connected with the upper polar plate of the capacitor C1, and the source electrode of the NMOS transistor M4 is connected with a ground port GND. And the grid electrode of the PMOS transistor M5 is connected with the grid electrode of the M6, the drain electrode of the PMOS transistor M5 is connected with the source electrode of the M7, and the source electrode of the PMOS transistor M is connected with a power supply port Vdd. The grid electrode of the PMOS transistor M6 is connected with the grid electrode of the M5, the drain electrode of the PMOS transistor M6 is connected with the source electrode of the M8, and the source electrode of the PMOS transistor M6 is connected with the drain electrode of the M6; and the grid electrode of the PMOS transistor M7 is connected with the grid electrode of the M8, the drain electrode of the PMOS transistor M7 is connected with the source electrode of the M9, and the source electrode of the PMOS transistor M7 is connected with the drain electrode of the M5. And the grid electrode of the PMOS transistor M8 is connected with the grid electrode of the PMOS transistor M7, the drain electrode of the PMOS transistor M8 is connected with the source electrode of the PMOS transistor M6, and the source electrode of the PMOS transistor M is connected with the ramp output port Vramp. And the grid electrode of the NMOS transistor M9 is connected with the grid electrode of the M3, the drain electrode of the NMOS transistor M7 is connected with the drain electrode of the M7, and the source electrode of the NMOS transistor M9 is connected with one end of the resistor R1.
The pulse modulation circuit of the present invention is described in further detail with reference to fig. 7.
The pulse modulation circuit comprises a power supply port Vdd, a ground port GND, a pulse modulation positive input end Vp, a pulse modulation negative input end Vn, a pulse modulation output signal PWM port, a current source IDC1, resistors R1 and R2, PMOS transistors M1-M6, PMOS transistors M8-M9, an NMOS transistor M7 and NMOS transistors M10-M12. The grid electrode of the PMOS transistor M1 is connected with the grid electrode of the PMOS transistor M2, the source electrode of the PMOS transistor M1 is connected with a power supply port Vdd, and the drain electrode of the PMOS transistor M1 is connected with a current source IDC 1. The grid electrode of the PMOS transistor M2 is connected with the grid electrode of the PMOS transistor M1, the source electrode of the PMOS transistor M2 is connected with a power supply port Vdd, and the drain electrode of the PMOS transistor M2 is connected with the source electrode of the PMOS transistor M5. The grid electrode of the PMOS transistor M3 is connected with the grid electrode of the M1, the source electrode of the PMOS transistor M3 is connected with a power supply port Vdd, and the drain electrode of the PMOS transistor M3 is connected with the source electrode of the M8. The grid electrode of the PMOS transistor M4 is connected with the grid electrode of the M1, the source electrode of the PMOS transistor M4 is connected with a power supply port Vdd, and the drain electrode of the PMOS transistor M4 is connected with the drain electrode of the M12. The grid electrode of the PMOS transistor M5 is connected with the pulse modulation positive input end Vp, the source electrode is connected with the drain electrode of the M2, and the drain electrode is connected with the resistor R1. The grid electrode of the PMOS transistor M6 is connected with the pulse modulation negative input end Vn, the source electrode of the PMOS transistor M6 is connected with the drain electrode of the M2, and the drain electrode of the PMOS transistor M6 is connected with the resistor R2. And the grid electrode of the PMOS transistor M8 is connected with the drain electrode of the M5, the source electrode of the PMOS transistor M8 is connected with the drain electrode of the M3, and the drain electrode of the PMOS transistor M8 is connected with the drain electrode of the M10. And the grid electrode of the PMOS transistor M9 is connected with the drain electrode of the M6, the source electrode of the PMOS transistor M9 is connected with the drain electrode of the M3, and the drain electrode of the PMOS transistor M11 is connected with the drain electrode of the M11. And the grid electrode of the NMOS transistor M7 is connected with the R1, the source electrode of the NMOS transistor M is connected with the ground port GND, and the drain electrode of the NMOS transistor M is connected with the drain electrode of the M11. And the grid electrode of the NMOS transistor M10 is connected with the grid electrode of the M11, the source electrode of the NMOS transistor M is connected with the ground port GND, and the drain electrode of the NMOS transistor M is connected with the drain electrode of the M8. And the grid electrode of the NMOS transistor M11 is connected with the grid electrode of the M10, the source electrode of the NMOS transistor M is connected with the ground port GND, and the drain electrode of the NMOS transistor M is connected with the drain electrode of the M9. And the grid electrode of the NMOS transistor M12 is connected with the grid electrode of the M9, the source electrode of the NMOS transistor M is connected with the ground port GND, and the drain electrode of the NMOS transistor M is connected with the drain electrode of the M4.
The error amplifier of the present invention is described in further detail with reference to fig. 8.
The error amplifier comprises a power supply port Vdd, a ground port GND, an FB feedback voltage input port, a 1V reference voltage input port, an error amplifier output port, a current source IDC1, PMOS transistors M1 and M2 and NMOS transistors M3 and M4. The upper end of the current source IDC1 is connected with a power supply port Vdd, and the lower end of the current source IDC1 is connected with the source electrode of the PMOS transistor M1. And the source electrode of the PMOS transistor M1 is connected with the lower end of the current source IDC1, the grid electrode of the PMOS transistor M1 is connected with the FB feedback voltage input end, and the drain electrode of the PMOS transistor M1 is connected with the drain electrode of the NMOS transistor M3. And the source electrode of the PMOS transistor M2 is connected with the lower end of the current source IDC1, the grid electrode of the PMOS transistor M2 is connected with the 1V reference voltage input port, and the drain electrode of the PMOS transistor M2 is connected with the drain electrode of the NMOS transistor M4. And the source electrode of the NMOS transistor M3 is connected with the ground port GND, the grid electrode of the NMOS transistor M4 is connected, and the drain electrode of the NMOS transistor M1 is connected with the drain electrode of the PMOS transistor M. And the source electrode of the NMOS transistor M4 is connected with a ground port GND, the grid electrode of the NMOS transistor M4 is connected with the grid electrode of the NMOS transistor M3, and the drain electrode of the NMOS transistor M4 is connected with the drain electrode of the PMOS transistor M2.
The working principle of the 4-transistor synchronous control buck-boost conversion circuit of the invention is described in detail below.
According to the invention, an input voltage VIN provides an output voltage VOUT for a load Rout through a power level transmission circuit, a switch tube control signal of the power level transmission circuit outputs a switch signal with adjustable duty ratio through a time sequence control logic circuit, a current sampling circuit and an error amplifier monitor an inductive current and the output voltage in real time, and a comparator of a pulse modulation circuit generates a pwm pulse signal for controlling a switch by comparing an output signal of the error amplifier and the current sampling signal, so as to provide a duty ratio control signal for the time sequence control logic circuit.
The hysteresis mode selection circuit monitors input and output voltages in real time and outputs enable signals of a buck mode, a buck mode and a boost mode according to the relation between the input and output voltages. The hysteresis comparator outputs a mode control signal, the D trigger ensures that mode switching only occurs at the initial moment of a switching period, output ripple deterioration and logic errors caused by mode switching in the switching period are avoided, the two-four-wire decoder outputs enable signals of three modes and a logic error signal, and when the logic error signal error is at a high level, the system enters a protection mode. Table 1 gives a truth table for a two-four wire decoder, where 1 represents high and 0 represents low.
Table 1 truth table for two-four wire decoder
en 1 en 2 en_buck error en_buck-boost en_boost
1 1 1 0 0 0
1 0 0 1 0 0
0 1 0 0 1 0
0 0 0 0 0 1
When Vin in an initial state is far smaller than Vout, the output en of the hysteresis comparator is at a low level, R3 is connected into the circuit, when V in rises to a point B voltage which is higher than a point A voltage, an en signal turns high, the converter should be switched from a boost mode to a buck-boost mode, the en signal turns low, R3 is short-circuited at the moment, and the point A voltage is reduced; when Vin is reduced to a point B voltage which is lower than the reduced point A voltage, the converter is switched from the step-up mode to the step-up mode, so that the mutual conversion between the step-up mode and the step-down mode is completed, and the relationship of switching critical points is as follows:
boost mode to buck-boost mode:
Figure BDA0003169589360000101
step (2) from a voltage increasing mode to a voltage increasing mode:
Figure BDA0003169589360000102
the DC offset voltage module is a superposed signal V after the converter enters a boost mode sum And the direct-current offset voltage is superposed, so that overshoot and undershoot generated on the output voltage during mode switching are avoided. When the circuit works in a buck-boost mode, the average inductive current is as follows:
Figure BDA0003169589360000103
wherein, I load Representing the average current of the load, D boost And represents the duty cycle signal of the K2 tube in the boost mode. When the circuit is switched from the boost-buck mode to the boost-boost mode and reaches a steady state, the average current of the load of the converter is controlled by
I load ＝I L_avg_boost (1-D boost )
Is given in which L_avg_boost The average inductor current in the boost mode is represented, and the average inductor current in the two modes before and after the switching point is approximately equal, so that the difference between the superimposed signal before the boost mode is switched to the boost mode and the superimposed signal after the boost mode is switched is approximately equal to the peak-to-peak value of the slope compensation signal in the boost mode at the maximum duty ratio, and therefore:
V sum_os ＝V sum(buck-boost) -V sum(boost) ＝D buck-boost(max) TΔV ramp
wherein, V sum(buck-boost) A ramp voltage superposition signal, V, before switching from buck mode to boost mode sum(boost) Indicating the ramp voltage superimposed signal after switching to boost mode, D buck-boost(max) Represents the conduction duty ratio of the K1b tube in the voltage increasing and decreasing mode, delta V ramp Representing the peak-to-peak value of the slope compensation voltage.
The sequential logic of the sequential logic circuit in three operating modes of step-down, step-up and step-down will be further described with reference to fig. 9.
The time sequence control logic circuit generates control logics of three working modes through digital logic, a main clock signal clk is generated by an oscillator, a clock falling edge is set as the initial moment of a switching period, enabling signals en _ buck, en _ boost and en _ buck _ boost of the three working modes are input by a hysteresis mode selector, conditions for entering the three working modes and signals for outputting driving a switching tube are given by a graph 9, TG1 represents a control signal for driving a K1 tube in a voltage reduction mode, and BG2 represents a control signal for driving a K2 tube in a voltage boosting mode. When entering a voltage reduction mode, if the rising edge of clk or pwm does not arrive, TG1=0, BG2=1; otherwise, if clk = =1 or pwm = =1, both tg1 and BG2 output 0, otherwise TG1=1, bg2=0. When entering the boosting mode, if clk = =1 or pwm = =1, tg1=1, bg2=0 after the falling edge of clk or the rising edge of pwm arrives; otherwise, both TG1 and BG2 output 1. When entering the buck-boost mode, if clk = =1, bg2=0 after the rising edge of clk or the falling edge of pwm arrives, otherwise, if clk = =1 and pwm = =1, bg2=1, otherwise BG2=0.

Claims (9)

1. The utility model provides a 4 pipe synchro control buck-boost conversion circuit of low dynamic interference of multimode switch, includes input voltage port VIN, output voltage port VOUT, power level transmission circuit, current sampling circuit, oscillator and ramp generator, pulse modulation circuit, error amplifier, its characterized in that: the circuit also comprises a sequential control logic circuit, a hysteresis mode selection circuit and a direct current offset voltage circuit; the input port pwm of the sequential control logic circuit is connected with the output port of the pulse modulation, the input port clk is connected with the output port clk of the oscillator and the slope generator, the input port mode is connected with the output port of the hysteresis mode selection circuit, the output port 1 is connected with the port TG1 of the power stage transmission circuit, the output port 2 is connected with the port BG1 of the power stage transmission circuit, the output port 3 is connected with the port BG2 of the power stage transmission circuit, and the output port 4 is connected with the port TG2 of the power stage transmission circuit; an input end 1 of the hysteresis mode selection circuit is connected with an input voltage port VIN, an input end (2) of the hysteresis mode selection circuit is connected with an output voltage port VOUT, and an output port of the hysteresis mode selection circuit is respectively connected with an input end of the direct-current offset voltage circuit and an input port of the sequential control logic circuit mode; the positive input port of the pulse modulation circuit is respectively connected with the current sampling circuit, the oscillator, the ramp generator output port ramp and the direct current offset voltage circuit output port, the negative input port is connected with the error amplifier output port, and the output port is connected with the sequential control logic circuit pwm input port; the input end of the direct current offset voltage circuit is connected with the output end of the hysteresis mode selection circuit, and the output end of the direct current offset voltage circuit is connected with the positive input end of the pulse modulation; the output port ramp of the oscillator and the ramp generator is connected with the output port of the current sampling circuit; the positive input port of the current sampling circuit is connected with a port SENS + of the power level transmission circuit, the negative input port of the current sampling circuit is connected with a port SENS-, and the output port of the current sampling circuit is connected with the positive input end of the pulse modulation circuit; a positive input port REF of the error amplifier is connected with a 1V reference voltage, and a negative input port is connected with a port FB of the power level transmission circuit; the input port of the power level transmission circuit is connected with an input voltage port VIN, an output voltage port is connected with an output voltage port VOUT, a SENS + port is connected with a positive input port of a current sampling circuit, a SENS-port is connected with a negative input port of the current sampling circuit, a TG1 port is connected with a time sequence control logic circuit output port 1, a BG1 port is connected with a time sequence control logic circuit output port 2, a BG2 port is connected with a time sequence control logic circuit output port 3, a TG2 port is connected with a time sequence control logic circuit output port 4, and an FB port is connected with a negative input port of an error amplifier.
2. The multi-mode switching low-dynamic-interference 4-transistor synchronous control buck-boost conversion circuit according to claim 1, wherein: the power level transmission circuit comprises a current sampling resistor Rsense, an NMOS transistor K1b, an inductor L, an NMOS transistor K2b, a divider resistor R1, a divider resistor R2, an output capacitor Cout and a load resistor Rout; the current sampling resistor Rsense is bridged between the positive input end SENS + of the current sampling circuit and the negative input end SENS-of the current sampling circuit; the drain electrode of the NMOS transistor K1 is connected with one end of a current sampling resistor Rsense, the source electrode of the NMOS transistor K1 is connected with one end SW1 of an inductor L, and the grid electrode of the NMOS transistor K1 is connected with a sequential control logic output TG 1; the drain electrode of the NMOS transistor K1b is connected with one end SW1 of the inductor L, the source electrode is connected with the ground end, and the grid electrode is connected with the sequential control logic output BG 1; the inductor L is bridged between the source electrode of the NMOS transistor K1 and the drain electrode of the NMOS transistor K2; the drain electrode of the NMOS transistor K2 is connected with the SW2 end of the inductor L, the source electrode of the NMOS transistor K2 is connected with the ground end, and the grid electrode of the NMOS transistor K2 is connected with the sequential control logic output BG 2; the drain electrode of the NMOS transistor K2b is connected with one end of the divider resistor R1, the source electrode is connected with the SW2 end of the inductor L, and the grid electrode is connected with the sequential control logic output TG 2; the voltage dividing resistor R1 is bridged between the drain electrode of the NMOS transistor K2b and the voltage dividing resistor R2; the voltage dividing resistor R2 is bridged between the ground end and the voltage dividing resistor R1; the output capacitor Cout is bridged between the drain electrode of the NMOS transistor K2b and the ground end; one end of the load resistor Rout is connected with the drain electrode of the NMOS transistor K2b, the other end of the load resistor Rout is connected with the ground end, and the output end of the oscillator is connected with the ramp generator and the input port clk of the sequential control logic circuit; the input end of the slope generator is connected with the output end of the oscillator, and the output end of the slope generator is connected to the positive input end of the pulse modulation after being added with the signal of the current sampling output end; the positive input end of the pulse modulation circuit is connected with the output end of the direct-current offset voltage circuit, the negative input end of the pulse modulation circuit is connected with the output end of the error amplifier, and the output end pwm of the pulse modulation circuit is connected with the input port pwm of the sequential control logic circuit; the positive input port of the error amplifier is connected with a 1V reference voltage REF, the negative input port FB is connected with one end of a divider resistor R2, and the output port is connected with the pulse modulation negative input port.
3. The multi-mode switching low-dynamic-interference 4-transistor synchronous control buck-boost conversion circuit according to claim 1, wherein: the direct-current offset voltage circuit comprises a power supply port Vdd, a ground port GND, PMOS transistors M1, M2, M3, M4 and M5, a current source IDC, a boost mode enabling signal en _ boost input port, resistors R1 and R2, a current sampling input signal Vsen and a direct-current output offset signal Vramp; the source electrode of the PMOS transistor M1 is connected with a power supply port Vdd, the grid electrode of the PMOS transistor M1 is connected with the grid electrode of the PMOS transistor M2, and the drain electrode of the PMOS transistor M1 is connected with the source electrode of the PMOS transistor M3; the source electrode of the PMOS transistor M2 is connected with a power supply port Vdd, the grid electrode of the PMOS transistor M2 is connected with the grid electrode of the PMOS transistor M1, and the drain electrode of the PMOS transistor M2 is connected with the source electrode of the PMOS transistor M4; the source electrode of the PMOS transistor M3 is connected with the drain electrode of the M1, the grid electrode of the PMOS transistor M3 is connected with the grid electrode of the M4, and the drain electrode of the PMOS transistor M3 is connected with the current source IDC; the source electrode of the PMOS transistor M4 is connected with the drain electrode of the M2, the grid electrode of the PMOS transistor M4 is connected with the grid electrode of the M3, and the drain electrode of the PMOS transistor M4 is connected with the source electrode of the M5; the source electrode of the PMOS transistor M5 is connected with the drain electrode of the PMOS transistor M4, the grid electrode of the PMOS transistor M5 is connected with the boost mode enabling signal en _ boost input port, and the drain electrode of the PMOS transistor M is connected with the resistor R1; the resistor R1 is bridged between a current sampling input signal Vsen and a direct current output offset signal Vramp; the resistor R2 is connected across the current sample input signal Vsen and the ground port GND.
4. The multi-mode switching low-dynamic-interference 4-transistor synchronous control buck-boost conversion circuit according to claim 1, wherein: the hysteresis mode selection circuit comprises a power supply port Vdd, a ground port GND, a mode selection enabling port SEL _ en, a mode enabling output port en, an input voltage port Vin, an output voltage port Vout, PMOS transistors M1-M3, NMOS transistors M4-M9, resistors R1-R5, current sources IDC1 and IDC2, an inverter INV1, wherein the source electrode of the PMOS transistor M1 is connected with the power supply port Vdd, the grid electrode of the PMOS transistor M1 is connected with the mode selection enabling port SEL _ en, and the drain electrode of the PMOS transistor M is connected with the current source IDC 1; the source electrode of the PMOS transistor M2 is connected with a current source IDC1, the grid electrode of the PMOS transistor M2 is connected with one end of a resistor R4 and one end of a resistor R5, the drain electrode of the PMOS transistor M5 is connected with the drain electrode of the NMOS transistor M4, the other end of the resistor R4 is connected with an input voltage port Vin, and the other end of the resistor R5 is connected with a ground port GND; the source electrode of the PMOS transistor M3 is connected with a current source IDC1, the grid electrode of the PMOS transistor M3 is connected with one end of a resistor R1, the drain electrode of the PMOS transistor M3 is connected with the drain electrode of an NMOS transistor M7, and the other end of the resistor R1 is connected with an output voltage port Vout; the grid electrode of the NMOS transistor M4 is connected with the mode enabling output port en, the drain electrode of the NMOS transistor is connected with one end of the resistor R2 and one end of the resistor R3, the source electrode of the NMOS transistor is connected with the ground port GND, the other end of the resistor R2 is connected with the grid electrode of the M3, and the other end of the resistor R3 is grounded; the grid electrode of the NMOS transistor M5 is connected with the grid electrode of the M7, the drain electrode of the NMOS transistor M2 is connected with the drain electrode of the NMOS transistor M2, and the source electrode of the NMOS transistor M5 is connected with a ground port GND; the grid electrode of the NMOS transistor M6 is connected with a mode selection enabling port SEL _ en, the drain electrode of the NMOS transistor M6 is connected with the grid electrode of the NMOS transistor M5, and the source electrode of the NMOS transistor M is connected with a ground port GND; the grid electrode of the NMOS transistor M7 is connected with the drain electrode of the M6, the drain electrode of the NMOS transistor M8 is connected with the grid electrode of the M8, and the source electrode of the NMOS transistor M7 is connected with a ground port GND; the grid electrode of the NMOS transistor M8 is connected with the drain electrode of the M7, the drain electrode of the NMOS transistor M is connected with the current source IDC2, and the source electrode of the NMOS transistor M is connected with a ground port GND; the grid electrode of the NMOS transistor M9 is connected with a mode selection enabling port SEL _ en, the drain electrode of the NMOS transistor M9 is connected with a current source IDC2, and the source electrode of the NMOS transistor M9 is connected with a ground port GND; the upper end of the current source IDC1 is connected with a power supply port Vdd, and the lower end of the current source IDC1 is connected with a source electrode M2; the upper end of the current source IDC2 is connected with a power supply port Vdd, and the lower end of the current source IDC2 is connected with an M8 source electrode; the input end of the inverter INV1 is connected with the drain electrode of the M8, and the output end is the mode enabling output port en.
5. The multi-mode switching low-dynamic-interference 4-transistor synchronous control buck-boost conversion circuit according to claim 1, wherein: the sequential control logic module comprises an input voltage Vin port, an output voltage Vout port, a Mode selection port SEL _ en, an input clock port clk, a buck Mode output control signal en _ buck, a buck-boost Mode output control signal en _ buck-boost, a boost Mode output control signal en _ boost, a logic error signal error, a first hysteresis Mode selector Mode _ Sel _1, a second hysteresis Mode selector Mode _ Sel _2, a first D trigger, a second D trigger and a second four-wire decoder; the first hysteresis Mode selector Mode _ Sel _1 and the second hysteresis Mode selector Mode _ Sel _2 are connected with an input voltage Vin port, an output voltage Vout port and a Mode selection port Sel _ en; the output port of the first hysteresis Mode selector Mode _ Sel _1 is connected with the input port of the first D flip-flop; the output port of the second hysteresis Mode selector Mode _ Sel _2 is connected with the input port of the second D trigger; the first D trigger and the second D trigger are both connected with an input clock port clk; the output port of the first D trigger is connected with the input port of the two-four-wire decoder; the output port of the second D flip-flop is connected with the input port of the two four-wire decoders, and the two four-wire decoders output a buck mode output control signal en _ buck, a buck-boost mode output control signal en _ buck-boost, a boost mode output control signal en _ boost and a logic error signal error.
6. The multi-mode switching low-dynamic-interference 4-transistor synchronous control buck-boost conversion circuit according to claim 1, wherein: the oscillator module comprises a power supply port Vdd, a ground port GND, a 0.9V reference voltage input port, current sources IDC 1-IDC 3, an NMOS transistor M1, an NMOS transistor M4, an NMOS transistor M5, an NMOS transistor M6, a PMOS transistor M2, a PMOS transistor M3, a capacitor C1, inverters INV1 AND INV2 AND an AND gate AND1; the upper end of the current source IDC1 is connected with a power supply port Vdd, and the lower end of the current source IDC1 is connected with the grid electrode of the PMOS transistor M2; the upper end of the current source IDC2 is connected with a power supply port Vdd, and the lower end of the current source IDC2 is connected with a source electrode of a PMOS transistor M2; the upper end of the current source IDC3 is connected with a power supply port Vdd, and the lower end of the current source IDC is connected with the drain electrode of the NMOS transistor M4; the grid electrode of the NMOS transistor M1 is connected with the output of the inverter INV1, and the drain electrode of the NMOS transistor M1 is connected with the grid electrode of the PMOS transistor M2; the source electrode is connected with a ground port GND; the grid electrode of the NMOS transistor M4 is connected with the drain electrode of the PMOS transistor M3, the drain electrode is connected with the lower end of the current source IDC3, and the source electrode is connected with a ground port GND; the grid electrode of the NMOS transistor M5 is connected with the grid electrode of the NMOS transistor M6, the drain electrode of the NMOS transistor M2 is connected with the drain electrode of the NMOS transistor M2, and the source electrode of the NMOS transistor M is connected with a ground port GND; the grid electrode of the NMOS transistor M6 is connected with the grid electrode of the NMOS transistor M5, the drain electrode of the NMOS transistor M3 is connected with the drain electrode of the NMOS transistor M3, and the source electrode of the NMOS transistor M is connected with a ground port GND; the upper polar plate of the capacitor C1 is connected with the grid of the M2, and the lower polar plate is connected with a ground port GND; the input of the inverter INV1 is connected with the output of the AND gate AND1, AND the output of the inverter INV1 is connected with the grid electrode of the M1; the input of the inverter INV2 is connected with the drain electrode of the M4, AND the output of the inverter INV2 is connected with the input of the AND gate AND1; AND the first input end of the AND gate AND1 is in output connection with the inverter INV2, the second input end of the AND gate AND1 is in output connection with the inverter INV1, AND the output end of the AND gate AND1 is in input connection with the inverter INV1.
7. The multi-mode switching low-dynamic-interference 4-transistor synchronous control buck-boost conversion circuit according to claim 1, wherein: the slope generator comprises a power supply port Vdd, a ground port GND, a clock input port clk, a slope output port Vramp, a current source IDC1, inverters INV1 and INV2, a capacitor C1, a resistor R1, NMOS transistors M1-M4, an NMOS transistor M9 and PMOS transistors M5-M8; the upper end of the current source IDC1 is connected with a power supply port Vdd, and the lower end of the current source IDC1 is connected with a source electrode of an NMOS transistor M1; the input end of the inverter INV1 is connected with the clock input port clk, and the output end of the inverter INV1 is connected with the input end of the inverter INV 2; the input end of the inverter INV2 is connected with the output end of the inverter INV1, and the output end of the inverter INV2 is connected with the grid electrode of the NMOS transistor M2; the upper polar plate of the capacitor C1 is connected with the source electrode of the NMOS transistor M3, and the lower polar plate is connected with a ground port GND; the resistor R1 is bridged between the source electrode of the NMOS transistor M9 and the ground port GND; the grid electrode of the NMOS transistor M1 is connected with the output end of the inverter INV1, the source electrode of the NMOS transistor M1 is connected with the lower end of the current source IDC1, and the drain electrode of the NMOS transistor M1 is connected with the source electrode of the M2; the grid electrode of the NMOS transistor M2 is connected with the output end of the inverter INV2, the source electrode of the NMOS transistor M2 is connected with the drain electrode of the M1, and the drain electrode of the NMOS transistor M2 is connected with the source electrode of the M1; the grid electrode of the NMOS transistor M3 is connected with the drain electrode of the M1, the source electrode of the NMOS transistor M3 is connected with the upper electrode plate of the capacitor C1, and the drain electrode of the NMOS transistor M3 is connected with the drain electrode of the M1; the grid electrode of the NMOS transistor M4 is connected with the grid electrode of the M1, the drain electrode of the NMOS transistor is connected with the upper polar plate of the capacitor C1, and the source electrode of the NMOS transistor is connected with a ground port GND; the grid electrode of the PMOS transistor M5 is connected with the grid electrode of the PMOS transistor M6, the drain electrode of the PMOS transistor M5 is connected with the source electrode of the PMOS transistor M7, and the source electrode of the PMOS transistor M is connected with a power supply port Vdd; the grid electrode of the PMOS transistor M6 is connected with the grid electrode of the M5, the drain electrode of the PMOS transistor M6 is connected with the source electrode of the M8, and the source electrode of the PMOS transistor M6 is connected with a power supply port Vdd; the grid electrode of the PMOS transistor M7 is connected with the grid electrode of the M8, the drain electrode of the PMOS transistor M7 is connected with the drain electrode of the M9, and the source electrode of the PMOS transistor M7 is connected with the drain electrode of the M5; the grid electrode of the PMOS transistor M8 is connected with the grid electrode of the PMOS transistor M7, the drain electrode of the PMOS transistor M8 is connected with the ramp output port Vramp, and the source electrode of the PMOS transistor M8 is connected with the drain electrode of the PMOS transistor M6; and the grid electrode of the NMOS transistor M9 is connected with the grid electrode of the M3, the drain electrode of the NMOS transistor M7 is connected with the drain electrode of the M7, and the source electrode of the NMOS transistor M9 is connected with one end of the resistor R1.
8. The multi-mode switching low-dynamic-interference 4-transistor synchronous control buck-boost conversion circuit according to claim 1, wherein: the pulse modulation circuit comprises a power supply port Vdd, a ground port GND, a pulse modulation positive input end Vp, a pulse modulation negative input end Vn, a pulse modulation output signal PWM port, a current source IDC1, resistors R1 and R2, PMOS transistors M1-M6, PMOS transistors M8-M9, an NMOS transistor M7 and NMOS transistors M10-M12; the grid electrode of the PMOS transistor M1 is connected with the grid electrode of the PMOS transistor M2, the source electrode of the PMOS transistor M1 is connected with a power supply port Vdd, and the drain electrode of the PMOS transistor M1 is connected with a current source IDC 1; the grid electrode of the PMOS transistor M2 is connected with the grid electrode of the PMOS transistor M1, the source electrode of the PMOS transistor M2 is connected with a power supply port Vdd, and the drain electrode of the PMOS transistor M2 is connected with the source electrode of the PMOS transistor M5; the grid electrode of the PMOS transistor M3 is connected with the grid electrode of the M1, the source electrode of the PMOS transistor M3 is connected with a power supply port Vdd, and the drain electrode of the PMOS transistor M3 is connected with the source electrode of the M8; the grid electrode of the PMOS transistor M4 is connected with the grid electrode of the PMOS transistor M1, the source electrode of the PMOS transistor M4 is connected with a power supply port Vdd, the drain electrode of the PMOS transistor M12 is connected with the drain electrode of the PMOS transistor M12 and the input end of an inverter INV, and the output end of the inverter INV is connected with a pulse modulation output signal PWM port; the grid electrode of the PMOS transistor M5 is connected with the pulse modulation positive input end Vp, the source electrode is connected with the drain electrode of the PMOS transistor M2, and the drain electrode is connected with the resistor R1; the grid electrode of the PMOS transistor M6 is connected with the pulse modulation negative input end Vn, the source electrode of the PMOS transistor M6 is connected with the drain electrode of the M2, the drain electrode of the PMOS transistor M2 is connected with one end of the resistor R2, and the other end of the resistor R2 is connected with the grid electrode and the drain electrode of the grid electrode of the NMOS transistor M7; the grid electrode of the PMOS transistor M8 is connected with the drain electrode of the M5, the source electrode of the PMOS transistor M8 is connected with the drain electrode of the M3, and the drain electrode of the PMOS transistor M8 is connected with the drain electrode of the M10; the grid electrode of the PMOS transistor M9 is connected with the drain electrode of the M6, the source electrode of the PMOS transistor M9 is connected with the drain electrode of the M3, and the drain electrode of the PMOS transistor M11 is connected with the drain electrode of the M11; the grid electrode of the NMOS transistor M7 is connected with the R1, the source electrode of the NMOS transistor M7 is connected with the ground port GND, and the drain electrode of the NMOS transistor M7 is connected with the grid electrode of the M7; the grid electrode of the NMOS transistor M10 is connected with the grid electrode of the NMOS transistor M11, the source electrode of the NMOS transistor M10 is connected with a ground port GND, and the drain electrode of the NMOS transistor M8 is connected with the drain electrode of the ground port GND; the grid electrode of the NMOS transistor M11 is connected with the grid electrode of the NMOS transistor M10, the source electrode of the NMOS transistor M11 is connected with a ground port GND, and the drain electrode of the NMOS transistor M11 is connected with the drain electrode of the NMOS transistor M9; and the grid electrode of the NMOS transistor M12 is connected with the drain electrode of the M9, the source electrode of the NMOS transistor M is connected with the ground port GND, and the drain electrode of the NMOS transistor M is connected with the drain electrode of the M4.
9. The multi-mode switching low-dynamic-interference 4-transistor synchronous control buck-boost conversion circuit according to claim 1, wherein: the error amplifier comprises a power supply port Vdd, a ground port GND, an FB feedback voltage input port, a 1V reference voltage input port, an error amplifier output port, a current source IDC1, PMOS transistors M1 and M2 and NMOS transistors M3 and M4; the upper end of the current source IDC1 is connected with a power supply port Vdd, and the lower end of the current source IDC1 is connected with a source electrode of the PMOS transistor M1; the source electrode of the PMOS transistor M1 is connected with the lower end of a current source IDC1, the grid electrode of the PMOS transistor M1 is connected with an FB feedback voltage input end, and the drain electrode of the PMOS transistor M1 is connected with the drain electrode of an NMOS transistor M3; the source electrode of the PMOS transistor M2 is connected with the lower end of the current source IDC1, the grid electrode of the PMOS transistor M2 is connected with the 1V reference voltage input port, and the drain electrode of the PMOS transistor M2 is connected with the drain electrode of the NMOS transistor M4 and the output port of the error amplifier; the source electrode of the NMOS transistor M3 is connected with the ground port GND, the grid electrode of the NMOS transistor M4 is connected with the grid electrode of the NMOS transistor, and the drain electrode of the NMOS transistor M1 is connected with the drain electrode of the PMOS transistor M; and the source electrode of the NMOS transistor M4 is connected with the ground port GND, the grid electrode of the NMOS transistor M3 is connected, and the drain electrode of the NMOS transistor M2 is connected with the drain electrode of the PMOS transistor M2.
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