CN113540046A - Semiconductor package including semiconductor chip and capacitor - Google Patents

Semiconductor package including semiconductor chip and capacitor Download PDF

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Publication number
CN113540046A
CN113540046A CN202110054116.3A CN202110054116A CN113540046A CN 113540046 A CN113540046 A CN 113540046A CN 202110054116 A CN202110054116 A CN 202110054116A CN 113540046 A CN113540046 A CN 113540046A
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China
Prior art keywords
semiconductor chip
semiconductor
package
capacitor
external terminal
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CN202110054116.3A
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Chinese (zh)
Inventor
河大赫
孙京美
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SK Hynix Inc
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SK Hynix Inc
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Publication of CN113540046A publication Critical patent/CN113540046A/en
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    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06575—Auxiliary carrier between devices, the carrier having no electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor package includes a semiconductor chip and a capacitor. A semiconductor package may include a capacitor and a semiconductor chip mounted on a package substrate. The capacitor may be disposed between the package substrate and the first semiconductor chip, and the capacitor may support the first semiconductor chip.

Description

Semiconductor package including semiconductor chip and capacitor
Technical Field
The present disclosure relates generally to semiconductor packaging technology and, more particularly, to a semiconductor package including a semiconductor chip and a capacitor.
Background
Various attempts have been made to integrate multiple semiconductor chips into a single package structure. As a plurality of semiconductor chips are arranged in a semiconductor package, the structure of the semiconductor package becomes more and more complicated. In addition, in order to secure electrical characteristics required for the semiconductor package, the demand for providing passive elements in the semiconductor package is increasing. Due to the complex structure of the semiconductor package, it is increasingly difficult to secure a space for placing a passive element in the semiconductor package.
Disclosure of Invention
In one embodiment, a semiconductor package includes: a package substrate; a first semiconductor chip disposed on the package substrate; and at least one capacitor disposed between the package substrate and the first semiconductor chip, wherein the at least one capacitor supports the first semiconductor chip.
In another embodiment, a semiconductor package includes: a package substrate; at least one capacitor disposed on the package substrate; and a first semiconductor chip disposed only on the at least one capacitor.
Drawings
Fig. 1 is a perspective view illustrating a semiconductor package according to an embodiment.
Fig. 2 is a cross-sectional view illustrating a semiconductor package according to an embodiment.
Fig. 3 is a perspective view illustrating a semiconductor package according to an embodiment.
Figure 4 is a block diagram illustrating an electronic system employing a memory card including a package according to one embodiment.
Fig. 5 is a block diagram illustrating an electronic system including a package according to one embodiment.
Detailed Description
Terms used herein may correspond to words selected in consideration of their functions in the presented embodiments, and the meanings of the terms may be interpreted differently according to the ordinary skill in the art to which the embodiments belong. Terms, if defined in detail, are to be construed according to the definition. Unless defined otherwise, terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, and are not used to indicate a particular order or quantity of elements.
It will also be understood that when an element or layer is referred to as being "on," "over," "under," or "external" to another element or layer, it can be in direct contact with the other element or layer, or intervening elements or layers may be present. Other words used to describe the relationship between elements or layers should be interpreted in a similar manner (e.g., "between … …" and "directly between … …" or "adjacent" and "directly adjacent").
Spatially relative terms, such as "under," "below," "lower," "above," "upper," "top" and "bottom," and the like, may be used to describe one element and/or feature's relationship to another element and/or feature as illustrated, for example, in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and/or operation in addition to the orientation depicted in the figures. For example, when the device in the figures is turned over, elements described as below and/or beneath other elements or features would then be oriented above the other elements or features. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
According to various embodiments, a semiconductor package may include an electronic device such as a semiconductor chip or a semiconductor die. Semiconductor chips or semiconductor dies may be obtained by dividing a semiconductor substrate, such as a wafer, into a plurality of pieces using a die sawing process. The semiconductor chip may correspond to a memory chip, a logic chip, an Application Specific Integrated Circuit (ASIC) chip, an Application Processor (AP), a Graphics Processing Unit (GPU), a Central Processing Unit (CPU), or a system on a chip (SoC). The memory chip may include a Dynamic Random Access Memory (DRAM) circuit, a Static Random Access Memory (SRAM) circuit, a NAND-type flash memory circuit, a NOR-type flash memory circuit, a Magnetic Random Access Memory (MRAM) circuit, a resistive random access memory (ReRAM) circuit, a ferroelectric random access memory (FeRAM) circuit, or a phase change random access memory (PcRAM) circuit integrated on a semiconductor substrate. The logic chip may include logic circuitry integrated on a semiconductor substrate. The semiconductor package may be used in a communication system, such as a mobile phone, an electronic system associated with biotechnology or healthcare, or a wearable electronic system. The semiconductor package may be applied to the internet of things (IOT).
Like reference numerals refer to like elements throughout the specification. Even though a reference numeral may not be mentioned or described with reference to one figure, it may be mentioned or described with reference to another figure. Further, even if a reference numeral is not shown in one drawing, it may be shown in another drawing.
Fig. 1 is a perspective view schematically illustrating a semiconductor package 10 according to an embodiment.
Referring to fig. 1, a semiconductor package 10 may include a package substrate 100, a first semiconductor chip 200, and a capacitor 300. At least one capacitor 300 may be disposed between the package substrate 100 and the first semiconductor chip 200. The plurality of capacitors 300 may be disposed on the first surface 101 of the package substrate 100 while being spaced apart from each other. Since the first semiconductor chip 200 is provided on the capacitor 300, a structure in which the capacitor 300 supports the first semiconductor chip 200 can be configured. The capacitor 300 may serve as a support for supporting the first semiconductor chip 200. The capacitor 300 may be disposed in a state of overlapping with the first semiconductor chip 200. Since the capacitor 300 overlaps the first semiconductor chip 200, an area required to dispose the capacitor 300 on the package substrate 100 can be reduced. The area of the package substrate 100 occupied by the capacitor 300 and the first semiconductor chip 200 can be reduced as compared with the case where the capacitor and the first semiconductor chip are arranged side by side without overlapping each other.
Fig. 2 is a cross-sectional view schematically illustrating a semiconductor package 10 according to an embodiment. Fig. 2 schematically illustrates a cross-sectional shape of the semiconductor package 10 along line X1-X2 of fig. 1.
Referring to fig. 1 and 2, the capacitor 300 may be introduced in the form of a multilayer ceramic capacitor (MLCC). The capacitor 300 may include a capacitor body 310, a first external terminal 320, and a second external terminal 330. The capacitor body 310 may include an internal electrode 312 provided as a plurality of layers in a dielectric layer 311. The dielectric layer 311 may be formed by laminating a plurality of sub-dielectric layers. The internal electrodes 312 may be interleaved between the sub-dielectric layers and alternate with each other.
The first and second external terminals 320 and 330 may be disposed at both ends of the capacitor body 310, respectively. The first external terminal 320 may include a first layer 321 and a second layer 322 having different metal materials. The first layer 321 of the first external terminal 320 may be connected to some of the internal electrodes 312, and may be electrically coupled to some of the internal electrodes 312. The first layer 321 of the first external terminal 320 may include a metal layer, for example, a copper (Cu) layer. The second layer 322 of the first external terminal 320 may be provided as a metal layer covering the first layer 321 of the first external terminal. The second layer 322 of the first external terminal 320 may include a nickel (Ni) layer that prevents contamination or oxidation of a copper (Cu) layer. The second layer 322 of the first external terminal 320 may further include a gold (Au) layer covering the nickel (Ni) layer. The gold (Au) layer may be a bonding layer bonding or coupling the first external terminal 320 to other elements.
The package substrate 100 may include a conductive placing finger (finger) 110 on the first surface 101. The conductive placement finger 110 may refer to a portion of the circuit wiring structure disposed in the package substrate 100. The first external terminal 320 of the capacitor 300 may be coupled or bonded to the conductive placement finger 110 by a conductive adhesive layer 350. The conductive adhesive layer 350 may be introduced as a solder layer containing solder.
The first external terminal 320 may be coupled to the package substrate 100 such that the capacitor 300 may be electrically coupled to the package substrate 100. The second external terminal 330 of the capacitor 300 may be located at an end opposite to the first external terminal 320 with the capacitor body 310 interposed between the second external terminal 330 and the first external terminal 320. The capacitor 300 may be mounted on the package substrate 100 in such a manner that the first external terminal 320, the capacitor body 310, and the second external terminal 330 are sequentially stacked in a direction substantially perpendicular to the first surface 101 of the package substrate 100. The capacitor 300 may be mounted on the package substrate 100 substantially perpendicular to the first surface 101 of the package substrate 100.
The second external terminal 330 may include a first layer 331 and a second layer 332 having different metal materials. The second external terminal 330 may have substantially the same layer structure as the first external terminal 320. The first layer 331 of the second external terminal 330 may be connected to the remaining internal electrodes 312, and may be electrically coupled to the remaining internal electrodes 312. The first layer 331 of the second external terminal 330 may include a metal layer, for example, a copper (Cu) layer. The second layer 332 of the external terminal 330 may be provided as a metal layer covering the first layer 331 of the second external terminal 330. The second layer 332 of the second external terminal 330 may include a composite layer of a nickel (Ni) layer and a gold (Au) layer.
Referring to fig. 2, the first semiconductor chip 200 may be supported by at least one capacitor 300. A portion 330-1 of the second external terminal 330 of the capacitor 300 may overlap the first semiconductor chip 200 so that the capacitor 300 may support the first semiconductor chip 200. A portion of the first semiconductor chip 200 may be coupled or bonded to the overlapping portion 330-1 of the second external terminal 330 by the insulating adhesive layer 230. The insulating adhesive layer 230 may be used to fix the first semiconductor chip 200 to the capacitor 300.
Another portion 330-2 of the second external terminal 330 may not be shielded by the first semiconductor chip 200 and may be exposed to the outside of the first semiconductor chip 200. The package substrate 100 may include first bonding fingers 130 located below the first surface 101. The first bonding wire 410 may be wire bonded such that one end of the first bonding wire 410 is bonded to the exposed portion 330-2 of the second external terminal 330 and the other end of the first bonding wire 410 may be bonded to the first bonding finger 130. The first bonding wires 410 may electrically connect the second external terminals 330 to the package substrate 100. The second layer 332 of the second external terminal 330 may include a gold (Au) layer as a surface layer. When the first bonding wire 410 is a gold (Au) wire, the first bonding wire 410 may be easily bonded and coupled to the gold (Au) layer of the second external terminal 330.
The first semiconductor chip 200 may include a first chip pad 201 and a second chip pad 202, the second chip pad 202 being disposed to be spaced apart from the first chip pad 201. The first chip pad 201 and the second chip pad 202 may be connection terminals that apply electrical signals to the first semiconductor chip 200.
The second bonding wires 420 may be wire bonded to connect the exposed portions 330-2 of the second external terminals 330 to the first chip pads 201 of the first semiconductor chip 200. The second bonding wire 420 may electrically connect the second external terminal 330 of the capacitor 300 to the first semiconductor chip 200. The first and second bonding wires 410 and 420 may electrically connect the first semiconductor chip 200 to the first bonding fingers 130 of the package substrate 100.
The ground terminal 131 may be disposed under the second surface 102 opposite to the first surface 101 of the package substrate 100. The package substrate 100 may include a first inner wiring 132 connecting the first bonding finger 130 to the ground terminal 131. When the first bonding finger 130 is connected to the ground terminal 131, the first bonding wire 410 and the second bonding wire 420 may provide an electrical path to ground the first semiconductor chip 200. In this case, the second external terminal 330, which is one terminal of the capacitor 300, may be connected to an electrical path configured to ground the semiconductor chip 200.
The third bonding wires 430 may be wire bonded to directly connect the second chip pads 202 of the first semiconductor chip 200 to the second bonding fingers 150 of the package substrate 100. The third bonding wire 430 may provide an electrical path to supply power to the first semiconductor chip 200 when the second bonding finger 150 is connected to the power terminal 135.
The power supply terminals 135 may be disposed below the second surface 102 of the package substrate 100. The second inner wiring 133 connecting the second bonding finger 150 to the power terminal 135 may be disposed in the package substrate 100. Second engagement finger 150 may be disposed spaced apart from first engagement finger 130 and conductive placement finger 110. A third internal wiring 134 may be provided in the package substrate 100 to electrically connect the conductive placing finger 110 to the second bonding finger 150.
The first external terminal 320, which is the other terminal of the capacitor 300, may be electrically connected to the power supply terminal 135 through the conductive placement finger 110, the third internal wiring 134, and the second internal wiring 133 connected to the first external terminal 320. In one embodiment, the third internal wiring 134 may be electrically connected to the power supply terminal 135. In addition, the capacitor 300 may be electrically connected to the first semiconductor chip 200 through the first external terminal 320, the conductive placement finger 110, the third internal wiring 134, the second bonding finger 150, and the third bonding wire 430. Accordingly, the first external terminal 320, which is the other terminal of the capacitor 300, may be connected to another electrical path that supplies power to the first semiconductor chip 200.
In this way, since the capacitor 300 is electrically connected between an electrical path that grounds the first semiconductor chip 200 and another electrical path that supplies power to the semiconductor chip 200, the capacitor 300 may function as a decoupling capacitor (decoupling capacitor) that reduces noise during operation of the first semiconductor chip 200. In one embodiment, the third bonding wire 430 may form an electrical path that grounds the first semiconductor chip 200, and the first bonding wire 410 and the second bonding wire 420 may form an electrical path that supplies power to the first semiconductor chip 200. In this case, the capacitor 300 may also be electrically connected between an electrical path that grounds the first semiconductor chip 200 and an electrical path that supplies power to the first semiconductor chip 200.
Since the capacitor 300 can be mounted at a position where the capacitor 300 overlaps the first semiconductor chip 200, an area of the package substrate 100 where the capacitor 300 is mounted can be secured. Accordingly, a greater number of capacitors 300 may be mounted on the package substrate 100, and the noise reduction effect may be further increased due to the decoupling effect from the large number of capacitors 300. Therefore, the electrical characteristics of the semiconductor package 10 can be improved.
Fig. 3 is a perspective view schematically illustrating a semiconductor package 20 according to an embodiment. In fig. 3, the same reference numerals as in fig. 1 and 2 may be understood to denote the same components.
Referring to fig. 3, the semiconductor package 20 may include a capacitor 300, a first semiconductor chip 200, a stacked structure 500 of second semiconductor chips 501, 502, and 503, and a third semiconductor chip 600. The stacked structure 500 of the second semiconductor chips 501, 502, and 503 may be disposed on the package substrate 100 to be spaced apart from the capacitor 300. The second semiconductor chip 502 of the second stage and the second semiconductor chip 503 of the third stage may be sequentially and vertically stacked on the second semiconductor chip 501 of the first stage. The second semiconductor chips 501, 502, and 503 of the first, second, and third stages may be stacked at positions offset from each other by a predetermined distance. The second semiconductor chips 501, 502, and 503 of the first, second, and third stages may be vertically stacked in the stair-shaped stacked structure 500.
The first semiconductor chip 200 may be supported by the capacitor 300 to have a height equal to that of the stacked structure 500 of the second semiconductor chip. The third semiconductor chip 600 may be further stacked on the stacked structure 500 of the first semiconductor chip 200 and the second semiconductor chip. The third semiconductor chip 600 may be commonly supported by the stacked structure 500 of the first semiconductor chip 200 and the second semiconductor chip. The second semiconductor chips 501, 502, and 503 may be electrically connected to the package substrate 100 through bonding wires (not shown). The third semiconductor chip 600 may be electrically connected to the package substrate 100 through other bonding wires (not shown).
The third semiconductor chip 600 may have a larger size than the first semiconductor chip 200 or the second semiconductor chips 501, 502, and 503. When the third semiconductor chip 600 is larger than the second semiconductor chips 501, 502, and 503, a portion 601 of the third semiconductor chip 600 may protrude from a side surface of the stacked structure 500 of the second semiconductor chips 501, 502, and 503 to be in a cantilever shape (overhung). The stacked structure of the capacitor 300 and the first semiconductor chip 200 may support the cantilever portion 601 of the third semiconductor chip 600. Therefore, it may not be necessary to introduce an additional support to support the cantilever portion 601 of the third semiconductor chip 600.
The second semiconductor chips 501, 502, and 503 constituting the stacked structure 500 may include DRAM memory chips. The third semiconductor chip 600 may include a NAND memory chip. The first semiconductor chip 200 may include a controller that controls the second semiconductor chips 501, 502, and 503 and the third semiconductor chip 600.
Although not shown, a sealing material may be provided to cover the package substrate 100 and to cover and protect the capacitor 300, the first semiconductor chip 200, the stacked structure 500 of the second semiconductor chips 501, 502, and 503, and the third semiconductor chip 600.
According to an embodiment of the present disclosure, a semiconductor package structure may be provided in which a capacitor is provided to support a semiconductor chip. The capacitor may be provided in a state of overlapping with the semiconductor chip. With this arrangement, a space for providing the passive element in the semiconductor package can be secured. Therefore, space utilization in the semiconductor package can be improved.
Fig. 4 is a block diagram illustrating an electronic system including a memory card 7800 employing at least one semiconductor package according to an embodiment. The memory card 7800 may include a memory 7810 (e.g., a non-volatile memory device) and a memory controller 7820. The memory 7810 and the memory controller 7820 may store data or read stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one semiconductor package according to an embodiment.
Memory 7810 may include non-volatile memory devices to which the techniques of embodiments of the present disclosure may be applied. The memory controller 7820 may control the memory 7810 to store data or read stored data in response to a read/write request from the host 7830.
Fig. 5 is a block diagram illustrating an electronic system 8710 including at least one semiconductor package according to an embodiment. The electronic system 8710 may include a controller 8711, an input/output device 8712, and a memory 8713. The controller 8711, the input/output device 8712, and the memory 8713 may be coupled to each other by a bus 8715 that provides a data movement path.
In one embodiment, the controller 8711 can include one or more microprocessors, digital signal processors, microcontrollers, and/or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include at least one semiconductor package according to an embodiment of the present disclosure. The input/output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, and the like. The memory 8713 is a device for storing data. The memory 8713 can store data and/or commands to be executed by the controller 8711, and the like.
The memory 8713 may include volatile memory devices such as DRAM and/or non-volatile memory devices such as flash memory. For example, the flash memory may be mounted to an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a Solid State Disk (SSD). In this case, the electronic system 8710 can stably store a large amount of data in the flash memory system.
Electronic system 8710 can also include an interface 8714 configured to send and receive data to and from a communication network. The interface 8714 may be a wired type or a wireless type. For example, interface 8714 may include an antenna, or a wired or wireless transceiver.
The electronic system 8710 may be a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system may be any one of a Personal Digital Assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission/reception system.
If electronic system 8710 is a device capable of performing wireless communication, electronic system 8710 may be used in a communication system by using a technology of Code Division Multiple Access (CDMA), global system for mobile communication (GSM), North American Digital Cellular (NADC), enhanced time division multiple access (E-TDMA), Wideband Code Division Multiple Access (WCDMA), CDMA2000, Long Term Evolution (LTE), or wireless broadband internet (Wibro).
The inventive concept has been disclosed in connection with some embodiments as described above. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure. Accordingly, the embodiments disclosed in this specification should not be considered limiting, but rather illustrative. The scope of the inventive concept is not limited by the above description but is defined by the appended claims, and all different features that come within the meaning and range of equivalents should be construed as being included in the inventive concept.
Cross Reference to Related Applications
This application claims priority to korean application No.10-2020-0046328, filed on 16/4/2020, which is hereby incorporated by reference in its entirety.

Claims (15)

1. A semiconductor package, comprising:
a package substrate;
a first semiconductor chip disposed on the package substrate; and
at least one capacitor disposed between the package substrate and the first semiconductor chip, wherein the at least one capacitor supports the first semiconductor chip.
2. The semiconductor package of claim 1, wherein the capacitor comprises:
a capacitor body; and
first and second external terminals provided at both ends of the capacitor main body, respectively,
wherein the first external terminal is coupled to the package substrate, and wherein the second external terminal supports the first semiconductor chip.
3. The semiconductor package of claim 2, wherein the second external terminal comprises a nickel layer and a gold layer.
4. The semiconductor package of claim 2, further comprising an insulating adhesive layer bonding the first semiconductor chip to the second external terminal.
5. The semiconductor package of claim 2, wherein a portion of the second external terminal is exposed and uncovered by the first semiconductor chip,
the semiconductor package also includes a first bonding wire electrically connecting the portion of the second external terminal to the package substrate.
6. The semiconductor package of claim 5, further comprising a second bond wire connecting the portion of the second external terminal to the first semiconductor chip.
7. The semiconductor package of claim 6, wherein the first and second bond wires provide electrical paths connecting the first semiconductor chip to the package substrate.
8. The semiconductor package of claim 6, wherein the package substrate includes a conductive placement finger, the first external terminal being bonded to the conductive placement finger by a conductive adhesive layer.
9. The semiconductor package of claim 8, wherein the conductive adhesive layer comprises a solder layer.
10. The semiconductor package of claim 8, wherein the package substrate further comprises bond fingers electrically connected to the conductive placement fingers by internal routing, and
wherein the semiconductor package further comprises a third bond wire connecting the first semiconductor chip to the bond finger.
11. The semiconductor package of claim 10, wherein the third bond wire provides an electrical path that supplies power to the first semiconductor chip, and
wherein the first and second bonding wires ground the first semiconductor chip.
12. The semiconductor package of claim 10, wherein the third bond wire grounds the first semiconductor chip, and
wherein the first bond wire and the second bond wire provide an electrical path to power the first semiconductor chip.
13. The semiconductor package of claim 1, further comprising:
a stacked structure including a second semiconductor chip and disposed on the package substrate to be spaced apart from the capacitor; and
a third semiconductor chip commonly supported by the stacked structure of the second semiconductor chip and the first semiconductor chip.
14. The semiconductor package of claim 1, wherein the capacitor comprises a multilayer ceramic capacitor.
15. A semiconductor package, comprising:
a package substrate;
at least one capacitor disposed on the package substrate; and
a first semiconductor chip disposed only on the at least one capacitor.
CN202110054116.3A 2020-04-16 2021-01-15 Semiconductor package including semiconductor chip and capacitor Pending CN113540046A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2020-0046328 2020-04-16
KR1020200046328A KR20210128295A (en) 2020-04-16 2020-04-16 Semiconductor packages including capacitors with semiconductor chips

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CN113540046A true CN113540046A (en) 2021-10-22

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US (1) US11450627B2 (en)
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