CN113539868B - 封装芯片电学性能的测试方法 - Google Patents

封装芯片电学性能的测试方法 Download PDF

Info

Publication number
CN113539868B
CN113539868B CN202010306983.7A CN202010306983A CN113539868B CN 113539868 B CN113539868 B CN 113539868B CN 202010306983 A CN202010306983 A CN 202010306983A CN 113539868 B CN113539868 B CN 113539868B
Authority
CN
China
Prior art keywords
wafer
metal layer
top metal
particles
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010306983.7A
Other languages
English (en)
Other versions
CN113539868A (zh
Inventor
梅萌
史刚
王培春
李广峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Montage Technology Kunshan Co Ltd
Original Assignee
Montage Technology Kunshan Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Montage Technology Kunshan Co Ltd filed Critical Montage Technology Kunshan Co Ltd
Priority to CN202010306983.7A priority Critical patent/CN113539868B/zh
Priority to PCT/CN2020/090699 priority patent/WO2021208177A1/zh
Priority to US17/272,766 priority patent/US11393732B2/en
Publication of CN113539868A publication Critical patent/CN113539868A/zh
Application granted granted Critical
Publication of CN113539868B publication Critical patent/CN113539868B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2611—Measuring inductance
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2894—Aspects of quality control [QC]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2898—Sample preparation, e.g. removing encapsulation, etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
    • H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

本申请公开了一种封装芯片电学性能测试结构的制作方法、封装芯片电学性能的测试方法，包括：提供第一晶圆和第二晶圆；分别在所述第一晶圆和所述第二晶圆上形成顶层金属层；分别在所述第一晶圆和所述第二晶圆的部分所述顶层金属层上形成凸块；去除所述第一晶圆中位于所述凸块下方之外的顶层金属层，完全保留所述第二晶圆中的顶层金属层；分别封装所述第一晶圆和所述第二晶圆形成第一颗粒和第二颗粒，将所述第二颗粒设置于基板上，所述凸块与所述基板连接，所述基板相对于所述第二颗粒的另一侧设置有用于测试的导电结构；采用探针与所述导电结构接触，测试所述第二颗粒的电学性能，所述第二颗粒的电学性能作为所述第一颗粒电学性能的参考。

Description

封装芯片电学性能的测试方法
技术领域
本发明一般涉及封装芯片测试技术领域，特别涉及一种封装芯片电学性能测试结构的制作方法、封装芯片电学性能的测试方法。
背景技术
半导体集成电路芯片指内含集成电路的硅片，体积很小，常常是计算机或其他电子设备的一部分。芯片封装是将半导体集成电路芯片用绝缘材料进行打包，封装芯片的引脚通过印刷电路板与其他器件建立连接。为了保证出厂的芯片的可靠性，需要在出厂前对封装芯片进行测试以确保功能完整性等。
目前测量封装芯片电学性能的方法是在封装芯片的凸块(bump)区域添加大量的焊料(solder)进行短接，将封装芯片与电路板连接，电路板的另一侧设置测试用的导电结构，然后，用探针与导电结构接触并通过矢量网络分析仪测量封装芯片的电学性能。该测试方法中，由于封装芯片与电路板连接的区域上覆盖有绿油，使得焊料短接的效果差，导致电学性能测试结果存在偏差。
发明内容
本发明的目的在于提供一种封装芯片电学性能的测试方法，增强凸块的短接效果，从而增强凸块与探针的接触性能，提高测试的可靠性。
本申请的一实施例中公开了一种封装芯片电学性能测试结构的制作方法，包括：
提供第一晶圆和第二晶圆；
分别在所述第一晶圆和所述第二晶圆上形成顶层金属层；
分别在所述第一晶圆和所述第二晶圆的部分所述顶层金属层上形成凸块；
去除所述第一晶圆中位于所述凸块下方之外的顶层金属层，完全保留所述第二晶圆中的顶层金属层；
分别封装所述第一晶圆和所述第二晶圆形成第一颗粒和第二颗粒，所述第二颗粒作为测试结构，所述第二颗粒的电学性能作为所述第一颗粒电学性能的参考。
在一优选例中，在部分所述顶层金属层上形成凸块的步骤，进一步包括：
在所述顶层金属层上沉积图案化的光阻，所述图案化的光阻暴露出部分的顶层金属层；
采用电镀沉积工艺在所述暴露的部分顶层金属层上生长所述凸块；
去除所述图案化的光阻。
在一优选例中，所述凸块包括铜、镍、锡、银中的一种或其任意组合。
在一优选例中，采用溅射工艺生长所述顶层金属层，所述顶层金属层包括铜、金、银、镍、锡中的一种或其任意组合。
在一优选例中，所述第一晶圆内包括有晶体管、互连结构和控制电路。
在一优选例中，分别封装所述第一晶圆和所述第二晶圆形成第一颗粒和第二颗粒的步骤，进一步包括：采用相同的封装工艺封装所述第一晶圆和所述第二晶圆。
本申请的另一实施例还公开了一种封装芯片电学性能的测试方法，采用前文所述的制作方法制作的测试结构，包括：
将所述测试结构设置于基板上，所述测试结构的凸块与所述基板连接，所述基板相对于所述测试结构的另一侧设置有用于测试的导电结构；
采用探针与所述导电结构接触，测试所述测试结构的电学性能。
在一优选例中，所述电学性能包括电阻性能和电感性能。
在一优选例中，所述基板为印刷电路板、柔性电路板、陶瓷基板或有机基板。
在一优选例中，所述导电结构包括锡球。
相对于现有技术，本申请至少具有以下有益效果：
本申请中，采用第二颗粒作为测试结构，第二颗粒表面具有完整的顶层金属层，顶层金属层与凸块的连接性能更好，使得测试过程中短接良好，从而提高测试的可靠性。
此外，本申请的第二颗粒与作为产品的第一颗粒(具有控制电路等)采用相同的金属层工艺和封装工艺，没有额外增加工艺，成本较低。
附图说明
参考以下附图描述本申请的非限制性和非穷举性实施例，其中除非另有说明，否则相同的附图标记在各个附图中指代相同的部分。
图1示出了本申请一实施例中封装芯片电学性能测试结构的制作方法的流程图。
图2示出了本申请一实施例中第一晶圆和第二晶圆的示意图。
图3示出了本申请一实施例中形成聚酰亚胺层和顶层金属层的示意图。
图4示出了本申请一实施例中形成图案化的光阻和凸块的示意图。
图5示出了本申请一实施例中去除图案化的光阻和顶层金属层的示意图。
图6示出了本申请一实施例中凸块进行回流焊工艺的示意图。
图7示出了本申请一实施例中封装芯片电学性能的测试方法的流程图。
图8示出了本申请一实施例中电学性能测试过程的示意图。
具体实施方式
现在将描述本申请的各个方面和示例。以下描述提供了用于彻底理解和实现这些示例的描述的具体细节。然而，本领域技术人员将理解，可以在没有许多这些细节的情况下实践本申请。
另外，可能未详细示出或描述一些众所周知的结构或功能，以便简明扼要并避免不必要地模糊相关描述。
在下面给出的描述中使用的术语旨在以其最广泛的合理方式解释，即使它与本申请的某些特定示例的详细描述一起使用。以下甚至可以强调某些术语，然而，任何旨在以任何受限制的方式解释的术语将在本详细描述部分中明确且具体地定义。
本申请的第一实施例中公开了一种封装芯片电学性能测试结构的制作方法，图1示出了测试结构的制作方法的流程图，图2至图6示出了各步骤对应的结构示意图。该方法包括：
步骤S101，提供第一晶圆(wafer)100和第二晶圆200，参考图2所示，所述晶圆指的是可以在其中形成器件的衬底，例如，硅衬底、锗硅衬底、砷化镓衬底等等，所述器件可以指的是CMOS电路，例如包括一个或多个晶体管、互连结构和控制电路等等，用于实现特定功能的结构。所述晶圆中还可以形成有其他器件结构，例如放大器、数/模转换器、模拟处理电路和/或数字处理电路、接口电路等，形成这些器件结构的方法均可以为CMOS工艺。其中，所述第一晶圆100用于形成正常的芯片产品，即在第一晶圆100中形成器件，所述第二晶圆200用于测试，即在第二晶圆200中不形成器件，仅形成需要实现测试的金属层和凸块，根据第二晶圆的测试结果衡量芯片产品的电学性能。所述第一晶圆100和所述第二晶圆200中分别形成焊盘112,212以及钝化层114,214，所述钝化层114,214分别部分覆盖所述焊盘112,212，所述钝化层114,214为氮化硅(SiN)。
在一实施例中，参考图3所示，分别在所述衬底110,210上形成聚酰亚胺(polyimide)层116,216，所述聚酰亚胺层116,216分别用于释放下方衬底110,210的应力。应当理解，所述聚酰亚胺层116,216是可选的，在其他实施例中，也可以不形成聚酰亚胺层116,216。
步骤S103，继续参考图3所示，分别在所述第一晶圆100和第二晶圆200上形成顶层金属层118,218。本领域技术人员应当公知的是，在芯片工艺制程中，需要形成多层金属层，例如，3至5层金属层，以实现电连接。本实施例中，所述顶层金属层指的是工艺制程中的最上层金属层或凸块下方的金属层(Under bump metellization)。在一实施例中，采用溅射(sputtering)工艺形成所述顶层金属层。所述顶层金属层118,218可包括铜(Cu)、钛(Ti)、金(Au)、银(Ag)、镍(Ni)、锡(Sn)中的一种或其任意组合，例如，溅射铜或钛形成所述顶层金属层。所述顶层金属层118,218的厚度可以为300nm～600nm，例如300nm、400nm、600nm等。
步骤S105，参考图4所示，分别在部分所述顶层金属层118,218上形成凸块(bump)122,222。在一实施例中，步骤S105中，在在部分所述顶层金属层上形成凸块的步骤，进一步包括：
参考图4所示，分别在所述顶层金属层118,218上沉积图案化的光阻(PR)120,220，所述图案化的光阻120,220暴露出部分所述顶层金属层118,218，同时暴露出所述焊盘112,212。应当理解，图案化的光阻可以采用本领域已知或未来可知的工艺形成，在此不做赘述。
之后，采用电镀沉积(ECD)工艺分别在所述图案化的光阻未覆盖的所述顶层金属层118,218上生长凸块122,222。在一实施例中，所述凸块122,222可包括铜、镍、锡、银中的一种或其任意组合。所述凸块122,222的厚度可以为38μm～95μm，例如，40μm、50μm、60μm、65μm、78μm、86μm、90μm等。例如，凸块122,222包括依次层叠的第一金属层1220,2220、第二金属层1222,2222和第三金属层1224,2224，所述第一金属层1220,2220为铜金属层。所述第二金属层1222,2222为镍金属层。所述第三金属层1224,2224为锡银焊料层。
在另一实施例中，所述凸块122,222包括两层金属层，例如，第一金属层和第二金属层，所述第一金属层为镍金属层，所述第二金属层为焊料层，例如，不含铅焊料层(LFsolder)。
接着，参考图5所示，去除所述图案化的光阻120,220，例如，采用等离子体蚀刻工艺或灰化工艺去除所述光阻120,220。
步骤S107，继续参考图5所示，去除所述第一晶圆100中位于所述凸块122下方之外的顶层金属层118，完全保留所述第二晶圆200中的顶层金属层218。本实施例中，去除所述第一晶圆100中位于所述凸块122下方之外的顶层金属层118，第一晶圆100中未去除的顶层金属层118用于实现互连，第二晶圆200中的顶层金属层218不需要实现互连，仅用于电学性能测试，因而不需要去除。本实施例中，可以采用湿法蚀刻工艺去除所述顶层金属层。
本实施例中，由于第二晶圆中的顶层金属层是未经蚀刻的金属层，因此第二晶圆中的顶层金属层的表面平整，该顶层金属层与凸块之间的接触性能良好。
参考图6所示，在一实施例中，所述制作方法还包括对所述凸块122,222进行回流焊(reflow)工艺。
步骤S109，分别封装所述第一晶圆100和所述第二晶圆200形成第一颗粒(die)和第二颗粒，所述第二颗粒作为测试结构，所述第二颗粒的电学性能作为所述第一颗粒电学性能的参考。在一实施例中，在步骤S109中，分别封装所述第一晶圆和所述第二晶圆形成第一颗粒和第二颗粒的步骤，进一步包括：采用相同的封装工艺封装所述第一晶圆和所述第二晶圆。本实施例中，可以采用本领域技术人员公知的技术对晶圆进行封装，在此不做赘述。本实施例中，第二颗粒的结构参考图8中200’所示，第二颗粒200’包括衬底210’、位于所述衬底210’上的顶层金属层218’以及与顶层金属层连接的凸块222’。本实施例中，第二颗粒与作为芯片产品的第一颗粒(具有控制电路等)采用相同的金属层工艺和封装工艺，没有额外增加工艺，实现测试的成本较低。
本申请的第二实施例还公开了一种封装芯片电学性能的测试方法，图7示出了封装芯片电学性能的测试方法的流程图，步骤S201至S209与前文所述的S101至S109相似，该方法包括：
步骤S201，提供第一晶圆和第二晶圆；
步骤S203，分别在所述第一晶圆和所述第二晶圆上形成顶层金属层；
步骤S205，分别在所述第一晶圆和所述第二晶圆的部分所述顶层金属层上形成凸块；
步骤S207，去除所述第一晶圆中位于所述凸块下方之外的顶层金属层，完全保留所述第二晶圆中的顶层金属层；
步骤S209，分别封装所述第一晶圆和所述第二晶圆形成第一颗粒和第二颗粒；
步骤S211，将所述第二颗粒设置于基板上，所述凸块与所述基板连接，所述基板相对于所述第二颗粒的另一侧设置有用于测试的导电结构。在一实施例中，所述基板为印刷电路板(PCB)、柔性电路板(FPC)或有机基板，所述基板上设置有用于电气连接的焊盘(PAD)，所述凸块与所述基板的焊盘连接。在一实施例中，采用封装胶连接所述测试结构与所述基板，用于补强颗粒与基板之间的连接。在一实施例中，所述导电结构为锡球。
步骤S213，采用探针与所述导电结构310接触，测试所述第二颗粒200’的电学性能，所述第二颗粒200’的电学性能作为所述第一颗粒电学性能的参考。在一实施例中，所述电学性能包括电阻性能和电感性能。
图8示出了一实施例中电学性能测试过程的示意图。第二颗粒200’倒置与基板300上，凸块222’与基板300上的焊盘(图中未示出)电气连接，凸块222’与基板300之间设置有封装胶(图中未示出)，基板300相对于所述第二颗粒200’的另一侧设置有锡球310。测试电学性能时，采用两个探针(图中箭头所示)分别与锡球310接触，其中一个探针的一端接地端(G)，另一个探针的一端接信号端(S)，采用矢量网络分析仪分别测试颗粒的电阻值和电感值，矢量网络分析仪采用本领域技术人员公知的方法测试电阻值和电感值，在此不做赘述。下表1中给出了本申请与现有的测试方法测量的电阻值(R)与电感值(H)的结果，下表1中仅以信号DAC1为例进行列举，分别测试了不同的6个样品，当然本领域技术人员可以测试QACA13等其他的信号。从下表1中可以看出，本申请的测试方法对于电阻值测试的改善非常明显，电阻值的标准差由38.5667降低到0.0568，同时对于电感值的测试也有一定程度的改善。
表1电学性能的测试结果
需要说明的是，在本专利的申请文件中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。本专利的申请文件中，如果提到根据某要素执行某行为，则是指至少根据该要素执行该行为的意思，其中包括了两种情况：仅根据该要素执行该行为、和根据该要素和其它要素执行该行为。多个、多次、多种等表达包括2个、2次、2种以及2个以上、2次以上、2种以上。
在本说明书提及的所有文献都被认为是整体性地包括在本申请的公开内容中，以便在必要时可以作为修改的依据。此外应理解，以上所述仅为本说明书的较佳实施例而已，并非用于限定本说明书的保护范围。凡在本说明书一个或多个实施例的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本说明书一个或多个实施例的保护范围之内。
在一些情况下，在权利要求书中记载的动作或步骤可以按照不同于实施例中的顺序来执行并且仍然可以实现期望的结果。另外，在附图中描绘的过程不一定要求示出的特定顺序或者连续顺序才能实现期望的结果。在某些实施方式中，多任务处理和并行处理也是可以的或者可能是有利的。

Claims (10)

1.一种封装芯片电学性能测试结构的制作方法，其特征在于，包括：
提供第一晶圆和第二晶圆；
分别在所述第一晶圆和所述第二晶圆上形成顶层金属层；
分别在所述第一晶圆和所述第二晶圆的部分所述顶层金属层上形成凸块；
去除所述第一晶圆中位于所述凸块下方之外的顶层金属层，完全保留所述第二晶圆中的顶层金属层；
分别封装所述第一晶圆和所述第二晶圆形成第一颗粒和第二颗粒，所述第二颗粒作为测试结构，所述第二颗粒的电学性能作为所述第一颗粒电学性能的参考。
2.如权利要求1所述的测试结构的制作方法，其特征在于，在部分所述顶层金属层上形成凸块的步骤，进一步包括：
在所述顶层金属层上沉积图案化的光阻，所述图案化的光阻暴露出部分的顶层金属层；
采用电镀沉积工艺在所述暴露的部分顶层金属层上生长所述凸块；
去除所述图案化的光阻。
3.如权利要求2所述的测试结构的制作方法，其特征在于，所述凸块包括铜、镍、锡、银中的一种或其任意组合。
4.如权利要求1所述的测试结构的制作方法，其特征在于，采用溅射工艺生长所述顶层金属层，所述顶层金属层包括铜、钛、金、银、镍、锡中的一种或其任意组合。
5.如权利要求1所述的测试结构的制作方法，其特征在于，所述第一晶圆内包括有晶体管、互连结构和控制电路。
6.如权利要求1所述的测试结构的制作方法，其特征在于，分别封装所述第一晶圆和所述第二晶圆形成第一颗粒和第二颗粒的步骤，进一步包括：采用相同的封装工艺封装所述第一晶圆和所述第二晶圆。
7.一种封装芯片电学性能的测试方法，其特征在于，采用如权利要求1-6中任意一项所述的制作方法制作的测试结构，包括：
将所述测试结构设置于基板上，所述测试结构的凸块与所述基板连接，所述基板相对于所述测试结构的另一侧设置有用于测试的导电结构；
采用探针与所述导电结构接触，测试所述测试结构的电学性能。
8.如权利要求7所述的封装芯片电学性能的测试方法，其特征在于，所述电学性能包括电阻性能和电感性能。
9.如权利要求7所述的封装芯片电学性能的测试方法，其特征在于，所述基板为印刷电路板、柔性电路板、陶瓷基板或有机基板。
10.如权利要求7所述的封装芯片电学性能的测试方法，其特征在于，所述导电结构包括锡球。
CN202010306983.7A 2020-04-17 2020-04-17 封装芯片电学性能的测试方法 Active CN113539868B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN202010306983.7A CN113539868B (zh) 2020-04-17 2020-04-17 封装芯片电学性能的测试方法
PCT/CN2020/090699 WO2021208177A1 (zh) 2020-04-17 2020-05-15 封装芯片电学性能的测试方法
US17/272,766 US11393732B2 (en) 2020-04-17 2020-05-15 Method for testing electrical performance of packaged chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010306983.7A CN113539868B (zh) 2020-04-17 2020-04-17 封装芯片电学性能的测试方法

Publications (2)

Publication Number Publication Date
CN113539868A CN113539868A (zh) 2021-10-22
CN113539868B true CN113539868B (zh) 2023-07-18

Family

ID=78083500

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010306983.7A Active CN113539868B (zh) 2020-04-17 2020-04-17 封装芯片电学性能的测试方法

Country Status (3)

Country Link
US (1) US11393732B2 (zh)
CN (1) CN113539868B (zh)
WO (1) WO2021208177A1 (zh)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170017510A (ko) * 2015-08-07 2017-02-15 주식회사 에스에프에이반도체 저항 측정용 재배선층을 갖는 웨이퍼 레벨 패키지 및 상기 저항 측정용 재배선층을 이용하여 상기 웨이퍼 레벨 패키지의 전기적 특성을 테스트하는 방법
CN110494964A (zh) * 2017-04-07 2019-11-22 微芯片技术股份有限公司 具有暴露的重新分布层特征的半导体封装件以及相关的封装和测试方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1198326C (zh) * 2003-01-07 2005-04-20 威盛电子股份有限公司 适用于集成电路芯片的信号检测方法
TWI355061B (en) * 2007-12-06 2011-12-21 Nanya Technology Corp Stacked-type chip package structure and fabricatio
US8558229B2 (en) * 2011-12-07 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Passivation layer for packaged chip
US10120826B2 (en) * 2013-07-02 2018-11-06 Inphi Corporation Single-chip control module for an integrated system-on-a-chip for silicon photonics
CN103824789A (zh) * 2013-11-26 2014-05-28 上海华力微电子有限公司 一种晶圆电性测试方法
CN104051337B (zh) * 2014-04-24 2017-02-15 上海珏芯光电科技有限公司 立体堆叠集成电路***芯片封装的制造方法与测试方法
US9735071B2 (en) * 2015-08-25 2017-08-15 International Business Machines Corporation Method of forming a temporary test structure for device fabrication
US10461000B2 (en) * 2016-08-08 2019-10-29 Semiconductor Components Industries, Llc Semiconductor wafer and method of probe testing
US10529671B2 (en) * 2016-12-13 2020-01-07 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10741537B2 (en) * 2017-01-18 2020-08-11 Taiwan Semiconductor Manufacturing Coompany Ltd. Semiconductor structure and manufacturing method thereof
JP2018166171A (ja) * 2017-03-28 2018-10-25 ルネサスエレクトロニクス株式会社 半導体装置の製造方法、半導体装置および半導体装置の検査装置
US10276457B2 (en) * 2017-03-29 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method for measuring charge accumulation in fabrication process of semiconductor device and method for fabricating semiconductor device
CN109979842A (zh) * 2019-03-29 2019-07-05 上海华力集成电路制造有限公司 芯片失效测试结构、包括其的芯片及应用其的测试方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170017510A (ko) * 2015-08-07 2017-02-15 주식회사 에스에프에이반도체 저항 측정용 재배선층을 갖는 웨이퍼 레벨 패키지 및 상기 저항 측정용 재배선층을 이용하여 상기 웨이퍼 레벨 패키지의 전기적 특성을 테스트하는 방법
CN110494964A (zh) * 2017-04-07 2019-11-22 微芯片技术股份有限公司 具有暴露的重新分布层特征的半导体封装件以及相关的封装和测试方法

Also Published As

Publication number Publication date
US11393732B2 (en) 2022-07-19
WO2021208177A1 (zh) 2021-10-21
US20220148932A1 (en) 2022-05-12
CN113539868A (zh) 2021-10-22

Similar Documents

Publication Publication Date Title
US8384222B2 (en) Semiconductor device and manufacturing method thereof
US6407459B2 (en) Chip scale package
US8124490B2 (en) Semiconductor device and method of forming passive devices
US9142500B2 (en) Apparatus for lead free solder interconnections for integrated circuits
US6075712A (en) Flip-chip having electrical contact pads on the backside of the chip
KR100605315B1 (ko) 집적회로 칩의 입출력 패드 구조
US20070023919A1 (en) Bonding pad on ic substrate and method for making the same
US20050248011A1 (en) Flip chip semiconductor package for testing bump and method of fabricating the same
KR100887475B1 (ko) 반도체 패키지 및 그 제조방법
US20070184577A1 (en) Method of fabricating wafer level package
US7648902B2 (en) Manufacturing method of redistribution circuit structure
US10651099B2 (en) Non-destructive testing of integrated circuit chips
US20080075841A1 (en) Apparatus and method incorporating discrete passive components in an electronic package
US20060231927A1 (en) Semiconductor chip mounting body and manufacturing method thereof
US20090014897A1 (en) Semiconductor chip package and method of manufacturing the same
JP4446793B2 (ja) 半導体装置およびその製造方法
CN108269730B (zh) 半导体器件及其制备方法
CN113539868B (zh) 封装芯片电学性能的测试方法
US7615864B2 (en) Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus
US20030189249A1 (en) Chip structure and wire bonding process suited for the same
CN113140521B (zh) 晶圆级封装方法以及晶圆级封装结构
US7129581B2 (en) Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus
US20040201109A1 (en) Semiconductor devices, manufacturing methods therefore, circuit substrates and electronic devices
US20200091020A1 (en) Pad structures in semiconductor devices
TWI498980B (zh) 半導體晶圓以及形成用於在晶圓分類測試期間的晶圓探測的犧牲凸塊墊之方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant