CN113539817A - Etching method - Google Patents

Etching method Download PDF

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Publication number
CN113539817A
CN113539817A CN202010296746.7A CN202010296746A CN113539817A CN 113539817 A CN113539817 A CN 113539817A CN 202010296746 A CN202010296746 A CN 202010296746A CN 113539817 A CN113539817 A CN 113539817A
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Prior art keywords
layer
mask
etching
gate region
sacrificial layer
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Chinese (zh)
Inventor
张显
刘金营
平延磊
吴莊莊
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SiEn Qingdao Integrated Circuits Co Ltd
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SiEn Qingdao Integrated Circuits Co Ltd
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Priority to CN202010296746.7A priority Critical patent/CN113539817A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

The invention provides an etching method, which can form a sacrificial layer on a gate region by a selective growth method or a barrier deposition method so as to compensate the height difference between the gate region and an active region by the sacrificial layer when a gate region groove and an active region groove are formed by etching, thereby avoiding the damage of the gate region caused by over-etching of the gate region and the problem of electric connection caused by insufficient etching of the active region.

Description

Etching method
Technical Field
The invention belongs to the field of semiconductor manufacturing, and relates to an etching method.
Background
The transistor is used as a variable current switch, can control output current based on input voltage, is different from a common mechanical switch, controls opening and closing of the transistor by utilizing an electric signal, has very high switching speed and is often applied to computers, mobile phones and intelligent household equipment.
The transistor comprises a Gate (Gate), a Source (Source) and a Drain (Drain), wherein in the formation process of the contact electrode arranged on a Gate region and an active region (Source or Drain), the height of the contact electrode arranged on the active region is larger than that of the contact electrode arranged on the Gate region due to the height difference between the Gate region and the active region, so that when the contact electrode is prepared, trenches with different etching depths are required to be formed in a dielectric layer (ILD). However, when trenches with different etching depths are formed by etching, there are often problems in that the trenches located above the gate region are over-etched, which results in damage to the gate region, or the trenches located above the active region are insufficiently etched, which results in electrical connection.
Therefore, it is necessary to provide an etching method to form a trench with a good etching depth.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an etching method for solving the problems of over-etching of a gate region and insufficient etching of an active region caused by a height difference between the gate region and the active region when forming a contact electrode of a transistor in the prior art.
To achieve the above and other related objects, the present invention provides an etching method, comprising:
providing a transistor, wherein the transistor comprises a gate region and an active region, and a height difference larger than zero is formed between the gate region and the active region;
forming a dielectric layer on the transistor;
forming a patterned first mask on the dielectric layer to form a first mask gate region opening in the first mask;
forming a sacrificial layer in the opening of the first mask gate region, wherein the projection of the sacrificial layer on the vertical direction covers the gate region;
removing the first mask;
forming a patterned second mask to form a second mask gate region opening and a second mask active region opening in the second mask, wherein the sacrificial layer is exposed from the second mask gate region opening;
etching the dielectric layer through the second mask active region opening to form an active region groove exposing the active region; and etching the sacrificial layer and the dielectric layer through the opening of the second mask gate region to form a gate region groove exposing the gate region.
Optionally, the method of forming the sacrificial layer includes a selective growth method or a barrier deposition method.
Optionally, a material of the first mask includes PPFAA, and a material of the sacrificial layer includes silicon oxide.
Optionally, an etching rate of the sacrificial layer is equal to an etching rate of the dielectric layer, and a thickness of the sacrificial layer is equal to the height difference.
Optionally, an etching rate of the dielectric layer is greater than an etching rate of the sacrificial layer.
Optionally, the step of forming the active region trench and the gate region trench includes:
etching the dielectric layer through the opening of the second mask active region to form a dielectric layer groove, wherein the depth of the dielectric layer groove is equal to the height difference;
removing the sacrificial layer by wet etching;
and etching the dielectric layer to form the active region groove and the gate region groove.
Optionally, the material of the sacrificial layer includes one of silicon oxide, silicon nitride, zinc oxide, and hafnium oxide.
Optionally, the dielectric layer includes one or a combination of a silicon oxide layer, a BPSG layer, a PSG layer, and a TEOS layer.
Optionally, after removing the first mask, the method further includes annealing the sacrificial layer, where the annealing method includes a laser annealing method, and the annealing temperature range includes 200 ℃ to 400 ℃.
Optionally, the second mask comprises an amorphous carbon layer, and the step of forming the patterned second mask comprises:
forming an amorphous carbon layer on the sacrificial layer and the dielectric layer;
forming an anti-reflection layer on the amorphous carbon layer;
forming a patterned photoresist on the anti-reflection layer;
and etching to form the patterned second mask.
As described above, according to the etching method of the present invention, the sacrificial layer may be formed on the gate region by the selective growth method or the barrier deposition method, so that when the gate region trench and the active region trench are formed by etching, the height difference between the gate region and the active region is compensated by the sacrificial layer, thereby avoiding the problems of damage to the gate region due to over-etching of the gate region and electrical connection due to insufficient etching of the active region.
Drawings
Fig. 1 is a process flow diagram of the etching method of the present invention.
Fig. 2 to 10 are schematic structural diagrams showing steps of the etching method according to the first embodiment.
Fig. 11 to 17 are schematic structural diagrams showing steps of the etching method according to the second embodiment.
Description of the element reference numerals
100. 110 transistor
200. 210 dielectric layer
201. 211 gate region trench
202. 212 active region trench
213 dielectric layer trench
300. 310 first mask
301 first mask gate region opening
400. 410 sacrificial layer
500. 510 second mask
501. 511 second mask gate region opening
502. 512 second mask active area opening
601. 611 dielectric antireflection layer
602. 612 bottom antireflective layer
700. 710 Photoresist
A gate region
B1 source region
B2 drain region
D. Height difference of D1
d thickness of sacrificial layer
d1 depth of dielectric layer trench
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structures are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Referring to fig. 1, the present invention provides an etching method, which can form a sacrificial layer on a gate region by a selective growth method or a barrier deposition method, so that when a gate region trench and an active region trench are formed by etching, a height difference between the gate region and the active region is compensated by the sacrificial layer, thereby preventing the gate region from being damaged due to over-etching of the gate region and the problem of electrical connection due to insufficient etching of the active region.
In particular, reference may be made to the following first and second embodiments.
Example one
Referring to fig. 2 to 10, in the present embodiment, a sacrificial layer is formed on a gate region by a selective growth method, so that when a gate region trench and an active region trench are formed by etching, a height difference between the gate region and the active region is compensated by the sacrificial layer, thereby avoiding a problem of electrical connection caused by over-etching of the gate region and insufficient etching of the active region.
First, referring to fig. 2, a transistor 100 is provided, the transistor 100 including a gate region a and an active region (including a source region B1 and a drain region B2), and the gate region a and the active region having a height difference D therebetween greater than zero. The transistor 100 may include a gate oxide layer, a protective passivation layer (e.g., a silicon nitride layer) covering the gate region a and the active region, a sidewall covering the sidewall of the transistor 100, and an ohmic contact layer on the surfaces of the gate region a and the active region, and the structure, the type, the material, and the like of the transistor 100 may be selected according to the requirement, which is not limited herein.
Next, referring to fig. 3, a dielectric layer 200 is formed on the transistor 100.
As an example, the dielectric layer 200 may include one or a combination of a silicon oxide layer, a BPSG (boron phosphorus doped silicon oxide) layer, a PSG (phosphorus doped silicon oxide) layer, and a TEOS (tetraethylorthosilicate) layer.
Specifically, the dielectric layer 200 may be selected according to the requirement of the line width and the material of the sacrificial layer 400 in the subsequent process, for example, when the line width is large, the dielectric layer 200 may be a BPSG layer, when the line width is small, a TEOS layer may be used, or a PSG layer may be used, but the invention is not limited thereto, and for example, the dielectric layer 200 may also be a silicon oxide layer or a combination of at least two of a silicon oxide layer, a BPSG layer, a PSG layer, and a TEOS layer, and may be appropriately selected according to the requirement.
Next, referring to fig. 4, a patterned first mask 300 is formed over the dielectric layer 200 to form a first mask gate region opening 301 in the first mask 300.
Specifically, a photolithography method may be adopted to form the first mask gate region opening 301 in the formed first mask 300, wherein a projection of the first mask gate region opening 301 in the vertical direction covers the gate region a, so that a projection formed in the vertical direction subsequently covers the sacrificial layer 400 of the gate region a, thereby avoiding over-etching of the gate region a.
Next, referring to fig. 5, the sacrificial layer 400 is formed in the first mask gate region opening 301, and the projection of the sacrificial layer 400 in the vertical direction covers the gate region a.
As an example, the material of the first mask 300 includes PPFAA (polyperfluoroalkylpropylene), and the material of the sacrificial layer 400 includes silicon oxide.
Specifically, because PPFAA has a lower surface energy than silicon oxide, if silicon oxide is to be formed on the PPFAA surface, the activation energy required is much greater than the activation energy required to form silicon oxide on silicon oxide or a material containing silicon oxide, and thus, under the same conditions, when PPFAA is used as the first mask 300 and a material containing silicon oxide is used as the dielectric layer 200, the sacrificial layer 400 can be formed in the first mask gate region opening 301 by the selective growth method.
As an example, the etching rate of the sacrificial layer 400 is equal to the etching rate of the dielectric layer 200, and the thickness D of the sacrificial layer 400 is equal to the height difference D.
Specifically, when the etching rate of the sacrificial layer 400 is equal to the etching rate of the dielectric layer 200, the thickness D of the sacrificial layer 400 is equal to the height difference D, so that the height difference D is compensated by the sacrificial layer 400, thereby avoiding over-etching the gate region a and insufficient etching of the active region.
Next, referring to fig. 6, the first mask 300 is removed.
Next, referring to fig. 7 to 9, the patterned second mask 500 is patterned to form a second mask gate region opening 501 and a second mask active region opening 502 in the second mask 500, and the second mask gate region opening 501 exposes the sacrificial layer 400.
Illustratively, after removing the first mask 300, the method further includes annealing the sacrificial layer 400, wherein the annealing method includes a laser annealing method, and the annealing temperature range includes 200 ℃ to 400 ℃.
Specifically, in order to form the sacrificial layer 400 with a good lattice structure to optimize the performance of the formed sacrificial layer 400, the present embodiment performs an annealing process on the sacrificial layer 400 after removing the first mask 300, wherein a laser annealing process with a low temperature and a low cost is preferred, and the temperature of the annealing process may be selected to be, for example, 300 ℃, so as to further reduce the cost, and the selection of the method and the temperature related to the annealing process is not limited thereto.
As an example, the second mask 500 includes an amorphous carbon layer, and the step of forming the patterned second mask 500 includes:
forming an amorphous carbon layer on the sacrificial layer 400 and the dielectric layer 200;
forming an anti-reflection layer on the amorphous carbon layer;
forming a patterned photoresist 700 on the anti-reflection layer;
the second mask 500 is etched to form a pattern.
Specifically, in this embodiment, the second mask 500 adopts an amorphous carbon layer to transfer the pattern, so as to be used as a barrier layer for forming the trench subsequently; the anti-reflective layer includes a dielectric anti-reflective layer 601 and a bottom anti-reflective layer 602, so as to play a role of anti-reflection during the exposure process of patterning the photoresist 700, thereby optimizing the exposure effect. The choice of materials for the second mask 500, the anti-reflective layer and the photoresist 700 is not limited herein. The patterned photoresist 700, the dielectric anti-reflective layer 601 and the bottom anti-reflective layer 602 may be removed during the etching process to form the patterned second mask 500, or may be removed by an ashing method, etc., which is not limited herein.
Next, referring to fig. 10, the dielectric layer 200 is etched through the second mask active region opening 502 to form an active region trench 202 exposing the active region; and etching the sacrificial layer 400 and the dielectric layer 200 through the second mask gate region opening 501 to form a gate region groove 201 exposing the gate region A.
Specifically, in this embodiment, since the etching rate of the sacrificial layer 400 is equal to the etching rate of the dielectric layer 200, and the thickness D of the sacrificial layer 400 is equal to the height difference D, when the dielectric layer 200 is etched to form the active region trench 202 and the gate region trench 201, the active region trench 202 and the gate region trench 201 can be formed in the dielectric layer 200 by one-time etching, and the problems of over-etching of the gate region a and insufficient etching of the active region can be avoided.
Example two
Referring to fig. 11 to 17, the difference between the first embodiment and the second embodiment is mainly as follows: and forming a sacrificial layer on the gate region by a barrier deposition method, so that when the gate region groove and the active region groove are formed by etching, the height difference between the gate region and the active region is compensated by the sacrificial layer, thereby avoiding the problems of gate region damage caused by over-etching of the gate region and electric connection caused by insufficient etching of the active region.
First, referring to fig. 11, a transistor 110 is provided, and a dielectric layer 210, a patterned first mask 310 and a sacrificial layer 410 are formed on the transistor 110.
Specifically, the structure and material of the transistor 110 and the structure and material of the dielectric layer 210 are not described herein. The thickness of the dielectric layer 210 above the gate region is preferably greater than the height difference D between the gate region and the active region, so as to facilitate the subsequent process operation. The first mask 310 may use a photoresist, the photoresist may be patterned through a photolithography step, and the sacrificial layer 410 may be formed by depositing and removing the photoresist, see fig. 12.
As an example, the material of the sacrificial layer 410 includes one of silicon nitride, zinc oxide, and hafnium oxide.
As an example, the etch rate of the dielectric layer 210 is greater than the etch rate of the sacrificial layer 410.
Specifically, the sacrificial layer 410 and the dielectric layer 210 have different selection time ratios, the sacrificial layer 410 can be used as a barrier layer, when the etching rate of the dielectric layer 210 is greater than that of the sacrificial layer 410, the step-by-step etching of the dielectric layer 210 can be realized through the barrier of the sacrificial layer 410, so that the height difference D is compensated through the first etching step of the dielectric layer 210, and the problems of over-etching of a gate region and insufficient etching of an active region can be avoided through the last etching step. The material of the dielectric layer 210 may be selected according to the material of the dielectric layer 210, and is not limited herein.
As an example, the step of forming the active region trench 212 and the gate region trench 211 includes:
etching the dielectric layer 210 through the second mask active region opening 512 to form a dielectric layer trench 213, wherein a depth D1 of the dielectric layer trench 213 is equal to the height difference D1, as shown in fig. 14 and 15;
removing the sacrificial layer 410 by wet etching, referring to fig. 16;
the dielectric layer 210 is etched to form the active region trench 512 and the gate region trench 511, see fig. 17.
Specifically, referring to fig. 13, forming the second mask active area opening 512 may include forming a second mask 510 on the sacrificial layer 410 and the dielectric layer 210, wherein the second mask 510 may include an amorphous carbon layer to transfer a pattern as a barrier layer for forming the active area trench 512 and the gate area trench 511; the anti-reflective layer includes a dielectric anti-reflective layer 611 and a bottom anti-reflective layer 612, so as to play a role of anti-reflection during the exposure process of the patterned photoresist 710, thereby optimizing the exposure effect. The choice of materials for the second mask 510, the anti-reflective layer and the photoresist 710 is not limited herein. The patterned photoresist 710, the dielectric anti-reflective layer 611 and the bottom anti-reflective layer 612 can be removed during the etching process to form the patterned second mask 510, or can be removed by an ashing method, etc., without being limited thereto.
In this embodiment, the step etching of the dielectric layer 210 is realized by the blocking of the sacrificial layer 410, so that the height difference D is compensated for by the gate region trench 213 formed by the first etching of the dielectric layer 210, and the active region trench 512 and the gate region trench 511 can be prepared and formed by the second etching of the dielectric layer 210, thereby avoiding the problems of over-etching of the gate region and insufficient etching of the active region.
In another embodiment, the sacrificial layer may also be a silicon oxide layer, that is, a material having the same etching rate as the dielectric layer may be used, and the sacrificial layer is formed by using a patterned photoresist as a shielding layer, which may specifically refer to fig. 11 to 12 in embodiment two, but different from embodiment two, the step of forming the trench in the dielectric layer may be completed by one-time etching, which may specifically refer to fig. 6 to 10 in embodiment one, and is not described herein again.
In summary, according to the etching method of the present invention, the sacrificial layer may be formed on the gate region by using a selective growth method or a barrier deposition method, so that when the gate region trench and the active region trench are formed by etching, the height difference between the gate region and the active region is compensated by the sacrificial layer, thereby avoiding the problems of gate region damage caused by over-etching of the gate region and electrical connection caused by insufficient etching of the active region.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (10)

1. An etching method is characterized by comprising the following steps:
providing a transistor, wherein the transistor comprises a gate region and an active region, and a height difference larger than zero is formed between the gate region and the active region;
forming a dielectric layer on the transistor;
forming a patterned first mask on the dielectric layer to form a first mask gate region opening in the first mask;
forming a sacrificial layer in the opening of the first mask gate region, wherein the projection of the sacrificial layer on the vertical direction covers the gate region;
removing the first mask;
forming a patterned second mask to form a second mask gate region opening and a second mask active region opening in the second mask, wherein the sacrificial layer is exposed from the second mask gate region opening;
etching the dielectric layer through the second mask active region opening to form an active region groove exposing the active region; and etching the sacrificial layer and the dielectric layer through the opening of the second mask gate region to form a gate region groove exposing the gate region.
2. The etching method according to claim 1, characterized in that: methods of forming the sacrificial layer include a selective growth method or a barrier deposition method.
3. The etching method according to claim 1, characterized in that: the material of the first mask comprises PPFAA, and the material of the sacrificial layer comprises silicon oxide.
4. The etching method according to claim 1, characterized in that: the etching rate of the sacrificial layer is equal to that of the dielectric layer, and the thickness of the sacrificial layer is equal to the height difference.
5. The etching method according to claim 1, characterized in that: the etching rate of the dielectric layer is greater than that of the sacrificial layer.
6. The etching method of claim 5, wherein the step of forming the active region trench and the gate region trench comprises:
etching the dielectric layer through the opening of the second mask active region to form a dielectric layer groove, wherein the depth of the dielectric layer groove is equal to the height difference;
removing the sacrificial layer by wet etching;
and etching the dielectric layer to form the active region groove and the gate region groove.
7. The etching method according to claim 1, characterized in that: the sacrificial layer is made of one of silicon oxide, silicon nitride, zinc oxide and hafnium oxide.
8. The etching method according to claim 1, characterized in that: the dielectric layer includes one or a combination of a silicon oxide layer, a BPSG layer, a PSG layer, and a TEOS layer.
9. The etching method according to claim 1, characterized in that: after the first mask is removed, the method further comprises the step of annealing the sacrificial layer, wherein the annealing method comprises a laser annealing method, and the annealing temperature range comprises 200-400 ℃.
10. The etching method of claim 1, wherein the second mask comprises an amorphous carbon layer, and the step of forming the patterned second mask comprises:
forming an amorphous carbon layer on the sacrificial layer and the dielectric layer;
forming an anti-reflection layer on the amorphous carbon layer;
forming a patterned photoresist on the anti-reflection layer;
and etching to form the patterned second mask.
CN202010296746.7A 2020-04-15 2020-04-15 Etching method Pending CN113539817A (en)

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Citations (5)

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Publication number Priority date Publication date Assignee Title
US20070218685A1 (en) * 2006-03-17 2007-09-20 Swaminathan Sivakumar Method of forming trench contacts for MOS transistors
US20080076244A1 (en) * 2006-09-26 2008-03-27 Chartered Semiconductor Manufacturing, Ltd. Damascene Contact Structure for Integrated Circuits
CN101312151A (en) * 2007-05-22 2008-11-26 中芯国际集成电路制造(上海)有限公司 Metal interlayer medium contact hole preparation method
CN109192699A (en) * 2018-09-07 2019-01-11 德淮半导体有限公司 Method for manufacturing semiconductor device
CN110556298A (en) * 2019-08-26 2019-12-10 上海新微技术研发中心有限公司 Method for manufacturing field effect transistor

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070218685A1 (en) * 2006-03-17 2007-09-20 Swaminathan Sivakumar Method of forming trench contacts for MOS transistors
CN101379596A (en) * 2006-03-17 2009-03-04 英特尔公司 Method of forming trench contacts for MOS transistors
US20080076244A1 (en) * 2006-09-26 2008-03-27 Chartered Semiconductor Manufacturing, Ltd. Damascene Contact Structure for Integrated Circuits
CN101312151A (en) * 2007-05-22 2008-11-26 中芯国际集成电路制造(上海)有限公司 Metal interlayer medium contact hole preparation method
CN109192699A (en) * 2018-09-07 2019-01-11 德淮半导体有限公司 Method for manufacturing semiconductor device
CN110556298A (en) * 2019-08-26 2019-12-10 上海新微技术研发中心有限公司 Method for manufacturing field effect transistor

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