CN113517813A - Fixed frequency dual-mode synchronous voltage reduction controller - Google Patents
Fixed frequency dual-mode synchronous voltage reduction controller Download PDFInfo
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- CN113517813A CN113517813A CN202110528103.5A CN202110528103A CN113517813A CN 113517813 A CN113517813 A CN 113517813A CN 202110528103 A CN202110528103 A CN 202110528103A CN 113517813 A CN113517813 A CN 113517813A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Dc-Dc Converters (AREA)
Abstract
A fixed frequency dual-mode synchronous voltage reduction controller relates to the integrated circuit technology, and the invention comprises: a conduction time circuit, the output end of which is connected to the first input end of the digital logic circuit; a comparator, the output end of which is connected to the second input end of the digital logic circuit; the digital logic circuit is provided with two output ends and is used for controlling the level states of the two output ends according to the level of the first input end and controlling the level states of the two output ends according to the level of the second input end; the positive input end of the switch selection circuit and the transconductance amplifier is connected with the second reference voltage end, and the negative input end of the switch selection circuit and the transconductance amplifier is connected with the feedback voltage end. The invention makes the conversion frequency be a fixed value, avoids the conversion frequency of the traditional hysteresis control mode from being influenced by other parameters such as ESR, inductance L and the like, further effectively reduces EMI interference, and can effectively improve the reliability and stability of equipment in the system.
Description
Technical Field
The present invention relates to integrated circuit technology.
Background
The synchronous buck controller with the fixed-switching-frequency dual-control mode function belongs to a very important component in power management application, and is mainly applied to various environments such as set-top boxes, notebook computers, mobile power supply systems, power supplies of linear voltage regulators and the like. The device has the advantages of small volume, low cost, convenient application, strong dry interference resistance and the like, thereby being widely applied.
In a portable application environment, the operating frequency of a mobile communication device may reach the range of hundreds of KHz to tens of MHz. In this wide bandwidth, noise affects the stability of the normal operation of the electronic device, and the communication quality of the communication device is degraded. This requires a fixed switching frequency for the DC-DC converter, which reduces EMI interference and improves the stability and anti-interference capability of the product equipment through the peripheral filter devices on the PCB.
Fig. 1 is a schematic diagram of a conventional hysteretic control mode DC-DC buck converter. In the conventional hysteretic control mode DC-DC converter, the conversion frequency equation is as follows.
The conversion frequency can be obtained from the formula according to the input voltage, the output voltage, the ESR value, the inductance L value and the series resistance feedback point voltage ripple amplitude value VHYSDelay time tdAnd the like. Therefore, in a practical application environment, the switching frequency generated by the DC-DC converter of the conventional hysteretic control mode is not a fixed value, but is randomly generated within a certain frequency range. This can cause EMI interference signals to other components in the PCB board, which ultimately affects the reliability and stability of the system.
Therefore, in order to avoid the above problems, it is necessary to redesign and optimize the DC-DC converter based on the conventional hysteretic control mode from the whole circuit structure, design a COT control mode having a fast transient response characteristic and a fixed switching frequency and a current control mode having a high-precision output voltage and a fixed switching frequency, and implement a dual control mode function in which one chip can implement both the COT control mode and the current control mode.
Disclosure of Invention
The technical problem to be solved by the invention is to redesign the whole circuit structure on the basis of the traditional hysteresis control mode to make the conversion frequency be a fixed value so as to reduce EMI interference and solve the problem that the conversion frequency of the traditional hysteresis control mode is dependent on the input voltage, the output voltage, the ESR value, the inductance L value and the series resistance feedback point voltage ripple amplitude value VHYSDelay time tdAnd the like, and various factors are changed.
The invention solves the technical problem by adopting the technical scheme that the fixed frequency dual-mode synchronous buck controller is characterized by comprising the following parts:
a conduction time circuit, the output end of which is connected to the first input end of the digital logic circuit;
a comparator, the output end of which is connected to the second input end of the digital logic circuit;
the digital logic circuit is provided with two output ends and is used for controlling the level states of the two output ends according to the level of the first input end and controlling the level states of the two output ends according to the level of the second input end;
the zero input end of the switch selection circuit is connected with the output end of the transconductance amplifier, the first input end of the switch selection circuit is connected with the feedback voltage end, the second input end of the switch selection circuit is connected with the first reference voltage end, the third input end of the switch selection circuit is connected with the CS end, the fourth input end of the switch selection circuit is connected with the PGND end, the fifth input end of the switch selection circuit is connected with the second reference voltage end, the first output end of the switch selection circuit is connected with the first negative input end of the comparator, the second output end of the switch selection circuit is connected with the first positive input end of the comparator, the third output end of the switch selection circuit is connected with the second positive input end of the comparator, and the fourth output end of the switch selection circuit is connected with the second negative input end of the comparator and used for realizing the selection of output signals according to the signal of the zero input end;
and the positive input end of the transconductance amplifier is connected with the second reference voltage end, and the negative input end of the transconductance amplifier is connected with the feedback voltage end.
The on-time circuit includes:
a switched Voltage (VDDQ) detection circuit composed of resistors connected in series,
the SW port voltage detection circuit comprises a twenty-first NMOS tube and a twenty-eighth NMOS tube, wherein the source electrode of the twenty-first NMOS tube is connected with the drain electrode of the twenty-eighth NMOS tube and a twenty-fifth resistor, the twenty-fifth resistor is grounded through a capacitor, the drain electrode of the twenty-eighth NMOS tube is grounded, and the source electrode of the twenty-first NMOS tube is used as an output end;
a twenty-first PMOS tube, wherein the source electrode of the twenty-first PMOS tube is connected with the VCC end, the drain electrode of the twenty-first PMOS tube is grounded through a twenty-first triode, and the grid electrode of the twenty-first PMOS tube is connected with the first bias signal end;
a twenty-first triode, the base of which is connected with the output end of the switching voltage detection circuit;
a source electrode of the twenty-second PMOS tube is connected with the VCC end, and a grid electrode and a drain electrode of the twenty-fifth NMOS tube are connected with a drain electrode of the twenty-fifth NMOS tube;
a twenty-fifth NMOS transistor, a gate connected to the second bias signal terminal, a source connected to the drain of the twenty-second NMOS transistor,
a twenty-second NMOS transistor, a grid electrode is connected with the drain electrode of the twenty-first PMOS transistor, a source electrode is connected with the drain electrode of the twenty-seventh NMOS transistor, a source electrode of the twenty-seventh NMOS transistor is grounded,
a twenty-third PMOS tube with a gate connected to the gate of the twenty-second PMOS tube, a source connected to the VCC end, a drain connected to the drain of the twenty-fourth NMOS tube,
a twenty-fourth NMOS transistor, a grid electrode of which is connected with the second bias signal end, and a source electrode of which is connected with a drain electrode of the twenty-third NMOS transistor;
a source electrode of the twenty-third NMOS tube is connected with a drain electrode of the twenty-seventh NMOS tube;
the grid electrode of the twenty-seventh NMOS tube is connected with a third bias signal end;
a gate of the twenty-fourth PMOS tube is connected with the first bias signal end, a source electrode of the twenty-fourth PMOS tube is connected with the VCC end, a drain electrode of the twenty-fourth PMOS tube is grounded through the second triode, and a base electrode of the twenty-second triode is connected with a source electrode of the twenty-first NMOS tube;
a twenty-fifth PMOS tube, a grid electrode is connected with a drain electrode of the twenty-third PMOS tube, a source electrode is connected with a VCC end, the drain electrode is used as an output end through an inverter,
and the grid electrode of the twenty-sixth NMOS tube is connected with the third bias signal end, the source electrode of the twenty-sixth NMOS tube is grounded, and the drain electrode of the twenty-fifth PMOS tube is connected with the drain electrode of the twenty-fifth PMOS tube.
The working logic of the digital logic circuit is as follows:
when the first input end receives a trigger signal, setting the first output end to be at a low level, and setting the second output end to be at a high level;
and when the second input end receives the trigger signal, setting the second output end to be at a low level, and setting the first output end to be at a high level.
Further, when the first input end receives the trigger signal, the first output end is set to be a low level, and after a preset second time delay, the second output end is set to be a high level;
and when the second input end receives the trigger signal, setting the second output end to be at a low level, and setting the first output end to be at a high level after a preset first time delay.
The chip realizes a COT control mode with fixed conversion frequency and rapid transient response characteristics and a current control mode with fixed conversion frequency and high-precision output voltage characteristics, and in the practical application process, the chip flexibly selects any one control mode by changing the connection relation of an external pin COMP.
Drawings
Fig. 1 is a schematic diagram of a conventional hysteretic control mode DC-DC buck converter.
Fig. 2 is a schematic diagram of the on-time circuit.
FIG. 3 is a logic timing diagram of the power tube controlled by the conduction time circuit and the PWM comparator.
Fig. 4 is a schematic diagram of a switch selection circuit.
Fig. 5 is a diagram showing the selection result of the switch selection circuit in the COT mode.
Fig. 6 is a schematic diagram of the selection result of the switch selection circuit in the current mode.
Fig. 7 is a schematic diagram of a COT control pattern with a fixed switching frequency.
Fig. 8 is a schematic diagram of a current control mode with a fixed switching frequency.
Fig. 9 is a schematic diagram of a simulated waveform of a switching frequency spectrum using the present invention.
Detailed description of the preferred embodiments
The invention comprises a PWM comparator, a reference circuit, a conduction time circuit, a digital logic circuit, a transconductance amplifier and a switch selection circuit, wherein the reference circuit is used for generating a reference voltage of 1.2V and a reference voltage of 0.75V; the PWM comparator is used for comparing the reference voltage with the feedback voltage; the on-time circuit is used for generating a fixed switching frequency; the digital logic circuit is used for controlling the working states of the DRVH and the DRVL and providing driving capability for the external power tube; the switch selection circuit is used for selecting the feedback voltage according to different control modes.
Referring to fig. 2 to 8, the present invention includes the following parts:
a conduction time circuit, the output end of which is connected to the first input end of the digital logic circuit;
a comparator, the output end of which is connected to the second input end of the digital logic circuit;
the digital logic circuit is provided with two output ends and is used for controlling the level states of the two output ends according to the level of the first input end EN _ on _ time and controlling the level states of the two output ends according to the level of the second input end EN _ off _ time;
the zero input end of the switch selection circuit is connected with the output end of the transconductance amplifier, the first input end of the switch selection circuit is connected with the feedback voltage end FB, the second input end of the switch selection circuit is connected with the first reference voltage end (1.2V), the third input end of the switch selection circuit is connected with the CS end, the fourth input end of the switch selection circuit is connected with the PGND end, the fifth input end of the switch selection circuit is connected with the second reference voltage end (0.75V), the first output end of the switch selection circuit is connected with the first negative input end of the comparator, the second output end of the switch selection circuit is connected with the first positive input end of the comparator, the third output end of the switch selection circuit is connected with the second positive input end of the comparator, and the fourth output end of the switch selection circuit is connected with the second negative input end of the comparator and used for realizing the selection of output signals according to the signal of the zero input end;
and the positive input end of the transconductance amplifier is connected with the second reference voltage end (0.75V), and the negative input end of the transconductance amplifier is connected with the feedback voltage end.
The on-time circuit includes:
and a switching voltage detection circuit formed by serially connecting resistors.
Referring to fig. 2, the twenty-first NMOS transistor in the present invention is referred to as "NMOS 21", and other MOS transistors are labeled similarly.
The SW port voltage detection circuit comprises a twenty-first NMOS tube and a twenty-eighth NMOS tube, wherein the source electrode of the twenty-first NMOS tube is connected with the drain electrode of the twenty-eighth NMOS tube and a twenty-fifth resistor, the twenty-fifth resistor is grounded through a capacitor, the drain electrode of the twenty-eighth NMOS tube is grounded, and the source electrode of the twenty-first NMOS tube is used as an output end;
a twenty-first PMOS tube, wherein the source electrode is connected with the VCC end, the drain electrode is grounded through a twenty-first triode PNP21, and the grid electrode is connected with the first bias signal end;
a twenty-first triode PNP21, the base of which is connected with the output end of the switching voltage detection circuit;
a source electrode of the twenty-second PMOS tube is connected with the VCC end, and a grid electrode and a drain electrode of the twenty-fifth NMOS tube are connected with a drain electrode of the twenty-fifth NMOS tube;
a twenty-fifth NMOS transistor, a gate connected to the second bias signal terminal, a source connected to the drain of the twenty-second NMOS transistor,
a twenty-second NMOS transistor, a grid electrode is connected with the drain electrode of the twenty-first PMOS transistor, a source electrode is connected with the drain electrode of the twenty-seventh NMOS transistor, a source electrode of the twenty-seventh NMOS transistor is grounded,
a twenty-third PMOS tube with a gate connected to the gate of the twenty-second PMOS tube, a source connected to the VCC end, a drain connected to the drain of the twenty-fourth NMOS tube,
a twenty-fourth NMOS transistor, a grid electrode of which is connected with the second bias signal end, and a source electrode of which is connected with a drain electrode of the twenty-third NMOS transistor;
a source electrode of the twenty-third NMOS tube is connected with a drain electrode of the twenty-seventh NMOS tube;
the grid electrode of the twenty-seventh NMOS tube is connected with a third bias signal end;
a gate of the twenty-fourth PMOS tube is connected with the first bias signal end, a source electrode of the twenty-fourth PMOS tube is connected with the VCC end, a drain electrode of the twenty-fourth PMOS tube is grounded through a second triode PNP22, and a base electrode of the twenty-second triode is connected with a source electrode of the twenty-first NMOS tube;
a twenty-fifth PMOS tube, a grid electrode is connected with a drain electrode of the twenty-third PMOS tube, a source electrode is connected with a VCC end, the drain electrode is used as an output end through an inverter,
and the grid electrode of the twenty-sixth NMOS tube is connected with the third bias signal end, the source electrode of the twenty-sixth NMOS tube is grounded, and the drain electrode of the twenty-fifth PMOS tube is connected with the drain electrode of the twenty-fifth PMOS tube.
As an example, the operating logic of the digital logic circuit is:
when the first input end receives a trigger signal, setting the first output end to be at a low level, and setting the second output end to be at a high level;
and when the second input end receives the trigger signal, setting the second output end to be at a low level, and setting the first output end to be at a high level.
Example (b):
as shown in fig. 2, in the present embodiment, the turn-on circuit includes resistors R1, R2, R3 that detect the VDDQ voltage value; r5, C1 producing switching frequencies; a comparator circuit.
In the on-time circuit, a resistor R1R 2R 3 detects an output voltage value VDDQ of the DC-DC,
the voltage value is used as a reference voltage of the comparator; the enable signal EN turns on the NMOS1 to detect the SW port voltage (POWER1 is on, SW port voltage is approximately equal to the POWER voltage Vin), and the SW port charges the resistor R5 and the capacitor C1. Therefore, the on time
When DRVH is high level, POWER1 is on, the SW port voltage value is approximately equal to Vin voltage value, SW charges R5 and C1, the voltage value on line name R800_ NEG gradually increases, when reaching to reach to
The inverter INV outputs a low level signal when the voltage value is high. This signal causes DRVH to be low, POWER1 to be off, POWER2 to be on, when VDDQ begins to fall; when the feedback voltage FB is lower than the reference voltage 0.75V, the PWM comparator outputs a low level to enable the POWER2 to be closed, the POWER1 to be opened, and the VDDQ voltage of the DC-DC output terminalStarting to increase, the feedback voltage FB increases while the SW port voltage is about equal to the supply voltage Vin, SW charges R5 and C1. This completes a cycle process.
In the POWER1 on state, the POWER voltage Vin can be periodically detected, so that the conversion frequency is a fixed value; meanwhile, the conduction time is further adjusted by adjusting the duty ratio D, and the conduction time is in direct proportion to the output voltage VDDQ and in inverse proportion to the input voltage Vin.
The invention has the main function of enabling the conversion frequency to be a fixed value, avoiding the conversion frequency of the traditional hysteresis control mode from being influenced by other parameters such as ESR, inductance L and the like, further effectively reducing EMI interference and effectively improving the reliability and stability of equipment in a system.
FIG. 3 is a logic sequence of the conduction time circuit and the PWM comparator to control the power tube.
The output signal of the on-time circuit is at low level, the signal makes DRVH at low level, POWER1 is closed, after the delay time, DRVL is at high level, POWER2 is on; the PWM output signal is low, DRVL is low, POWER2 is off, DRVH is high after a delay time, and POWER1 is on.
Fig. 4 is a switch selection circuit configuration.
An important feature of the present invention is the dual control mode, which requires the switch selection circuit to select the input signal of the corresponding PWM comparator according to different control modes. The COMP port is used to select the control mode. And the output end of the transconductance amplifier circuit is connected with a COMP port. When COMP is connected to a power supply voltage Vin, the chip works in a COT mode, NMOS8 and NMOS4 are conducted, and a reference voltage of 0.75V is connected to positive phase input ends 1 and 2 of the PWM comparator; NMOS6 and NMOS2 are turned on and the feedback voltage FB is connected to the PWM comparator negative inputs 1 and 2. When COMP is connected with the external compensation circuits Rc and Cc, the chip works in a current mode, the NMOS7 is conducted, and the COMP is connected with a positive phase input end 1 of the PWM comparator; the NMOS3 is conducted, and the CS port voltage is connected with the positive input end 2 of the PWM comparator; the NMOS5 is conducted, and the reference voltage 1.2V is connected with the negative phase input end 1 of the PWM comparator; the NMOS1 is turned on, and PGND is connected to the negative input terminal 2 of the PWM comparator.
Fig. 5 shows the chip operating in the COT mode by connecting the COMP port to the power Vin, and the switch selection circuit uses the reference voltage 0.75V and the feedback voltage FB as the input signals of the PWM comparator.
Fig. 6 shows the chip operating in the current mode by connecting the COMP port to the external compensation circuits Rc and Cc, and the switch selection circuit uses the reference voltage 1.2V, COMP port voltage, the CS port voltage, and the PGND port voltage as input signals of the PWM comparator.
Fig. 7 is a circuit configuration of COT control mode with a fixed switching frequency.
The embodiment comprises the following steps: the feedback resistors Rf1 and Rf2, the PWM comparator, the conduction time circuit and the digital logic circuit are connected in series in the chip; the peripheral devices comprise POWER switch tubes POWER1, POWER2, an inductor L and the like.
The working principle of the invention is that the inductive current generates ripple waves on ESR, when the ripple voltage gradually decreases, the voltage of FB at a feedback point also decreases, when the feedback voltage FB is lower than the reference voltage 0.75V, the PWM comparator outputs low level, the signal enables POWER2 to be closed through a digital logic circuit, the POWER1 is conducted, and the output voltage VDDQ starts to increase; when POWER1 is turned on, in the on-time circuit, the SW port charges R5 and C1, generating a ripple voltage whose value reaches the reference voltage
At that time, the on-time circuit outputs a low level, and this signal turns POWER1 off, POWER2 turns on, and the output voltage VDDQ begins to drop.
Fig. 8 is a circuit configuration of a current control mode with a fixed switching frequency.
The embodiment comprises the following steps: the chip is internally connected with feedback resistors Rf1 and Rf2, a transconductance amplifier, a PWM comparator, an on-time circuit and a digital logic circuit in series; the peripheral devices comprise POWER switch tubes POWER1, POWER2, an inductor L, a current detection resistor Rs and the like. On the basis of the COT mode, a transconductance amplifier, an external detection resistor Rs and compensation circuits Rc and Cc are added, so that the chip has a current control mode.
The working principle of the invention is that POWER2 is conducted, voltage drop is generated on a detection resistor Rs, the difference value generated by the voltage value and PGND is compared with the difference value generated by COMP port voltage and reference 1.2V through a PWM comparator, and the conduction or closing state of a POWER switch tube is further controlled.
A transconductance amplifier is mainly used for designing a current mode, loop gain is increased, and output voltage precision is improved. The gain of the feedback voltage FB to the output terminal VDDQ is
The gain produced by the transconductance amplifier is AV2＝Gm×R0(ii) a Gain of PWM comparator and power switch tube is
So that the loop gain is
Fig. 9 is a whole circuit simulation waveform. At the switching frequency 400KHz point, the generated electromagnetic interference is the largest, and at the other frequency points, the interference is small. The simulation result proves the feasibility of the scheme and solves the defects of the traditional hysteresis control mode.
Claims (4)
1. A fixed frequency dual-mode synchronous buck controller, comprising:
a conduction time circuit, the output end of which is connected to the first input end of the digital logic circuit;
a comparator, the output end of which is connected to the second input end of the digital logic circuit;
the digital logic circuit is provided with two output ends and is used for controlling the level states of the two output ends according to the level of the first input end and controlling the level states of the two output ends according to the level of the second input end;
the zero input end of the switch selection circuit is connected with the output end of the transconductance amplifier, the first input end of the switch selection circuit is connected with the feedback voltage end, the second input end of the switch selection circuit is connected with the first reference voltage end, the third input end of the switch selection circuit is connected with the CS end, the fourth input end of the switch selection circuit is connected with the PGND end, the fifth input end of the switch selection circuit is connected with the second reference voltage end, the first output end of the switch selection circuit is connected with the first negative input end of the comparator, the second output end of the switch selection circuit is connected with the first positive input end of the comparator, the third output end of the switch selection circuit is connected with the second positive input end of the comparator, and the fourth output end of the switch selection circuit is connected with the second negative input end of the comparator and used for realizing the selection of output signals according to the signal of the zero input end;
and the positive input end of the transconductance amplifier is connected with the second reference voltage end, and the negative input end of the transconductance amplifier is connected with the feedback voltage end.
2. The fixed-frequency dual-mode synchronous buck controller of claim 1, wherein the on-time circuit comprises:
a switching voltage detection circuit formed by serially connecting resistors,
the SW port voltage detection circuit comprises a twenty-first NMOS tube and a twenty-eighth NMOS tube, wherein the source electrode of the twenty-first NMOS tube is connected with the drain electrode of the twenty-eighth NMOS tube and a twenty-fifth resistor, the twenty-fifth resistor is grounded through a capacitor, the drain electrode of the twenty-eighth NMOS tube is grounded, and the source electrode of the twenty-first NMOS tube is used as an output end;
a twenty-first PMOS tube, wherein the source electrode of the twenty-first PMOS tube is connected with the VCC end, the drain electrode of the twenty-first PMOS tube is grounded through a twenty-first triode, and the grid electrode of the twenty-first PMOS tube is connected with the first bias signal end;
a twenty-first triode, the base of which is connected with the output end of the switching voltage detection circuit;
a source electrode of the twenty-second PMOS tube is connected with the VCC end, and a grid electrode and a drain electrode of the twenty-fifth NMOS tube are connected with a drain electrode of the twenty-fifth NMOS tube;
a twenty-fifth NMOS transistor, a gate connected to the second bias signal terminal, a source connected to the drain of the twenty-second NMOS transistor,
a twenty-second NMOS transistor, a grid electrode is connected with the drain electrode of the twenty-first PMOS transistor, a source electrode is connected with the drain electrode of the twenty-seventh NMOS transistor, a source electrode of the twenty-seventh NMOS transistor is grounded,
a twenty-third PMOS tube with a gate connected to the gate of the twenty-second PMOS tube, a source connected to the VCC end, a drain connected to the drain of the twenty-fourth NMOS tube,
a twenty-fourth NMOS transistor, a grid electrode of which is connected with the second bias signal end, and a source electrode of which is connected with a drain electrode of the twenty-third NMOS transistor;
a source electrode of the twenty-third NMOS tube is connected with a drain electrode of the twenty-seventh NMOS tube;
the grid electrode of the twenty-seventh NMOS tube is connected with a third bias signal end;
a gate of the twenty-fourth PMOS tube is connected with the first bias signal end, a source electrode of the twenty-fourth PMOS tube is connected with the VCC end, a drain electrode of the twenty-fourth PMOS tube is grounded through the second triode, and a base electrode of the twenty-second triode is connected with a source electrode of the twenty-first NMOS tube;
a twenty-fifth PMOS tube, a grid electrode is connected with a drain electrode of the twenty-third PMOS tube, a source electrode is connected with a VCC end, the drain electrode is used as an output end through an inverter,
and the grid electrode of the twenty-sixth NMOS tube is connected with the third bias signal end, the source electrode of the twenty-sixth NMOS tube is grounded, and the drain electrode of the twenty-fifth PMOS tube is connected with the drain electrode of the twenty-fifth PMOS tube.
3. The fixed frequency dual-mode synchronous buck controller of claim 1, wherein the digital logic circuit has operating logic to:
when the first input end receives a trigger signal, setting the first output end to be at a low level, and setting the second output end to be at a high level;
and when the second input end receives the trigger signal, setting the second output end to be at a low level, and setting the first output end to be at a high level.
4. The fixed-frequency dual-mode synchronous buck controller of claim 3,
when the first input end receives a trigger signal, setting the first output end to be at a low level, and setting the second output end to be at a high level after a preset second time delay;
and when the second input end receives the trigger signal, setting the second output end to be at a low level, and setting the first output end to be at a high level after a preset first time delay.
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