CN113517324A

CN113517324A - Display substrate, manufacturing method thereof and display device

Info

Publication number: CN113517324A
Application number: CN202110572148.2A
Authority: CN
Inventors: 王本莲; 杜丽丽; 龙跃; 黄炜赟
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2021-05-25
Filing date: 2021-05-25
Publication date: 2021-10-19

Abstract

The disclosure provides a display substrate, a manufacturing method thereof and a display device. The display substrate comprises a first display area and a second display area surrounding the first display area; the first display area is provided with a plurality of first light-emitting devices, and the second display area is provided with a plurality of second light-emitting devices; the second display area is provided with a plurality of first pixel circuits corresponding to the first light-emitting devices and a plurality of second pixel circuits corresponding to the second light-emitting devices; wherein the plurality of first pixel circuits are positioned on at least three sides of the first display area.

Description

Display substrate, manufacturing method thereof and display device

Technical Field

The disclosure relates to the field of display technologies, and in particular, to a display substrate, a manufacturing method thereof, and a display device.

Background

With the continuous development of the full-face screen, the blind hole screen and the through hole screen appear in succession behind the Liuhai screen and the water drop screen in two years to further improve the screen occupation ratio.

However, even the through-hole screen cannot realize a true full-screen. As shown in fig. 1, in order to enable the camera to collect external light, the display screen 100 needs to be provided with an opening 102 at a position corresponding to the camera, and an image cannot be displayed in an area where the opening 102 is located.

The camera under the screen is a new comprehensive screen technology, and an area where the camera is arranged on the display screen can display images and can shoot pictures. But the light transmittance of the under-screen camera area is problematic.

Disclosure of Invention

The disclosure provides a display substrate, a manufacturing method thereof and a display device.

In a first aspect of the present disclosure, a display substrate is provided, which includes a first display area and a second display area surrounding the first display area; the first display area is provided with a plurality of first light-emitting devices, and the second display area is provided with a plurality of second light-emitting devices; the second display area is provided with a plurality of first pixel circuits corresponding to the first light-emitting devices and a plurality of second pixel circuits corresponding to the second light-emitting devices; wherein the plurality of first pixel circuits are positioned on at least three sides of the first display area.

In a second aspect of the present disclosure, a display device is provided, which includes the display substrate of the first aspect.

In a third aspect of the present disclosure, a method for manufacturing a display substrate is provided, including:

obtaining a substrate base plate;

forming a plurality of first light emitting devices in a first display region of the substrate;

forming a plurality of second light emitting devices in a second display region of the substrate, the second display region surrounding the first display region;

forming a plurality of first pixel circuits corresponding to the first light emitting devices and a plurality of second pixel circuits corresponding to the second light emitting devices in a second display region of the substrate;

wherein the plurality of first pixel circuits are positioned on at least three sides of the first display area.

According to the display substrate, the manufacturing method of the display substrate and the display device, the first pixel circuits are arranged on at least three sides of the first display area, so that the wiring quantity can be increased in a single wiring layer, the times of a composition process can be reduced, the cost is reduced, and the factory productivity is improved.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure or related technologies, the drawings needed to be used in the description of the embodiments or related technologies are briefly introduced below, and it is obvious that the drawings in the following description are only embodiments of the present disclosure, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

Fig. 1 shows a schematic view of a display screen with a camera aperture.

FIG. 2A shows a schematic diagram of an exemplary display substrate with an off-screen camera.

Fig. 2B shows a schematic view of the light emitting device layers of the display substrate.

Fig. 2C is a schematic diagram showing a positional relationship between the first light emitting device and the first pixel circuit in the display substrate.

Fig. 3A illustrates a schematic view of an exemplary display substrate provided by an embodiment of the present disclosure.

Fig. 3B illustrates a schematic diagram of a positional relationship between a first light emitting device and a first pixel circuit in a display substrate according to an embodiment of the present disclosure.

Fig. 3C shows a schematic diagram of a display substrate first display area exemplarily equally divided into four regions according to an embodiment of the present disclosure.

Fig. 3D illustrates an exemplary schematic diagram of the positional relationship of each group of first light emitting devices and each group of first pixel circuits in the display substrate according to the embodiment of the disclosure.

Fig. 3E shows a schematic diagram of an exemplary lead layer of a display substrate according to an embodiment of the present disclosure.

Fig. 3F illustrates an exemplary light emitting device layout of a display substrate according to an embodiment of the present disclosure.

Fig. 4 shows a schematic flow chart of an exemplary method for manufacturing a display substrate provided by the embodiment of the present disclosure.

Detailed Description

For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

It is to be noted that technical terms or scientific terms used in the embodiments of the present disclosure should have a general meaning as understood by those having ordinary skill in the art to which the present disclosure belongs, unless otherwise defined. The use of "first," "second," and similar terms in the embodiments of the disclosure is not intended to indicate any order, quantity, or importance, but rather to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

Fig. 2A shows a schematic diagram of an exemplary display substrate 200 with an off-screen camera. Fig. 2B shows a schematic view of the light emitting device layers of the display substrate 200.

As shown in fig. 2A and 2B, the display substrate 200 may include a first display region 202 and a second display region 204 surrounding the first display region 202. The first display region 202 has a plurality of first light emitting devices 2022 disposed therein, and the second display region 204 has a plurality of second light emitting devices 2042 disposed therein.

On the back side (opposite to the light emitting direction) of the light emitting device 2022 in the first display region 202, a screen down camera (not shown) may be disposed, and the screen down camera may collect external light through the display substrate 200 to realize imaging.

Fig. 2C is a schematic diagram showing a positional relationship between the first light-emitting device 2022 and the first pixel circuit 2024 in the display substrate 200.

As shown in fig. 2C, in order to increase the light transmittance of the display substrate 200 in the first display area 202, so that the camera disposed under the screen of the first display area 202 can collect more external light to better realize imaging, the first pixel circuit 2024 corresponding to the first light emitting device 2022 of the first display area 202 may be disposed in the second display area 204, thereby preventing light shielding caused when the first pixel circuit 2024 is disposed in the first display area 202.

In this way, only the light emitting device portion is reserved in the first display area 202, and the corresponding driving circuit is disposed outside the first display area 202, so that the light transmittance of the display substrate 200 in the first display area 202 is improved, and it is beneficial for the under-screen camera to complete imaging.

In order to transmit the driving signal of the first pixel circuit 2024 into the first light emitting device 2022, the first pixel circuit 2024 and the first light emitting device 2022 may be correspondingly connected by a wiring 2026. However, due to the process limitation of the Pitch (Pitch) of the trace 2026, when the trace 2026 is routed, all the traces 2026 connecting the first pixel circuit 2024 and the first light emitting device 2022 may not be formed in the same layer, and the traces 2026 need to be formed in different layers.

For example, assuming that the area of the first display region 202 is about 3mm × 3mm, the size of the pixel unit (Pitch) is about 60 μm, so there are about 50 × 50 pixel units in the first display region 202. Assuming a subpixel arrangement of 2G1B1R (two green subpixels share one blue subpixel and one red subpixel), 100 × 50 subpixels are used. The sub-pixels need to electrically connect the first pixel circuit 2024 outside the first display region 202 and the first light emitting device 2022 in the first display region 202 through the trace 2026.

As shown in fig. 2C, when the first pixel circuits 2024 are disposed on two sides of the first display area 202, 50 traces 2026 need to be respectively pulled out to the left and the right for each row of pixels in the first display area 202 (all traces 2026 are not shown in fig. 2C). Thus, pulling the traces to both sides can compress the trace Pitch in the lateral direction as compared to pulling the trace to only one side.

Typically, Pitch of trace 2026 is about 4 μm, so for a single layer trace, one row of pixels can only be pulled: the pixel unit Pitch/trace Pitch is 60 μm/4 μm and 15 lines.

Therefore, to pull 50 ITO lines to the left and right of each row, 50/15-3.33 layers of traces are needed. Thus, at least 4 layers of traces need to be added, and 8 patterning processes (masks) are required to manufacture the 4 layers of traces, which is costly and affects the productivity of the factory.

In view of this, the present disclosure provides a display substrate including a first display area and a second display area surrounding the first display area; the first display area is provided with a plurality of first light-emitting devices, and the second display area is provided with a plurality of second light-emitting devices; the second display area is provided with a plurality of first pixel circuits corresponding to the first light-emitting devices and a plurality of second pixel circuits corresponding to the second light-emitting devices; wherein the plurality of first pixel circuits are positioned on at least three sides of the first display area. The first pixel circuits are arranged on at least three sides of the first display area, so that the wiring quantity can be increased in a single wiring layer, the times of a composition process can be reduced, the cost is reduced while full-screen display is achieved, and the factory capacity is improved.

Fig. 3A illustrates a schematic diagram of an exemplary display substrate 300 provided by an embodiment of the present disclosure. Fig. 3B illustrates a schematic positional relationship of the first light emitting devices 3022a to d and the first pixel circuits 3024a to d in the display substrate 300 according to an embodiment of the present disclosure.

As shown in fig. 3A and 3B, the display substrate 300 includes a first display area 302 and a second display area 304 surrounding the first display area 302.

The first display area 302 is provided with a plurality of first light emitting devices 3022a to d, and the second display area 304 is provided with a plurality of second light emitting devices 3042. The second display region 304 may further be provided with a plurality of first pixel circuits 3024a to d corresponding to the first light emitting devices 3022a to d and a plurality of second pixel circuits (not shown) corresponding to the second light emitting device 3042.

The display substrate 300 may further include an image pickup unit (not shown in the drawings). The camera unit can be arranged in the first display area 302 (or the orthographic projection of the camera unit in the display substrate 300 is positioned in the first display area 302) and positioned on one side of the light emitting direction far away from the first light emitting device 3022, so that an image can be displayed in the camera area of the display substrate 300, and external light can be collected to complete imaging, thereby realizing a real comprehensive screen.

The plurality of first pixel circuits 3024a to d may be located on at least three sides of the first display region 302.

For example, as shown in fig. 3B, a first pixel circuit 3024a may be disposed on a first side (e.g., a left side with reference to fig. 3B) of the first display area 302, a first pixel circuit 3024B may be disposed on a second side (e.g., an upper side with reference to fig. 3B) of the first display area 302, and a first pixel circuit 3024c may be disposed on a third side (e.g., a right side with reference to fig. 3B) of the first display area 302. In this way, by disposing the first pixel circuits on three sides of the first display area 302, the number of wires in a single-layer wire can be increased compared to that disposed on two sides of the first display area 302. Because the trace on one side of the added arrangement (e.g., trace 3026b) is perpendicular to the trace on the other two sides (e.g., traces 3026a and 3026c), and does not interfere with each other, only the Pitch requirement between the traces on that side needs to be considered, thereby increasing the number of single-layer traces using the side of the added arrangement. Therefore, due to the increase of the number of the single-layer routing, the number of the routing layers can be correspondingly reduced, so that the composition process is saved, the cost is reduced, and the factory capacity is improved.

The three-side arrangement manner of the first pixel circuit above is merely exemplary, and the first pixel circuit may be optionally arranged in three-side based on the premise that four sides exist in the first display region 302, and is not limited to the above example.

In some embodiments, as shown in fig. 3A and 3B, a plurality of first pixel circuits 3024a to d may be disposed on four sides of the first display area 302, so that the number of single-layer traces can be further increased.

As in the previous calculation, similarly, the area of the first display area 302 is 3mm × 3mm, the size of the pixel unit (Pitch) is about 60 μm, and the number of required routing layers is about (50/13)/2 to 1.92 layers under the condition that the routing Pitch is 4 μm, that is, the original 4-layer routing and 8-layer composition process needs to be added, instead of the 2-layer routing and 4-layer composition process, which greatly improves the factory productivity and reduces the cost.

Thus, the pixel circuits outside the first display area 302 are compressed longitudinally in addition to being compressed transversely, and the pixel circuits corresponding to the light emitting devices of the first display area 302 can be dispersedly placed on four sides of the first display area 302, so that the number of the wires required to be pulled out in each direction is further reduced by half compared with the wires pulled out on two sides, and under the condition of the same wire Pitch, the number of newly added wire layers can be reduced by half, thereby better improving the factory productivity and reducing the cost. Meanwhile, even if the number of routing layers is halved, the number of routing lines on the same routing layer is increased, and the number of Pixels Per Inch (PPI) in the first display area 302 can be adaptively increased, thereby improving the display effect of the first display area 302.

In some embodiments, as shown in fig. 3A and 3B, the plurality of first pixel circuits 3024 a-d may be equally divided into four groups. A first group of first pixel circuits 3024a may be disposed at a first side (e.g., a left side with reference to fig. 3B) of the first display region 302 and connected to the corresponding first light emitting devices 3022a through first wires 3026 a. The second group first pixel circuit 3024B may be disposed at a second side (e.g., an upper side with reference to fig. 3B) of the first display region 302 and connected to the corresponding first light emitting device 3022B through a second wire 3026B. The third group first pixel circuit 3024c may be disposed at a third side (e.g., a right side with reference to fig. 3B) of the first display region 302 and connected to the corresponding first light emitting device 3022c through a third wire 3026 c. The fourth group first pixel circuit 3024d may be disposed on a fourth side (e.g., a lower side with reference to fig. 3B) of the first display region 302 and connected to the corresponding first light emitting device 3022d through a fourth wire 3026 d. The first lead 3026a is parallel to the third lead 3026c, and the first lead 3026a is perpendicular to the second lead 3026b and the fourth lead 3026d, respectively.

Accordingly, the first display area 302 may be divided into four regions having equal areas. Fig. 3C shows a schematic view of the display substrate 300 with the first display area 302 illustratively equally divided into four regions, according to an embodiment of the disclosure. As shown in fig. 3C, the first display region 302 may be divided into a first region a, a second region B, a third region C, and a fourth region D having equal areas. As shown in fig. 3B, the plurality of first light emitting devices 3022a to d may be equally divided into four groups by the four regions. The first group first light emitting device 3022a is connected to the first group first pixel circuit 3024a, the second group first light emitting device 3022b is connected to the second group first pixel circuit 3024b, the third group first light emitting device 3022c is connected to the third group first pixel circuit 3024c, and the fourth group first light emitting device 3022d is connected to the fourth group first pixel circuit 3024 d.

In some embodiments, the distance between the center of each group of first light emitting devices and the center of the corresponding group of first pixel circuits is smaller than the distance between the center of the group of first light emitting devices and the centers of the other groups of first pixel circuits, so that the length of the lead wires of the correspondingly connected group of first light emitting devices and the first pixel circuit group is minimum, and the wiring and the process manufacturing are facilitated.

Fig. 3D illustrates an exemplary schematic diagram of the positional relationship between each group of first light emitting devices and each group of first pixel circuits in the display substrate 300 according to the embodiment of the disclosure. As shown in fig. 3D, a connection line between the center C1 of the first group first light emitting device 3022a and the center C2 of its corresponding group first pixel circuit 3024a is significantly shorter than a connection line between the center C1 and the centers C3 to C5 of the second to fourth groups of first pixel circuits 3024b to D. Similarly, the distance between the center of the first light emitting device in the other group and the center of the first pixel circuit in the corresponding group is also smaller than the distance between the center of the first light emitting device in the group and the center of the first pixel circuit in the other group, and details are not repeated here.

In some embodiments, as shown in fig. 3B, each group of the first light emitting devices 3022a to d may form an isosceles triangle array, and correspondingly, each group of the first pixel circuits 3024a to d may also form an isosceles triangle array, so that the leads connecting the first light emitting devices and the corresponding first pixel circuits may be straight lines, which is beneficial for wiring and process manufacturing.

In some embodiments, in order to further improve the light transmittance of the first display area 302 so that the camera unit can collect more light, the first lead wire 3026a, the second lead wire 3026b, the third lead wire 3026c, and the fourth lead wire 3026d are transparent metal wires, for example, ITO.

In some embodiments, the display substrate 300 may further include a wiring layer. Fig. 3E shows a schematic diagram of an exemplary lead layer of the display substrate 300 according to an embodiment of the present disclosure. As shown in fig. 3E, a first lead 3026a, a second lead 3026b, a third lead 3026c, and a fourth lead 3026d are disposed in the same lead layer, that is, at least a portion of the first lead 3026a, the second lead 3026b, the third lead 3026c, and the fourth lead 3026d are disposed in the same layer, so that the number of single-layer traces can be increased, and accordingly, the number of trace layers can be reduced, thereby saving the patterning process, reducing the cost, and improving the factory productivity.

In some embodiments, other methods may also be employed to further increase the light transmittance of the first display area 302. Fig. 3F illustrates an exemplary light emitting device layout of the display substrate 300 according to an embodiment of the present disclosure. As shown in fig. 3F, the arrangement density of the second light emitting devices 3042 is greater than that of the first light emitting devices 3022. In other words, the number of Pixels Per Inch (PPI) of the first light emitting device 3022 is smaller, and thus the inter-device gap is larger, facilitating the transmission of light, thereby improving the light transmittance of the first display region 302.

The embodiment of the present disclosure further provides a display device including any one embodiment or a combination of embodiments of the display substrate 300. In some embodiments, the display device may be an organic light emitting diode display device (OLED).

The display device in this embodiment may be: any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a notebook computer, a digital photo frame, a navigator and the like.

The embodiment of the disclosure also provides a manufacturing method of the display substrate.

Fig. 4 shows a schematic flow chart of an exemplary method 400 for manufacturing the display substrate 300 provided by the embodiment of the present disclosure. As shown in fig. 4, the method 400 may include the following steps.

At step 402, a substrate base plate is acquired.

In step 404, a plurality of first light emitting devices 3022 are formed in the first display area 302 of the substrate base.

At step 406, a plurality of second light emitting devices 3042 are formed in the second display area 304 of the substrate, the second display area 304 surrounding the first display area 302.

In step 408, a plurality of first pixel circuits 3024a to d corresponding to the first light emitting device 3022 and a plurality of second pixel circuits corresponding to the second light emitting device 3042 are formed in the second display region 304 of the substrate. The plurality of first pixel circuits 3024a to d are located on at least three sides of the first display area 302.

In some embodiments, the plurality of first pixel circuits are equally divided into four groups, and the method 400 may further include the steps of:

a first wiring 3026a connecting the first group of first pixel circuits 3024a and the corresponding first light emitting device 3022a is formed, the first group of first pixel circuits 3024a being located at a first side of the first display region 302;

a second wiring 3026b connecting the second group of first pixel circuits 3024b and the corresponding first light emitting device 3022b is formed, the second group of first pixel circuits 3024b being located at the second side of the first display region 302;

a third wiring 3026c connecting the third group first pixel circuit 3024c and the corresponding first light emitting device 3022c is formed, the third group first pixel circuit 3024c being located on the third side of the first display region 302;

a fourth wiring 3026d connecting the fourth group first pixel circuit 3024d and the corresponding first light emitting device 3022 is formed, the fourth group first pixel circuit 3024d being located on the fourth side of the first display region 302;

the first lead 3026a is parallel to the third lead 3026c, and the first lead 3026a is perpendicular to the second lead 3026b and the fourth lead 3026d, respectively.

In some embodiments, the method 400 may further include the steps of:

forming a lead layer on a base substrate; the lead layer is provided with a first lead, a second lead, a third lead and a fourth lead.

The method 400 of the above embodiment is used for manufacturing the display substrate 300 corresponding to any of the above embodiments, and has the advantages of the corresponding display substrate embodiment, which are not described herein again.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of the present disclosure, also technical features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present disclosure as described above, which are not provided in detail for the sake of brevity.

In addition, well-known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown in the provided figures for simplicity of illustration and discussion, and so as not to obscure the embodiments of the disclosure. Furthermore, devices may be shown in block diagram form in order to avoid obscuring embodiments of the present disclosure, and this also takes into account the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the embodiments of the present disclosure are to be implemented (i.e., specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the embodiments of the disclosure can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative instead of restrictive.

While the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic ram (dram)) may use the discussed embodiments.

The disclosed embodiments are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalents, improvements, and the like that may be made within the spirit and principles of the embodiments of the disclosure are intended to be included within the scope of the disclosure.

Claims

1. A display substrate includes a first display area and a second display area surrounding the first display area; the first display area is provided with a plurality of first light-emitting devices, and the second display area is provided with a plurality of second light-emitting devices; the second display area is provided with a plurality of first pixel circuits corresponding to the first light-emitting devices and a plurality of second pixel circuits corresponding to the second light-emitting devices; wherein the plurality of first pixel circuits are positioned on at least three sides of the first display area.

2. The display substrate of claim 1, wherein a plurality of the first pixel circuits are located on four sides of the first display region.

3. The display substrate of claim 2, wherein the plurality of first pixel circuits are equally divided into four groups, a first group of the first pixel circuits is located at a first side of the first display region and connected to the corresponding first light emitting devices through first wires, a second group of the first pixel circuits is located at a second side of the first display region and connected to the corresponding first light emitting devices through second wires, a third group of the first pixel circuits is located at a third side of the first display region and connected to the corresponding first light emitting devices through third wires, and a fourth group of the first pixel circuits is located at a fourth side of the first display region and connected to the corresponding first light emitting devices through fourth wires; wherein the first lead is parallel to the third lead, and the first lead is perpendicular to the second lead and the fourth lead, respectively.

4. The display substrate of claim 3, wherein the first display region is divided into four regions having equal areas, and the plurality of first light emitting devices are equally divided into four groups by the four regions; the first group of first light-emitting devices is correspondingly connected with the first group of first pixel circuits, the second group of first light-emitting devices is correspondingly connected with the second group of first pixel circuits, the third group of first light-emitting devices is correspondingly connected with the third group of first pixel circuits, and the fourth group of first light-emitting devices is correspondingly connected with the fourth group of first pixel circuits.

5. The display substrate of claim 4, wherein a distance between a center of each group of the first light emitting devices and a center of the corresponding group of the first pixel circuits is smaller than a distance between the center of the group of the first light emitting devices and a center of the other group of the first pixel circuits.

6. The display substrate of claim 5, wherein each group of the first light emitting devices forms an isosceles triangle array, and each group of the first pixel circuits correspondingly forms an isosceles triangle array.

7. The display substrate of claim 6, wherein the first, second, third, and fourth leads are transparent metal traces.

8. The display substrate of claim 3, further comprising a lead layer in which the first, second, third, and fourth leads are disposed.

9. The display substrate according to any one of claims 1 to 8, further comprising an image pickup unit provided in the first display region on a side away from a light emitting direction of the first light emitting device.

10. The display substrate of any one of claims 1-8, wherein the second light emitting devices are arranged at a density greater than the density of the first light emitting devices.

11. A display device comprising the display substrate of any one of claims 1-10.

12. The display device of claim 11, wherein the display device is an organic light emitting diode display device.

13. A method of manufacturing a display substrate, comprising:

obtaining a substrate base plate;

14. The method of claim 13, wherein the plurality of first pixel circuits are equally divided into four groups, the method further comprising:

forming a first lead connecting a first group of first pixel circuits and corresponding first light emitting devices, the first group of first pixel circuits being located on a first side of the first display region;

forming a second lead connecting a second group of first pixel circuits and the corresponding first light emitting devices, wherein the second group of first pixel circuits are positioned on a second side of the first display area;

forming a third lead connecting a third group of first pixel circuits and the corresponding first light emitting devices, the third group of first pixel circuits being located on a third side of the first display region;

forming a fourth lead connecting a fourth group of first pixel circuits and corresponding first light emitting devices, the fourth group of first pixel circuits being located at a fourth side of the first display region;

wherein the first lead is parallel to the third lead, and the first lead is perpendicular to the second lead and the fourth lead, respectively.

15. The method of claim 14, further comprising:

forming a lead layer on the substrate base plate;

the first lead, the second lead, the third lead and the fourth lead are arranged in the lead layer.