CN113517223B - Method for manufacturing active area metal zero layer - Google Patents
Method for manufacturing active area metal zero layer Download PDFInfo
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- CN113517223B CN113517223B CN202110723734.2A CN202110723734A CN113517223B CN 113517223 B CN113517223 B CN 113517223B CN 202110723734 A CN202110723734 A CN 202110723734A CN 113517223 B CN113517223 B CN 113517223B
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 123
- 239000002184 metal Substances 0.000 title claims abstract description 123
- 238000000034 method Methods 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000010410 layer Substances 0.000 claims abstract description 96
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000005530 etching Methods 0.000 claims abstract description 19
- 239000011229 interlayer Substances 0.000 claims abstract description 14
- 238000001259 photo etching Methods 0.000 claims abstract description 10
- 238000004140 cleaning Methods 0.000 claims abstract description 6
- 239000011261 inert gas Substances 0.000 claims abstract description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 15
- 229910052721 tungsten Inorganic materials 0.000 claims description 15
- 239000010937 tungsten Substances 0.000 claims description 15
- 239000004020 conductor Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims description 3
- 238000007517 polishing process Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 239000011148 porous material Substances 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003344 environmental pollutant Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 231100000719 pollutant Toxicity 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a manufacturing method of an active area metal zero layer, which comprises the following steps: step one, providing a semiconductor substrate for completing the front-end process. And step two, photoetching to define a forming area of the metal zero layer of the active area. And thirdly, etching the interlayer film of the forming area of the metal zero layer of the active area to form a first middle connecting groove. And fourthly, performing pretreatment before metal filling by adopting inert gas bombardment and plasma cleaning, and enlarging the size of the first middle section connecting groove and finally controlling the size and the shape of the first middle section connecting groove by utilizing the pretreatment before metal filling. And fifthly, filling metal in the first middle section connecting groove to form an active area metal zero layer. The invention can well control the size and the morphology of the middle section connecting groove, can improve the filling performance of the metal zero layer of the active region, and can simultaneously prevent the short circuit between the metal zero layer of the active region and the grid electrode and the too small contact area with the active region.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing an active region metal zero layer (M0A).
Background
After the front end of line (FEOL) process is completed, a middle of line process (MOL) is required in which the contact structures at the tops of the source, drain and gate structures are formed, M0A is used to make contact with the source and drain regions and the gate connection metal zero layer (M0P) is used to make contact with the gate structure in order to make a smaller contact structure. Both M0A and M0P are achieved by first forming the middle connecting grooves and then filling the middle connecting grooves with metal, typically tungsten.
With further shrinking of advanced semiconductor process line widths, the size of the middle-stage connection trenches becomes smaller and smaller, and in a 14nm fin transistor (FinFET) process, the distance between gates in the SRAM region has been reduced to 90nm, while the size of the middle-stage connection trenches has been smaller than 30nm. The outline and the size of the middle connecting groove become a critical problem for restricting the improvement of the yield of the advanced system Cheng Kaifa, and the resistance and parasitic capacitance of the device connecting section are obviously affected. Too small a size of the middle connecting slot can result in open circuit (open) of the connection with the active region; too large a size of the middle connecting slot can significantly increase parasitic capacitance (C), and in severe cases even cause short circuit (short) with the gate, the size and profile of the middle connecting slot can also affect the filling of subsequent metals such as tungsten.
As the line width of advanced semiconductor processes is further reduced, the problem of tungsten filling of the middle-stage connection slots becomes more and more pronounced. Because the middle section size is too little when tungsten fills, seal on the top when tungsten block fills easily, lead to subsequent tungsten unable further to fill, and then lead to inside gap and the cavity that exist of tungsten that fills, this resistance that can increase the linkage segment, gap and the cavity in tungsten also can further influence the filling of back end contact hole.
Disclosure of Invention
The invention aims to provide a manufacturing method of an active area metal zero layer, which can well control the size and the morphology of a middle section connecting groove, can improve the filling performance of the active area metal zero layer and can simultaneously prevent short circuit between the active area metal zero layer and a grid electrode and over-small contact area between the active area metal zero layer and the active area.
In order to solve the technical problems, the manufacturing method of the active region metal zero layer provided by the invention comprises the following steps:
step one, providing a semiconductor substrate with a front-end process, forming a gate structure on the semiconductor substrate and filling an interlayer film in a spacer of the gate structure.
And step two, photoetching to define a forming area of the metal zero layer of the active area.
And thirdly, etching the interlayer film of the forming area of the active area metal zero layer to form a first middle connecting groove.
And fourthly, performing pretreatment before metal filling by adopting inert gas bombardment and plasma cleaning, and expanding the size of the first middle section connecting groove and finally controlling the size and the shape of the first middle section connecting groove by utilizing the pretreatment before metal filling.
And fifthly, filling metal in the first middle section connecting groove to form the active area metal zero layer.
In the first step, a drain region and a source region are formed in the semiconductor substrate at two sides of the gate structure, and the active region metal zero layer is formed on the top of the drain region and the source region and is in good contact.
In a further improvement, in the fifth step, the metal material of the active area metal zero layer includes tungsten.
In a further improvement, in the fifth step, before forming tungsten, a step of forming a Ti layer and a TiN layer is further included.
The further improvement is that the photoetching definition of the second step ensures that short circuit does not occur between the first middle section connecting groove and the grid structure after the etching of the third step is completed.
In the fourth step, the pre-metal filling pretreatment increases the top opening of the first middle section connecting groove, and the pre-metal filling pretreatment is required to ensure that the final size and morphology of the first middle section connecting groove can not generate pores or hollows in the metal filling in the fifth step.
A further improvement is that the pretreatment before metal filling is required to ensure that the bottom area of the first middle section connecting groove is increased to reduce the contact resistance of the active area metal zero layer and the active area to a required value.
In a further improvement, in the first step, the semiconductor substrate includes a silicon substrate.
A further improvement is that a fin is also formed on the semiconductor substrate.
The grid structure is further improved by laminating a grid dielectric layer and a grid conductive material layer.
A further improvement is that the gate dielectric layer comprises a high dielectric constant layer and the gate conductive material layer comprises a metal gate.
A further improvement is that the metal gate includes a metal work function layer and a metal conductive material layer.
A further improvement is that the top surface of the gate structure is also covered with the interlayer film.
Further improvement is that after the third step is completed and before the fourth step is performed, the method further comprises:
and forming a second middle section connecting groove penetrating through the interlayer film at the top of the gate structure by adopting a photoetching and etching process.
And step four, the pretreatment before metal filling also carries out treatment on the second middle section connecting groove.
And fifthly, filling metal in the second middle section connecting groove and forming a gate connecting metal zero layer.
The further improvement is that the fifth step comprises the following sub-steps:
and depositing metal to completely fill the first middle section connecting groove and the second middle section connecting groove, wherein the metal also extends to the outside of the first middle section connecting groove and the second middle section connecting groove.
And performing a metal chemical mechanical polishing process to remove metal outside the first middle section connecting groove and the second middle section connecting groove.
The invention does not directly determine the size and the shape of the middle section connecting groove at the top of the active region such as the source region or the drain region, namely the first middle section connecting groove, but adopts the photoetching and etching process to form the first middle section connecting groove with smaller size, thus well ensuring that the first middle section connecting groove and the grid are not in short circuit; and then, the first middle connecting groove is pretreated before metal filling, namely pretreatment before metal filling is carried out, and the pretreatment before metal filling is combined with inert gas bombardment and plasma cleaning, so that not only can the treatment on pollutants in the etching process of the first middle connecting groove be realized, but also the size of the first middle connecting groove can be enlarged, and the appearance of reduced top necking can be formed.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a flow chart of a method of fabricating an active region metal zero layer according to an embodiment of the present invention;
fig. 2A to fig. 2F are schematic device structures at each step of the method for manufacturing an active region metal zero layer according to an embodiment of the present invention.
Detailed Description
Referring to fig. 1, a flow chart of a method for manufacturing an active area metal zero layer 110 according to an embodiment of the invention is shown; fig. 2A to 2E are schematic views of device structures in steps of a method for manufacturing an active region metal zero layer 110 according to an embodiment of the present invention; the manufacturing method of the active area metal zero layer 110 in the embodiment of the invention comprises the following steps:
step one, as shown in fig. 2A, a semiconductor substrate 101 is provided after the front-end process is completed, a gate structure 103 is formed on the semiconductor substrate 101, and an interlayer film 106 is filled in a spacer of the gate structure 103.
In the embodiment of the present invention, a drain region and a source region are formed in the semiconductor substrate 101 at two sides of the gate structure 103, and in fig. 2A, the source region and the drain region are symmetrically disposed at two sides of the gate structure 103 and are composed of a source drain region 102. Typically, an embedded epitaxial layer is also formed in the source drain region 102.
The semiconductor substrate 101 includes a silicon substrate.
A fin body is also formed on the semiconductor substrate 101. The fin body is formed by performing patterned etching on the semiconductor substrate 101, and the cross-sectional view of fig. 2A is a cross-sectional view along the length direction of the fin body.
The gate structure 103 is formed by stacking a gate dielectric layer and a gate conductive material layer.
The gate dielectric layer includes a high dielectric constant layer 1031 and the gate conductive material layer includes a metal gate.
The metal gate includes a metal work function layer 1032 and a metal conductive material layer 1034. Typically, there is also an interfacial layer between the high dielectric constant layer 1031 and the semiconductor substrate 101, a bottom barrier layer at the bottom of the high dielectric constant layer 1031, and a top barrier layer between the metal work function layer 1032 and the metal conductive material layer 1034.
The interlayer film 106 is also covered on the top surface of the gate structure 103.
In addition, the material of the metal conductive material layer 1034 includes tungsten or aluminum. Typically, the metal gate is formed using a gate-last (gate-last) process. After the metal gate is formed, it is further necessary to etch back the metal gate, and form a top dielectric layer 107 on top of the etched back metal gate, where the material of the top dielectric layer 107 is typically silicon nitride.
An etch stop layer 105 is further formed on the outer surface of the semiconductor substrate 101 outside the gate structure 103, and the etch stop layer 105 is typically silicon nitride.
Step two, as shown in fig. 2B, the formation region of the active region metal zero layer 110 is defined by photolithography.
In the embodiment of the present invention, the active area metal zero layer 110 is formed on the top of the drain area and the source area, and the active area metal zero layer 110 needs to form good contact with the drain area and the source area.
The photolithography definition of the second step ensures that a short circuit does not occur between the first middle connecting groove 108a and the gate structure 103 after the etching of the subsequent third step is completed.
Step three, as shown in fig. 2B, etching the interlayer film 106 in the formation region of the active region metal zero layer 110 to form a first middle connection groove 108a.
In the embodiment of the present invention, etching of the interlayer film 106 is stopped on the etching stop layer 105. Thereafter, as shown in fig. 2C, the etching stop layer 105 is further etched to expose the surface of the source drain region 102 at the bottom.
Step four, as shown in fig. 2D, performing pretreatment before metal filling by using inert gas bombardment and plasma cleaning, and using the pretreatment before metal filling to enlarge the size of the first middle section connecting groove 108 and finally control the size and the shape of the first middle section connecting groove 108. In fig. 2D, the first intermediate connecting slot after the pre-treatment prior to the metal filling is individually identified by reference numeral 108.
In the embodiment of the present invention, the pre-metal filling pretreatment increases the top opening of the first middle connecting groove 108a, and the pre-metal filling pretreatment is required to ensure that the final size and morphology of the first middle connecting groove 108a can not generate voids or hollows in the metal filling in the subsequent step five. At the same time, the pre-metal-fill pretreatment requirement ensures that the bottom area of the first middle-stage connecting trench 108a increases to reduce the contact resistance of the active region metal zero layer 110 and active region to a desired value.
Step five, as shown in fig. 2F, the first middle connecting groove 108 is filled with metal to form the active area metal zero layer 110.
In an embodiment of the present invention, the metal material of the active area metal zero layer 110 includes tungsten.
As shown in fig. 2E, before forming tungsten, a step of forming a Ti layer and a TiN layer 109 is further included.
After the step three is completed and before the step four is performed, the method further comprises the following steps:
a second middle connection groove (not shown) passing through the interlayer film 106 on top of the gate structure 103 is formed on top of the gate structure 103 using a photolithography and etching process.
And step four, the pretreatment before metal filling also carries out treatment on the second middle section connecting groove.
And fifthly, filling metal in the second middle section connecting groove and forming a gate connecting metal zero layer.
The fifth step comprises the following sub-steps:
the deposited metal completely fills the first and second middle connecting grooves 108a and extends outside the first and second middle connecting grooves 108a and 108.
And performing a metal chemical mechanical polishing process to remove metal outside the first middle section connecting groove 108a and the second middle section connecting groove.
In the embodiment of the invention, the size and the shape of the first middle section connecting groove 108a which is the middle section connecting groove at the top of the active region such as the source region or the drain region are not directly determined through the photoetching and etching process, but the first middle section connecting groove 108a with smaller size is formed by adopting the photoetching and etching process, so that the first middle section connecting groove 108a and the grid electrode can be well prevented from being shorted; after that, the first middle connecting groove 108a is pretreated before metal filling, that is, pretreatment before metal filling is performed, and the pretreatment before metal filling combines inert gas bombardment and plasma cleaning, so that not only can the treatment of pollutants in the etching process of the first middle connecting groove 108a be realized, but also the size of the first middle connecting groove 108a can be enlarged, and the appearance of reduced top necking can be formed, therefore, the size and the appearance of the middle connecting groove can be well controlled, the filling performance of the metal zero layer 110 of the active area can be improved, filling defects such as gaps or hollows can be prevented, short circuits between the metal zero layer 110 of the active area and a grid can be prevented, the contact area between the metal zero layer 110 of the active area and the active area can be prevented from being too small, and the contact resistance can be reduced.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (10)
1. The manufacturing method of the active area metal zero layer is characterized by comprising the following steps of:
step one, providing a semiconductor substrate with a front-end process, wherein a grid structure is formed on the semiconductor substrate, and an interlayer film is filled in a spacing region of the grid structure;
the top surface of the gate structure is also covered with the interlayer film;
step two, photoetching to define a forming area of the active area metal zero layer;
the photoetching definition of the second step ensures that short circuit does not occur between the first middle section connecting groove and the grid structure after the etching of the third step is completed;
step three, etching the interlayer film of the forming area of the active area metal zero layer to form a first middle connecting groove;
step four, carrying out pretreatment before metal filling by adopting inert gas bombardment and plasma cleaning, and enlarging the size of the first middle section connecting groove and finally controlling the size and the shape of the first middle section connecting groove by utilizing the pretreatment before metal filling;
the pre-metal filling pretreatment can increase the top opening of the first middle section connecting groove, and the pre-metal filling pretreatment is required to ensure that the final size and morphology of the first middle section connecting groove can not generate pores or hollows in the metal filling in the subsequent step five;
the pretreatment before metal filling is required to ensure that the bottom area of the first middle section connecting groove is increased to reduce the contact resistance of the active area metal zero layer and the active area to a required value;
filling metal in the first middle section connecting groove to form the active area metal zero layer;
after the step three is completed and before the step four is performed, the method further comprises the following steps:
forming a second middle section connecting groove penetrating through the interlayer film at the top of the grid structure by adopting a photoetching and etching process;
in the fourth step, the pretreatment before metal filling also carries out treatment on the second middle section connecting groove;
and fifthly, filling metal in the second middle section connecting groove and forming a gate connecting metal zero layer.
2. The method of manufacturing an active area metal zero layer of claim 1, wherein: in the first step, a drain region and a source region are formed in the semiconductor substrate at two sides of the gate structure, and the active region metal zero layer is formed and contacted at the tops of the drain region and the source region.
3. The method of manufacturing an active area metal zero layer according to claim 2, wherein: in the fifth step, the metal material of the active area metal zero layer includes tungsten.
4. A method of fabricating an active area metal zero layer as claimed in claim 3, wherein: in the fifth step, before forming tungsten, a step of forming a Ti layer and a TiN layer is further included.
5. The method of manufacturing an active area metal zero layer of claim 1, wherein: in step one, the semiconductor substrate comprises a silicon substrate.
6. The method of manufacturing an active area metal zero layer according to claim 5, wherein: a fin is also formed on the semiconductor substrate.
7. The method of manufacturing an active area metal zero layer of claim 1, wherein: the grid structure is formed by laminating a grid dielectric layer and a grid conductive material layer.
8. The method of manufacturing an active area metal zero layer of claim 7, wherein: the gate dielectric layer comprises a high dielectric constant layer and the gate conductive material layer comprises a metal gate.
9. The method of manufacturing an active area metal zero layer of claim 8, wherein: the metal gate includes a metal work function layer and a metal conductive material layer.
10. The method of manufacturing an active area metal zero layer of claim 1, wherein: the fifth step comprises the following sub-steps:
depositing metal to completely fill the first middle section connecting groove and the second middle section connecting groove, wherein the metal also extends to the outside of the first middle section connecting groove and the second middle section connecting groove;
and performing a metal chemical mechanical polishing process to remove metal outside the first middle section connecting groove and the second middle section connecting groove.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000003922A (en) * | 1998-06-30 | 2000-01-25 | 김영환 | Method for forming a contact hole of semiconductor devices |
| CN1725511A (en) * | 2004-05-24 | 2006-01-25 | 三星Sdi株式会社 | Semiconductor device and method of fabricating the same |
| CN108400109A (en) * | 2018-02-07 | 2018-08-14 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of contact hole |
| CN112017963A (en) * | 2019-05-31 | 2020-12-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| KR100571658B1 (en) * | 2003-11-21 | 2006-04-17 | 주식회사 하이닉스반도체 | Method for fabrication of semiconductor device |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000003922A (en) * | 1998-06-30 | 2000-01-25 | 김영환 | Method for forming a contact hole of semiconductor devices |
| CN1725511A (en) * | 2004-05-24 | 2006-01-25 | 三星Sdi株式会社 | Semiconductor device and method of fabricating the same |
| CN108400109A (en) * | 2018-02-07 | 2018-08-14 | 上海华虹宏力半导体制造有限公司 | The manufacturing method of contact hole |
| CN112017963A (en) * | 2019-05-31 | 2020-12-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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