CN113516935B

CN113516935B - Source electrode driving circuit and detection method thereof, display device and driving method thereof

Info

Publication number: CN113516935B
Application number: CN202010272169.8A
Authority: CN
Inventors: 朱学辉; 张俊瑞; 王志东; 周丽佳; 彭析竹; 项欣; 刘小乔
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2020-04-09
Filing date: 2020-04-09
Publication date: 2023-12-19
Anticipated expiration: 2040-04-09
Also published as: CN113516935A

Abstract

The invention discloses a source electrode driving circuit, a detection method thereof, a display device and a driving method thereof, wherein a control circuit is configured to output a trigger signal according to signals of an enabling end, a gating end, a kth counting output end and an Nth counting output end; the data output counter is configured to enable the 1 st counting output end to the N th counting output end to sequentially output a counting control signal according to the trigger signal; the signal generating circuit is configured to sequentially output data control signals from a plurality of generating output terminals of the signal generating circuit according to the count control signals output from the 1 st count output terminal to the nth count output terminal; the data processing output circuit is configured to receive the data signal to be displayed and the data control signal, and output the data signal to the data input terminal of the display panel through the data output end according to the data control signal after processing the data signal to be displayed.

Description

Source electrode driving circuit and detection method thereof, display device and driving method thereof

Technical Field

The present invention relates to the field of circuit technologies, and in particular, to a source driving circuit, a detection method thereof, a display device and a driving method thereof.

Background

The display device includes a display panel, a source driving circuit, and a gate driving circuit. Wherein, the display panel is provided with crisscross grid lines and data lines, thin film transistors and pixel electrodes. The grid line is connected with the grid driving circuit, the data line is connected with the source driving circuit, the grid of the thin film transistor is connected with the grid line, the source is connected with the data line, and the drain is connected with the pixel electrode. The grid driving circuit scans the grid lines line by line so as to enable the thin film transistors to be turned on line by line; meanwhile, the source electrode driving circuit outputs data signals to all the data lines at the same time, the data signals are transmitted to the source electrodes of the turned-on thin film transistors through the data lines and are loaded onto the pixel electrodes through the drain electrodes of the thin film transistors, so that the pixel electrodes are charged, and the display panel achieves a display function.

In practical applications, in order to determine the quality of the source driving circuit, it is generally necessary to detect the source driving circuit. However, the method of detecting the source driving circuit generally takes a long time, resulting in a waste of time.

Disclosure of Invention

The embodiment of the invention provides a source electrode driving circuit, a detection method thereof, a display device and a driving method thereof, which are used for detecting the source electrode driving circuit and reducing the time used for detection.

The embodiment of the invention provides a source electrode driving circuit, which comprises: a control circuit, a data output counter, a signal generation circuit, and a data processing output circuit; the data output counter is provided with a plurality of counting output ends, wherein the plurality of counting output ends comprise 1 st counting output ends to N th counting output ends which are sequentially arranged; wherein N is an integer greater than 1;

the control circuit is electrically connected with the enabling end, the gating end, the kth counting output end, the Nth counting output end and the data output counter respectively, and is configured to output a trigger signal to the data output counter according to signals of the enabling end, the gating end, the kth counting output end and the Nth counting output end; wherein k is an integer and 1< k < N;

the data output counter is configured to enable the 1 st counting output end to the N th counting output end to sequentially output a counting control signal according to the trigger signal;

the signal generating circuit is configured to receive the count control signals output from the 1 st count output end to the nth count output end, and enable a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the count control signals output from the 1 st count output end to the nth count output end;

The data processing output circuit is configured to receive a data signal to be displayed and the data control signal, and output the data signal to the data input terminal of the display panel through the data output end according to the data control signal after processing the data signal to be displayed.

Optionally, in an embodiment of the present invention, the control circuit includes: or gate and alternative selector;

the first input end of the OR gate is electrically connected with the enabling end, the second input end of the OR gate is electrically connected with the output end of the alternative selector, and the output end of the OR gate is electrically connected with the data output counter;

the control end of the two-out selector is electrically connected with the gating end, the first input end of the two-out selector is electrically connected with the Nth counting output end, and the second input end of the two-out selector is electrically connected with the kth counting output end.

Optionally, in an embodiment of the present invention, the data output counter includes a plurality of latches in cascade; wherein the output end of one latch is correspondingly and electrically connected with one counting output end;

the input end of the 1 st-stage latch is electrically connected with the control circuit and is configured to receive the trigger signal; in each two adjacent stages of latches, the input end of the latch of the next stage is electrically connected with the output end of the latch of the previous stage;

The control end of the latch of the odd number stage is electrically connected with the first clock signal end, and the control end of the latch of the even number stage is electrically connected with the second clock signal end.

Optionally, in an embodiment of the present invention, the signal generating circuit includes a plurality of switch circuits; wherein one of the switch circuits is correspondingly and electrically connected with one of the generating output ends; one counting output end is correspondingly and electrically connected with the control ends of at least two switching circuits;

the switching circuit is configured to output a data control signal through the generation output terminal of the electrical connection according to a count control signal of the count output terminal of the electrical connection.

Optionally, in an embodiment of the present invention, the plurality of switch circuits includes 1 st to 2N-th switch circuits sequentially arranged; the N-th counting output end is electrically connected with the control end of the 2N-1-th switching circuit and the control end of the 2N-th switching circuit, N is an integer and is more than or equal to 1 and less than or equal to N;

the input end of the 2n-1 switch circuit with the odd counting output end electrically connected is electrically connected with the third clock signal end, and the input end of the 2n switch circuit with the odd counting output end electrically connected is electrically connected with the second clock signal end;

The input end of the 2n-1 switch circuit with the even number of counting output ends electrically connected is electrically connected with the fourth clock signal end, and the input end of the 2n switch circuit with the even number of counting output ends electrically connected is electrically connected with the first clock signal end.

Optionally, in an embodiment of the present invention, the switching circuit includes: a transmission gate, a first inverter, a switching transistor, and a buffer;

the input end of the transmission gate is used as the input end of the switching circuit, the first control end of the transmission gate is electrically connected with the input end of the first inverter, the second control end of the transmission gate is electrically connected with the output end of the first inverter, and the output end of the transmission gate is electrically connected with the input end of the buffer;

the input end of the first inverter is used as the control end of the switching circuit, and the output end of the first inverter is electrically connected with the grid electrode of the switching transistor;

the source electrode of the switching transistor is electrically connected with the grounding end, and the drain electrode of the switching transistor is electrically connected with the input end of the buffer;

the output end of the buffer is electrically connected with the corresponding generating output end.

The embodiment of the invention also provides a detection method of the source electrode driving circuit, which comprises the following steps:

In a first detection mode, the control circuit outputs a trigger signal to the data output counter according to signals of the enabling end, the gating end and the Nth counting output end; the data output counter enables the 1 st counting output end to the N th counting output end to sequentially output a counting control signal according to the trigger signal; the signal generation circuit enables a plurality of generation output ends of the signal generation circuit to sequentially output data control signals according to the count control signals output from the 1 st count output end to the N th count output end; the data processing output circuit receives the data signal to be displayed and the data control signal, processes the data signal to be displayed, and outputs the processed data signal to each data input terminal of the display panel through a data output end according to the data control signal; the gating end loads a first gating signal;

in a second detection mode, the control circuit outputs a trigger signal to the data output counter according to signals of the enabling end, the gating end and the kth counting output end; the data output counter enables the 1 st counting output end to the k th counting output end to sequentially output a counting control signal according to the trigger signal; the signal generation circuit enables a plurality of generation output ends of the signal generation circuit to sequentially output data control signals according to the count control signals output from the 1 st count output end to the kth count output end; the data processing output circuit receives the data signal to be displayed and the data control signal, processes the data signal to be displayed, and outputs the processed data signal to the corresponding data input terminal in the display panel through a part of data output ends according to the data control signal; wherein the strobe terminal loads a second strobe signal.

The embodiment of the invention also provides a display device which comprises the source electrode driving circuit.

Optionally, in an embodiment of the present invention, the method further includes: a display panel and a gate driving circuit;

the display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of data input terminals; wherein, one of the data input terminals is correspondingly and electrically connected with at least one of the data lines;

the grid driving circuit is respectively and electrically connected with the grid lines;

the source electrode driving circuits are respectively and electrically connected with the data input terminals; wherein one of the data output terminals is electrically connected to one of the data input terminals.

The embodiment of the invention also provides a driving method of the display device, which comprises the following steps:

in a first display mode, the control circuit outputs a trigger signal to the data output counter according to signals of the enabling end, the gating end and the Nth counting output end; the data output counter enables the 1 st counting output end to the N th counting output end to sequentially output a counting control signal according to the trigger signal; the signal generation circuit enables a plurality of generation output ends of the signal generation circuit to sequentially output data control signals according to the count control signals output from the 1 st count output end to the N th count output end; the data processing output circuit receives the data signal to be displayed and the data control signal, and outputs the data signal to a data input terminal of the display panel through a data output end according to the data control signal after processing the data signal to be displayed; the grid driving circuit loads corresponding signals to the grid lines and controls the display panel to display images in a first display mode; the gating end loads a first gating signal;

In a second display mode, the control circuit outputs a trigger signal to the data output counter according to signals of the enabling end, the gating end and the kth counting output end; the data output counter enables the 1 st counting output end to the k th counting output end to sequentially output a counting control signal according to the trigger signal; the signal generation circuit enables a plurality of generation output ends of the signal generation circuit to sequentially output data control signals according to the count control signals output from the 1 st count output end to the kth count output end; the data processing output circuit receives the data signal to be displayed and the data control signal, and outputs the data signal to the corresponding data input terminal in the display panel through a part of data output end according to the data control signal after processing the data signal to be displayed; the grid driving circuit loads corresponding signals to the grid lines and controls the display panel to display images in a second display mode; wherein the strobe terminal loads a second strobe signal.

The invention has the following beneficial effects:

according to the source electrode driving circuit and the detection method thereof, when in the first detection mode, the control circuit can output the trigger signal to the data output counter according to the signals of the enabling end, the gating end and the Nth counting output end by loading the first gating signal to the gating end; the data output counter enables the 1 st counting output end to the N th counting output end to sequentially output counting control signals according to the trigger signals; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the N th counting output end; the data processing output circuit receives the data signal to be displayed and the data control signal, processes the data signal to be displayed, and outputs the processed data signal to the data input terminal of the display panel through the data output end according to the data control signal. Thus, each data input terminal can input data signals, each data line can input data signals, namely, one row of sub-pixels in the display panel can input signals, and further, the working state of the source driving circuit corresponding to each sub-pixel input signal in one row can be detected.

In addition, in the second detection mode, by loading a second gating signal on the gating end, the control circuit can output a trigger signal to the data output counter according to signals of the enabling end, the gating end and the kth counting output end; the data output counter enables the 1 st counting output end to the kth counting output end to sequentially output counting control signals according to the trigger signals; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the kth counting output end; the data processing output circuit receives the data signal to be displayed and the data control signal, processes the data signal to be displayed, and outputs the processed data signal to the data input terminal of the display panel through the data output end according to the data control signal. Therefore, only a part of data input terminals can be input with data signals, so that a part of data lines can be input with data signals, all the data input terminals are not required to be input with data signals, and then part of sub-pixel input signals in one row of the display panel can be switched to the next row of sub-pixels so that part of sub-pixel input signals in the next row can be detected for the working state of the source drive circuit when the corresponding row is switched.

In the display device and the driving method thereof provided by the embodiment of the invention, in a first display mode, a control circuit outputs a trigger signal to a data output counter according to signals of an enabling end, a gating end and an Nth counting output end; the data output counter enables the 1 st counting output end to the N th counting output end to sequentially output counting control signals according to the trigger signals; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the N th counting output end; the data processing output circuit receives the data signal to be displayed and the data control signal, and outputs the display data signal to the data input terminal of the display panel through the data output end according to the data control signal after processing the data signal to be displayed; the grid driving circuit loads corresponding signals to the grid lines and controls the display panel to display images in a first display mode. This allows the entire display area of the display panel to be displayed.

In the second display mode, the control circuit outputs a trigger signal to the data output counter according to signals of the enabling end, the gating end and the kth counting output end; the data output counter enables the 1 st counting output end to the kth counting output end to sequentially output counting control signals according to the trigger signals; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the kth counting output end; the data processing output circuit receives the data signal to be displayed and the data control signal, and outputs the display data signal to the corresponding data input terminal in the display panel through a part of data output end according to the data control signal after processing the data signal to be displayed; the grid driving circuit loads corresponding signals to the grid lines and controls the display panel to display images in a second display mode. This can cause a partial region in the display area of the display panel to display a picture, so that power consumption can be reduced.

Drawings

Fig. 1 is a schematic diagram of a source driving circuit and a display panel according to an embodiment of the invention;

fig. 2 is a schematic diagram of a specific structure of a source driving circuit according to an embodiment of the invention;

FIG. 3 is a schematic diagram of a specific structure of a switch circuit according to an embodiment of the present invention;

FIG. 4 is a flowchart of a method for detecting a source driver circuit according to an embodiment of the invention;

FIG. 5 is a timing diagram of signals according to an embodiment of the present invention;

FIG. 6 is a timing diagram of other signals according to an embodiment of the present invention;

fig. 7 is a schematic structural diagram of a display device according to an embodiment of the invention;

fig. 8 is a flowchart of a driving method of a display device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. And embodiments of the invention and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be made by a person skilled in the art without creative efforts, based on the described embodiments of the present invention fall within the protection scope of the present invention.

Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The terms "first," "second," and the like, as used herein, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

It should be noted that the dimensions and shapes of the figures in the drawings do not reflect true proportions, and are intended to illustrate the present invention only. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

The source driving circuit provided by the embodiment of the invention, as shown in fig. 1, may include: a control circuit 100, a data output counter 200, a signal generation circuit 300, and a data processing output circuit 400; the data output counter 200 has a plurality of count output ends, wherein the plurality of count output ends include 1 st count output end CNT-1 to N th count output end CNT-N arranged in sequence; where N is an integer greater than 1 (n=44 in fig. 1 as an example);

The control circuit 100 is electrically connected to the enable terminal EN, the strobe terminal CS, the kth count output terminal CNT-k, the nth count output terminal CNT-N, and the data output counter 200, respectively, and the control circuit 100 is configured to output a trigger signal to the data output counter 200 according to signals of the enable terminal EN, the strobe terminal CS, the kth count output terminal CNT-k, and the nth count output terminal CNT-N; wherein k is an integer and 1< k < N; (k=8 is taken as an example in fig. 1);

the data output counter 200 is configured to sequentially output count control signals from the 1 st count output terminal to the nth count output terminal CNT-N according to the trigger signal;

the signal generating circuit 300 is configured to receive the count control signals output from the 1 st to nth count output terminals CNT-N, and to cause the plurality of generation output terminals of the signal generating circuit 300 to sequentially output the data control signals according to the count control signals output from the 1 st to nth count output terminals CNT-N;

the data processing output circuit 400 is configured to receive a data signal to be displayed and a data control signal, and output the data signal to the data input terminal of the display panel 500 through the data output terminal according to the data control signal after processing the data signal to be displayed.

The source electrode driving circuit provided by the embodiment of the invention may include: control circuit, data output counter, signal generation circuit and data processing output circuit. In the first detection mode, by loading a first gating signal to the gating end, the control circuit can output a trigger signal to the data output counter according to signals of the enabling end, the gating end and the Nth counting output end; the data output counter enables the 1 st counting output end to the N th counting output end to sequentially output counting control signals according to the trigger signals; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the N th counting output end; the data processing output circuit receives the data signal to be displayed and the data control signal, processes the data signal to be displayed, and outputs the processed data signal to the data input terminal of the display panel through the data output end according to the data control signal. Thus, each data input terminal can input data signals, each data line can input data signals, namely, one row of sub-pixels in the display panel can input signals, and further, the working state of the source driving circuit corresponding to each sub-pixel input signal in one row can be detected.

In addition, in the source driving circuit provided by the embodiment of the invention, in the second detection mode, by loading the second gating signal on the gating end, the control circuit can output the trigger signal to the data output counter according to the signals of the enabling end, the gating end and the kth counting output end; the data output counter enables the 1 st counting output end to the kth counting output end to sequentially output counting control signals according to the trigger signals; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the kth counting output end; the data processing output circuit receives the data signal to be displayed and the data control signal, processes the data signal to be displayed, and outputs the processed data signal to the data input terminal of the display panel through the data output end according to the data control signal. Therefore, only a part of data input terminals can be input with data signals, so that a part of data lines can be input with data signals, all the data input terminals are not required to be input with data signals, and then part of sub-pixel input signals in one row of the display panel can be switched to the next row of sub-pixels so that part of sub-pixel input signals in the next row can be detected for the working state of the source drive circuit when the corresponding row is switched.

The present invention will be described in detail with reference to specific examples. The present embodiment is for better explaining the present invention, but not limiting the present invention.

In particular implementations, in embodiments of the present invention, k may be set to any of these values, 2 through N-1. For example, as shown in fig. 1 and 2, n=44, or n=50, or n=60, or n=80, or the like may be used. And k=8, or k=20, or k=30, or k=40, or the like may be used. Of course, in practical applications, the requirements of different display panels on the source driving circuit are different, so the values of N and k may be determined by design according to the requirements of practical applications, which is not limited herein.

In particular, in an embodiment of the present invention, as shown in fig. 1 and 2, the control circuit 100 may include: or gate 110 and one-out-of-two selector 120; wherein,

a first input terminal of the or gate 110 is electrically connected to the enable terminal EN, a second input terminal of the or gate 110 is electrically connected to an output terminal of the one-out-of-two selector 120, and an output terminal of the or gate 110 is electrically connected to the data output counter 200;

the control terminal of the one-out-of-two selector 120 is electrically connected to the gate terminal CS, the first input terminal of the one-out-of-two selector 120 is electrically connected to the nth count output terminal CNT-N, and the second input terminal of the one-out-of-two selector 120 is electrically connected to the kth count output terminal CNT-k.

In particular, in the embodiment of the present invention, the or gate 110 may have its output terminal output a low level when the signals input by the first input terminal and the second input terminal are both low. And, the or gate 110 may have its output terminal output a high level when a signal inputted from at least one of the first input terminal and the second input terminal thereof is a high level. It should be noted that, in practical applications, the structure and the working principle of the or gate 110 may be substantially the same as those in the related art, and will not be described herein.

In particular implementations, in embodiments of the present invention, as shown in FIGS. 1 and 2, the data output counter 200 may include a plurality of latches SK-1, SK-2, … … SK-8, … … SK-N-1, SK-N in cascade; wherein, the output end Q of one latch SK-n is correspondingly and electrically connected with one counting output end CNT-n; and N is an integer and N is 1-N. And, an input D of the 1 st stage latch SK-1 is electrically connected to the control circuit 100 and is configured to receive a trigger signal, i.e. the input D of the 1 st stage latch SK-1 is electrically connected to an output of the OR gate 110. In each two adjacent stages of latches, the input end D of the next stage of latch SK-n+1 is electrically connected with the output end Q of the previous stage of latch SK-n; the control terminal C of the latch of the odd-numbered stage is electrically connected with the first clock signal terminal CK1, and the control terminal C of the latch of the even-numbered stage is electrically connected with the second clock signal terminal CK 2.

In a specific implementation, in the embodiment of the present invention, when the control terminal C of the latch is at a high level, the output terminal Q of the latch may be changed along with the input terminal D, that is, the level of the output terminal Q and the level of the input terminal D may be the same. When its control terminal C changes from high to low, the output terminal Q remains in the previous state until the next time the control terminal C changes to high. It should be noted that, in practical application, the structure and the working principle of the latch may be substantially the same as those in the related art, and will not be described herein.

In particular implementations, in embodiments of the present invention, as shown in FIGS. 1 and 2, the signal generation circuit 300 may include a plurality of switching circuits TK-z (z is an integer and 1.ltoreq.z.ltoreq.2N); wherein, a switch circuit is correspondingly and electrically connected with a generating output end; and one counting output end is correspondingly and electrically connected with the control ends of the at least two switching circuits. And the switching circuit is configured to output the data control signal through the electrically connected generation output terminal according to the count control signal of the electrically connected count output terminal.

Illustratively, in a specific implementation, in an embodiment of the present invention, as shown in fig. 1 and 2, the plurality of switching circuits may include 1 st to 2 nth switching circuits TK-1 to TK-2N arranged in sequence; wherein the N-th counting output end CNT-N is electrically connected with the control end S of the 2N-1-th switching circuit TK-2N-1 and the control end S of the 2N-th switching circuit TK-2N. And, the output KO of the 2n-1 th switching circuit TK-2n-1 is electrically connected with the 2n-1 st generation output CTRL-2n-1, and the output KO of the 2 n-th switching circuit TK-2n is electrically connected with the 2 n-th generation output CTRL-2 n. And N is an integer and N is 1-N.

And, the input end IN of the 2n-1 th switching circuit TK-2n-1 electrically connected to the odd numbered counting output end is electrically connected to the third clock signal end CK3, and the input end IN of the 2 n-th switching circuit TK-2n electrically connected to the odd numbered counting output end is electrically connected to the second clock signal end CK 2. For example, the input terminal IN of the 1 st switching circuit TK-1 to which the 1 st count output terminal CNT-1 is electrically connected, the input terminal IN of the 5 th switching circuit TK-5 to which the 3 rd count output terminal CNT-3 is electrically connected, and the input terminal IN of the 9 th switching circuit TK-9 to which the 5 th count output terminal CNT-5 is electrically connected are all electrically connected to the third clock signal terminal CK 3. The same applies to the rest, and so on, and will not be described in detail herein.

And, the input terminal IN of the 2 n-th switching circuit TK-2n, to which the odd-numbered count output terminal is electrically connected, is electrically connected to the second clock signal terminal CK 2. For example, the input IN of the 2 nd switching circuit TK-2, to which the 1 st count output CNT-1 is electrically connected, the input IN of the 6 th switching circuit TK-6, to which the 3 rd count output CNT-3 is electrically connected, and the input IN of the 10 th switching circuit TK-10, to which the 5 th count output CNT-5 is electrically connected, are all electrically connected to the second clock signal terminal CK 2. The same applies to the rest, and so on, and will not be described in detail herein.

And, the input terminal IN of the 2n-1 th switching circuit TK-2n-1, to which the even number of count output terminals are electrically connected, is electrically connected to the fourth clock signal terminal CK 4. For example, the input IN of the 3 rd switching circuit TK-3, to which the 2 nd count output CNT-2 is electrically connected, the input IN of the 7 th switching circuit TK-7, to which the 4 th count output CNT-4 is electrically connected, and the input IN of the 11 th switching circuit TK-11, to which the 6 th count output CNT-6 is electrically connected, are all electrically connected to the fourth clock signal terminal CK 4. The same applies to the rest, and so on, and will not be described in detail herein.

And, the input terminal IN of the 2 n-th switching circuit TK-2n, to which the even-numbered count output terminals are electrically connected, is electrically connected to the first clock signal terminal CK 1. For example, the input IN of the 4 th switching circuit TK-4 to which the 2 nd count output CNT-2 is electrically connected, the input IN of the 8 th switching circuit TK-8 to which the 4 th count output CNT-4 is electrically connected, and the input IN of the 12 th switching circuit TK-12 to which the 6 th count output CNT-6 is electrically connected are all electrically connected to the first clock signal terminal CK 1. The same applies to the rest, and so on, and will not be described in detail herein.

In particular, in an embodiment of the present invention, as shown in FIGS. 2 and 3, the switching circuit TK-z (z is an integer and 1.ltoreq.z.ltoreq.2N) may include: a transmission gate TM, a first inverter N1, a switching transistor M0, and a buffer H0; the input end of the transmission gate TM is used as an input end of the switching circuit (i.e., the input end of the transmission gate TM is electrically connected with the input end IN of the switching circuit), the first control end of the transmission gate TM is electrically connected with the input end of the first inverter N1, the second control end of the transmission gate TM is electrically connected with the output end of the first inverter N1, and the output end of the transmission gate TM is electrically connected with the input end of the buffer H0. The input terminal of the first inverter N1 serves as a control terminal of the switching circuit (i.e., the input terminal of the first inverter N1 is electrically connected to the control terminal S of the switching circuit), and the output terminal of the first inverter N1 is electrically connected to the gate of the switching transistor M0. The source of the switching transistor M0 is electrically connected to the ground GND, and the drain of the switching transistor M0 is electrically connected to the input terminal of the buffer H0. The output of the buffer H0 is electrically connected to the corresponding generation output, i.e. the output of the buffer H0 serves as the output KO of the switching circuit.

In particular, in the embodiment of the present invention, the transmission gate TM outputs the signal of its input terminal through its output terminal when its first input terminal is at a low level and its second input terminal is at a high level. It should be noted that, in practical application, the structure and the working principle of the transmission gate TM may be substantially the same as those in the related art, and will not be described herein.

In a specific implementation, in the embodiment of the present invention, the first inverter N1 may invert the signal input to its input terminal and output the signal through its output terminal. It should be noted that, in practical applications, the structure and the working principle of the first inverter N1 may be substantially the same as those of the inverter in the related art, which is not described herein.

In particular embodiments, the buffer H0 may include an even number of second inverters in embodiments of the present invention. Wherein the even number of second inverters are sequentially arranged in series. For example, as shown in fig. 3, the buffer H0 may include 2 second inverters N2-1, N2-2. The input end of the second inverter N2-1 is electrically connected with the output end of the transmission gate TM, the output end of the second inverter N2-1 is electrically connected with the input end of the second inverter N2-2, and the output end of the second inverter N2-1 is used as the output end of the buffer H0, namely, the output end of the second inverter N2-2 is electrically connected with the output end KO of the switching circuit TK-z.

The above is merely illustrative of a specific structure of the source driving circuit provided in the embodiments of the present disclosure, and the specific structure is not limited to the above structure provided in the embodiments of the present disclosure in the specific implementation, but may be other structures known to those skilled in the art, and is not limited herein.

Based on the same inventive concept, the embodiment of the present invention further provides a method for detecting the source driving circuit, as shown in fig. 4, which may include the following steps:

s401, in a first detection mode, the control circuit outputs a trigger signal to the data output counter according to signals of an enabling end, a gating end and an Nth counting output end; the data output counter enables the 1 st counting output end to the N th counting output end to sequentially output counting control signals according to the trigger signals; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the N th counting output end; the data processing output circuit receives the data signal to be displayed and the data control signal, processes the data signal to be displayed, and outputs the processed data signal to each data input terminal of the display panel through the data output end according to the data control signal; the gating end loads a first gating signal;

S402, in a second detection mode, the control circuit outputs a trigger signal to the data output counter according to signals of the enabling end, the gating end and the kth counting output end; the data output counter enables the 1 st counting output end to the kth counting output end to sequentially output counting control signals according to the trigger signals; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the kth counting output end; the data processing output circuit receives the data signal to be displayed and the data control signal, processes the data signal to be displayed, and outputs the processed data signal to the corresponding data input terminal in the display panel through part of the data output end according to the data control signal; wherein the strobe terminal loads the second strobe signal.

The following describes a detection method of the source driving circuit according to an embodiment of the present invention with reference to timing diagrams shown in fig. 1, 2, 5 and 6. Where n=44 and k=8 are taken as an example. Wherein CK1 represents the signal CK1 of the first clock signal terminal CK1, CK2 represents the signal CK2 of the second clock signal terminal CK2, CK3 represents the signal CK3 of the third clock signal terminal CK3, CK4 represents the signal CK4 of the fourth clock signal terminal CK4, EN represents the signal of the enable terminal EN, CNT-1 to CNT-N represent the count control signals of the 1 st to nth count output terminals CNT-1 to CNT-N, CTRL-1 to CTRL-2N represent the data control signals of the 1 st to 2 nd generation output terminals CTRL-1 to CTRL-2N.

Referring to fig. 1, fig. 2, and fig. 5, in a first detection mode, the detection method of the source driving circuit according to the embodiment of the present invention may include the following steps:

in the first detection mode, in the TF0 stage, the gate terminal CS is loaded with the first gate signal at the low level, so that the alternative selector 120 inputs the signal of the 44 th count output terminal CNT-44 to the second input terminal of the or gate 110, which enables the or gate 110 to input the trigger signal to the input terminal D of the 1 st stage latch SK-1 under the common control of the signals of the second input terminal and the enable terminal EN, and the 1 st stage latch SK-1 outputs the corresponding count control signal CNT-1 under the control of the signal CK1 of the first clock signal terminal CK 1. The input terminal IN of the 1 st switching circuit TK-1 receives the signal CK3 of the third clock signal terminal CK3, and the 1 st switching circuit TK-1 outputs a high-level signal of the third clock signal terminal CK3 to the 1 st generation output terminal CTRL-1 under the control of the count control signal CNT-1 output from the 1 st count output terminal CNT-1, so that the 1 st generation output terminal CTRL-1 outputs the data control signal CTRL-1. And the input terminal IN of the 2 nd switching circuit TK-2 receives the signal CK2 of the second clock signal terminal CK2, and the 2 nd switching circuit TK-2 outputs a high-level signal of the second clock signal terminal CK2 to the 2 nd generation output terminal CTRL-2 under the control of the count control signal CNT-1 output from the 1 st count output terminal CNT-1, so that the 2 nd generation output terminal CTRL-2 outputs the data control signal CTRL-2.

And, the count control signal CNT-1 of the 1 st count output terminal CNT-1 is inputted to the input terminal D of the 2 nd stage latch SK-2, and the 2 nd stage latch SK-2 makes the 2 nd count output terminal CNT-2 output the count control signal CNT-2 under the control of the signal CK2 of the second clock signal terminal CK 2. The input terminal IN of the 3 rd switching circuit TK-3 receives the signal CK4 of the fourth clock signal terminal CK4, and the 3 rd switching circuit TK-3 outputs a high-level signal of the fourth clock signal terminal CK4 to the 3 rd generation output terminal CTRL-3 under the control of the count control signal CNT-2 output from the 2 nd count output terminal CNT-2, so that the 3 rd generation output terminal CTRL-3 outputs the data control signal CTRL-3. And the input terminal IN of the 4 th switching circuit TK-4 receives the signal CK1 of the first clock signal terminal CK1, and the 4 th switching circuit TK-4 outputs a high-level signal of the first clock signal terminal CK1 to the 4 th generation output terminal CTRL-4 under the control of the count control signal CNT-2 output from the 2 nd count output terminal CNT-2, so that the 4 th generation output terminal CTRL-4 outputs the data control signal CTRL-4.

The rest are the same, and so on, and are not described in detail herein.

The count control signal CNT-43 of the 43 rd count output terminal CNT-43 is input to the input terminal D of the 44 th stage latch SK-44, and the 44 th stage latch SK-44 makes the 44 th count output terminal CNT-44 output the count control signal CNT-44 under the control of the signal CK2 of the second clock signal terminal CK 2. The input terminal IN of the 87 th switching circuit TK-87 receives the signal CK4 of the fourth clock signal terminal CK4, and the 87 th switching circuit TK-87 outputs a signal of a high level of the fourth clock signal terminal CK4 to the 87 th generation output terminal CTRL-87 under the control of the count control signal CNT-44 output from the 44 th count output terminal CNT-44, so that the 87 th generation output terminal CTRL-87 outputs the data control signal CTRL-87. And the input terminal IN of the 88 th switching circuit TK-88 receives the signal CK1 of the first clock signal terminal CK1, and the 88 th switching circuit TK-88 outputs a high level signal of the first clock signal terminal CK1 to the 88 th generation output terminal CTRL-88 under the control of the count control signal CNT-44 output from the 44 th count output terminal CNT-44, so that the 88 th generation output terminal CTRL-88 can output the data control signal CTRL-88.

And, the data processing output circuit 400 receives the data signal to be displayed and the data control signals ctrl-1 to ctrl-88, and outputs the data signal to be displayed to each data input terminal 540 of the display panel 500 through the data output terminals CO-1 to CO-88 according to the data control signals ctrl-1 to ctrl-88 after processing the data signal to be displayed. In this way, signals can be input to each of the sub-pixels in one row of the display panel 500, so that the operating state of the source driving circuit when signals are input to the sub-pixels in one row can be detected.

Referring to fig. 1, fig. 2, and fig. 6, in a second detection mode, the detection method of the source driving circuit according to the embodiment of the present invention may include the following steps:

in the second detection mode, in the TF1 stage, the strobe terminal CS is loaded with the high-level second strobe signal, so that the alternative selector 120 inputs the signal of the 8 th count output terminal CNT-8 to the second input terminal of the or gate 110, which enables the or gate 110 to input the trigger signal to the input terminal D of the 1 st stage latch SK-1 under the common control of the signals of the second input terminal and the enable terminal EN, and the 1 st stage latch SK-1 outputs the corresponding count control signal CNT-1 under the control of the signal CK1 of the first clock signal terminal CK 1. The input terminal IN of the 1 st switching circuit TK-1 receives the signal CK3 of the third clock signal terminal CK3, and the 1 st switching circuit TK-1 outputs a high-level signal of the third clock signal terminal CK3 to the 1 st generation output terminal CTRL-1 under the control of the count control signal CNT-1 output from the 1 st count output terminal CNT-1, so that the 1 st generation output terminal CTRL-1 outputs the data control signal CTRL-1. And the input terminal IN of the 2 nd switching circuit TK-2 receives the signal CK2 of the second clock signal terminal CK2, and the 2 nd switching circuit TK-2 outputs a high-level signal of the second clock signal terminal CK2 to the 2 nd generation output terminal CTRL-2 under the control of the count control signal CNT-1 output from the 1 st count output terminal CNT-1, so that the 2 nd generation output terminal CTRL-2 outputs the data control signal CTRL-2.

The rest are the same, and so on, and are not described in detail herein.

The count control signal CNT-7 of the 7 th count output terminal CNT-7 is input to the input terminal D of the 8 th stage latch SK-8, and the 8 th stage latch SK-8 causes the 8 th count output terminal CNT-8 to output the count control signal CNT-8 under the control of the signal CK2 of the second clock signal terminal CK 2. The input terminal IN of the 15 th switching circuit TK-15 receives the signal CK4 of the fourth clock signal terminal CK4, and the 15 th switching circuit TK-15 outputs a high-level signal of the fourth clock signal terminal CK4 to the 15 th generation output terminal CTRL-15 under the control of the count control signal CNT-8 output from the 8 th count output terminal CNT-8, so that the 15 th generation output terminal CTRL-15 outputs the data control signal CTRL-15. And the input terminal IN of the 16 th switching circuit TK-16 receives the signal CK1 of the first clock signal terminal CK1, and the 16 th switching circuit TK-16 outputs a high-level signal of the first clock signal terminal CK1 to the 16 th generation output terminal CTRL-16 under the control of the count control signal CNT-8 output from the 8 th count output terminal CNT-8, so that the 16 th generation output terminal CTRL-16 outputs the data control signal CTRL-16.

And, the data processing output circuit 400 receives the data signal to be displayed and the data control signals ctrl-1 to ctrl-16, and outputs the data signal to the corresponding data input terminal of the display panel 500 through the 16 data output terminals CO-1 to CO-16 according to the data control signals ctrl-1 to ctrl-16 after processing the data signal to be displayed, so that signals can be input to a part of the sub-pixels in a row of the sub-pixels in the display panel 500.

Thereafter, the TF2 phase is entered. In the TF2 stage, the strobe terminal CS is loaded with the high-level second strobe signal, so that the one-out-of-two selector 120 inputs the signal of the 8 th count output terminal CNT-8 to the second input terminal of the or gate 110, which enables the or gate 110 to input the trigger signal to the input terminal D of the 1 st stage latch SK-1 under the common control of the signals of the second input terminal and the enable terminal EN, and the 1 st stage latch SK-1 outputs the corresponding count control signal CNT-1 to the 1 st count output terminal CNT-1 under the control of the signal CK1 of the first clock signal terminal CK 1. The input terminal IN of the 1 st switching circuit TK-1 receives the signal CK3 of the third clock signal terminal CK3, and the 1 st switching circuit TK-1 outputs a high-level signal of the third clock signal terminal CK3 to the 1 st generation output terminal CTRL-1 under the control of the count control signal CNT-1 output from the 1 st count output terminal CNT-1, so that the 1 st generation output terminal CTRL-1 outputs the data control signal CTRL-1. And the input terminal IN of the 2 nd switching circuit TK-2 receives the signal CK2 of the second clock signal terminal CK2, and the 2 nd switching circuit TK-2 outputs a high-level signal of the second clock signal terminal CK2 to the 2 nd generation output terminal CTRL-2 under the control of the count control signal CNT-1 output from the 1 st count output terminal CNT-1, so that the 2 nd generation output terminal CTRL-2 outputs the data control signal CTRL-2.

The rest are the same, and so on, and are not described in detail herein.

And, the data processing output circuit 400 receives the data signal to be displayed and the data control signals ctrl-1 to ctrl-16, and outputs the data signal to the corresponding data input terminal of the display panel 500 through the 16 data output terminals CO-1 to CO-16 according to the data control signals ctrl-1 to ctrl-16 after processing the data signal to be displayed, so that signals can be input to a part of the sub-pixels in another row of the sub-pixels in the display panel 500.

In this way, the source driving circuit can switch to the next row of subpixels after inputting signals to a part of subpixels in one row of the display panel 500, so that the part of subpixels in the next row can input signals, and the operating state of the source driving circuit when the corresponding row is switched from row to row can be detected.

Based on the same inventive concept, the embodiment of the invention also provides a display device, which comprises the source electrode driving circuit. The principle of the display device for solving the problems is similar to that of the source driving circuit, so the implementation of the display device can be referred to the implementation of the source driving circuit, and the repetition is omitted herein.

In specific implementation, in an embodiment of the present invention, as shown in fig. 1 and fig. 7, the display device may further include: a display panel 500 and a gate driving circuit 530. The display panel 500 includes a plurality of gate lines 520, a plurality of data lines 510, and a plurality of data input terminals 540. The gate driving circuits 530 are electrically connected to the gate lines 520, respectively. The source driving circuits 550 are electrically connected to the data input terminals 540, respectively.

The display panel 500 is provided with a plurality of pixel units, and a plurality of sub-pixels are disposed in the pixel units. For example, red, green, and blue sub-pixels. Illustratively, a thin film transistor and a pixel electrode are disposed in the subpixel. The grid line is connected with the grid driving circuit, the data line is connected with the source driving circuit, the grid of the thin film transistor is connected with the grid line, the source is connected with the data line, and the drain is connected with the pixel electrode. Illustratively, the gate driving circuit scans the gate lines row by row to turn on the thin film transistors row by row; meanwhile, the source electrode driving circuit outputs data signals to all the data lines at the same time, the data signals are transmitted to the source electrodes of the turned-on thin film transistors through the data lines and are loaded onto the pixel electrodes through the drain electrodes of the thin film transistors, so that the pixel electrodes are charged, and the display panel achieves a display function.

In particular embodiments of the present invention, one data input terminal may be electrically connected to at least one data line, and one data output terminal may be electrically connected to one data input terminal. Illustratively, as shown in fig. 7, one data input terminal may be electrically connected to one data line correspondingly, and one data output terminal may be electrically connected to one data input terminal.

It should be noted that, the structure of the source driving circuit in the display device according to the embodiment of the present invention may be referred to the above description, and will not be repeated here.

In a specific implementation, in an embodiment of the present invention, the display device may be: any product or component with display function such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. Other essential components of the display device will be understood by those skilled in the art, and are not described herein in detail, nor should they be considered as limiting the invention.

Based on the same inventive concept, the embodiment of the present invention further provides a driving method of a display device, as shown in fig. 8, which may include the following steps:

s810, in a first display mode, the control circuit outputs a trigger signal to the data output counter according to signals of an enabling end, a gating end and an Nth counting output end; the data output counter enables the 1 st counting output end to the N th counting output end to sequentially output counting control signals according to the trigger signals; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the N th counting output end; the data processing output circuit receives the data signal to be displayed and the data control signal, and outputs the display data signal to the data input terminal of the display panel through the data output end according to the data control signal after processing the data signal to be displayed; the grid driving circuit loads corresponding signals to the grid lines and controls the display panel to display images in a first display mode; the gating end loads a first gating signal;

S820, in the second display mode, the control circuit outputs a trigger signal to the data output counter according to signals of the enabling end, the gating end and the kth counting output end; the data output counter enables the 1 st counting output end to the kth counting output end to sequentially output counting control signals according to the trigger signals; the signal generating circuit enables a plurality of generating output ends of the signal generating circuit to sequentially output data control signals according to the counting control signals output from the 1 st counting output end to the kth counting output end; the data processing output circuit receives the data signal to be displayed and the data control signal, and outputs the display data signal to the corresponding data input terminal in the display panel through a part of data output end according to the data control signal after processing the data signal to be displayed; the grid driving circuit loads corresponding signals to the grid lines and controls the display panel to display images in a second display mode; wherein the strobe terminal loads the second strobe signal.

It should be noted that the sequence of step S810 and step S820 is not differentiated. In practical applications, the step S810 may be located before the step S820, or the step S810 may be located after the step S820, which is not limited herein.

In particular, in step S810, the entire display area of the display panel 500 may be caused to display a screen. In step S820, a partial region in the display area of the display panel 500 may be caused to display a picture, so that power consumption may be reduced.

Next, a driving method of the display device according to an embodiment of the present invention will be described with reference to timing diagrams shown in fig. 1, 2, 5 and 6. Where n=44 and k=8 are taken as an example.

Referring to fig. 1, fig. 2, and fig. 5, in a first display mode, the driving method of the display device according to the embodiment of the present invention may include the following steps:

in the first display mode, the gate terminal CS is loaded with the first gate signal at the low level in the TF0 stage, so that the one-out-of-two selector 120 inputs the signal of the 44 th count output terminal CNT-44 to the second input terminal of the or gate 110.

This allows the or gate 110 to input a trigger signal to the input terminal D of the 1 st stage latch SK-1 under the common control of the signals of the second input terminal thereof and the enable terminal EN, and the 1 st stage latch SK-1 to output a corresponding count control signal CNT-1 under the control of the signal CK1 of the first clock signal terminal CK 1. The input terminal IN of the 1 st switching circuit TK-1 receives the signal CK3 of the third clock signal terminal CK3, and the 1 st switching circuit TK-1 outputs a high-level signal of the third clock signal terminal CK3 to the 1 st generation output terminal CTRL-1 under the control of the count control signal CNT-1 output from the 1 st count output terminal CNT-1, so that the 1 st generation output terminal CTRL-1 outputs the data control signal CTRL-1. And the input terminal IN of the 2 nd switching circuit TK-2 receives the signal CK2 of the second clock signal terminal CK2, and the 2 nd switching circuit TK-2 outputs a high-level signal of the second clock signal terminal CK2 to the 2 nd generation output terminal CTRL-2 under the control of the count control signal CNT-1 output from the 1 st count output terminal CNT-1, so that the 2 nd generation output terminal CTRL-2 outputs the data control signal CTRL-2.

The rest are the same, and so on, and are not described in detail herein.

And, the data processing output circuit 400 receives the data signal to be displayed and the data control signal, and outputs the processed data signal to each data input terminal of the display panel 500 through the data output terminal according to the data control signal. And, the gate driving circuit loads the corresponding signals to the gate lines so that the thin film transistors in the sub-pixels in the row are all turned on, and therefore the drain electrodes of the thin film transistors are loaded on the pixel electrodes to charge the pixel electrodes, and further, one row of sub-pixels of the display panel 500 are charged. After the charging of each row of sub-pixels in the display panel 500 is completed, the entire display area of the display panel 500 may be displayed.

Referring to fig. 1, fig. 2, and fig. 6, in a second display mode, the driving method of the display device according to the embodiment of the present invention may include the following steps:

in the second display mode, in the TF1 stage, the strobe terminal CS is loaded with the high-level second strobe signal, so that the one-out-of-two selector 120 inputs the signal of the 8 th count output terminal CNT-8 to the second input terminal of the or gate 110, which enables the or gate 110 to input the trigger signal to the input terminal D of the 1 st stage latch SK-1 under the common control of the signals of the second input terminal and the enable terminal EN, and the 1 st stage latch SK-1 outputs the corresponding count control signal CNT-1 under the control of the signal CK1 of the first clock signal terminal CK 1. The input terminal IN of the 1 st switching circuit TK-1 receives the signal CK3 of the third clock signal terminal CK3, and the 1 st switching circuit TK-1 outputs a high-level signal of the third clock signal terminal CK3 to the 1 st generation output terminal CTRL-1 under the control of the count control signal CNT-1 output from the 1 st count output terminal CNT-1, so that the 1 st generation output terminal CTRL-1 outputs the data control signal CTRL-1. And the input terminal IN of the 2 nd switching circuit TK-2 receives the signal CK2 of the second clock signal terminal CK2, and the 2 nd switching circuit TK-2 outputs a high-level signal of the second clock signal terminal CK2 to the 2 nd generation output terminal CTRL-2 under the control of the count control signal CNT-1 output from the 1 st count output terminal CNT-1, so that the 2 nd generation output terminal CTRL-2 outputs the data control signal CTRL-2.

The rest are the same, and so on, and are not described in detail herein.

And, the data processing output circuit 400 receives the data signal to be displayed and the data control signals ctrl-1 to ctrl-16, and outputs the data signal to be displayed to the corresponding data input terminal of the display panel 500 through the 16 data output terminals CO-1 to CO-16 after processing the data signal to be displayed according to the data control signals ctrl-1 to ctrl-16. And, the gate driving circuit loads the corresponding signals to the gate lines so that the thin film transistors in the sub-pixels in the row are all turned on, and therefore the drain electrodes of the thin film transistors are loaded on the pixel electrodes to charge the pixel electrodes, and then part of the sub-pixels in one row of the display panel 500 are charged, so that part of the areas in the display area of the display panel 500 are displayed.

The rest are the same, and so on, and are not described in detail herein.

And, the data processing output circuit 400 receives the data signal to be displayed and the data control signals ctrl-1 to ctrl-16, and outputs the data signal to be displayed to the corresponding data input terminal of the display panel 500 through the 16 data output terminals CO-1 to CO-16 after processing the data signal to be displayed according to the data control signals ctrl-1 to ctrl-16. And, the gate driving circuit loads the corresponding signals to the gate lines so that the thin film transistors in each sub-pixel in the row are all turned on, and therefore the drain electrodes of the thin film transistors are loaded on the pixel electrodes to charge the pixel electrodes, and then part of the sub-pixels in another row of the display panel 500 are charged. After the charging of part of the sub-pixels in all the rows in the display panel 500 is completed, part of the area in the display area of the display panel 500 can be displayed, so that power consumption can be reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A source driver circuit, comprising: a control circuit, a data output counter, a signal generation circuit, and a data processing output circuit; the data output counter is provided with a plurality of counting output ends, wherein the plurality of counting output ends comprise 1 st counting output ends to N th counting output ends which are sequentially arranged; wherein N is an integer greater than 1;

2. The source driver circuit of claim 1, wherein the control circuit comprises: or gate and alternative selector;

3. The source drive circuit of claim 1, wherein the data output counter comprises a plurality of latches in cascade; wherein the output end of one latch is correspondingly and electrically connected with one counting output end;

4. A source driving circuit according to any one of claims 1 to 3, wherein the signal generating circuit includes a plurality of switching circuits; wherein one of the switch circuits is correspondingly and electrically connected with one of the generating output ends; one counting output end is correspondingly and electrically connected with the control ends of at least two switching circuits;

5. The source driver circuit according to claim 4, wherein the plurality of switch circuits includes 1 st to 2N-th switch circuits arranged in order; the N-th counting output end is electrically connected with the control end of the 2N-1-th switching circuit and the control end of the 2N-th switching circuit, N is an integer and is more than or equal to 1 and less than or equal to N;

6. The source driver circuit of claim 5, wherein the switching circuit comprises: a transmission gate, a first inverter, a switching transistor, and a buffer;

7. A method for detecting a source driver circuit according to any one of claims 1 to 6, comprising:

8. A display device comprising the source driver circuit according to any one of claims 1 to 6.

9. The display device according to claim 8, further comprising: a display panel and a gate driving circuit;

10. A driving method of the display device according to claim 9, comprising:

In a second display mode, the control circuit outputs a trigger signal to the data output counter according to signals of the enabling end, the gating end and the kth counting output end; the data output counter enables the 1 st counting output end to the k th counting output end to sequentially output a counting control signal according to the trigger signal; the signal generation circuit enables a plurality of generation output ends of the signal generation circuit to sequentially output data control signals according to the count control signals output from the 1 st count output end to the kth count output end; the data processing output circuit receives the data signal to be displayed and the data control signal, and outputs the data signal to the corresponding data input terminal in the display panel through a part of data output end according to the data control signal after processing the data signal to be displayed;

the grid driving circuit loads corresponding signals to the grid lines and controls the display panel to display images in a second display mode; wherein the strobe terminal loads a second strobe signal.