CN113484718A - Detection circuit structure and detection method - Google Patents
Detection circuit structure and detection method Download PDFInfo
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- CN113484718A CN113484718A CN202110643915.4A CN202110643915A CN113484718A CN 113484718 A CN113484718 A CN 113484718A CN 202110643915 A CN202110643915 A CN 202110643915A CN 113484718 A CN113484718 A CN 113484718A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
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Abstract
The invention provides a detection circuit structure and a detection method for quickly positioning the open circuit position of a circuit, wherein a first-level test point is arranged at two ends of a serpentine circuit, a high-level test point of a high-level test position is arranged on a first terminal and/or a second terminal, and a voltage with potential difference is accessed to the two ends of the serpentine circuit and other test points to perform grading test, so that a fault sub-circuit of the serpentine circuit can be quickly positioned, the test frequency C is less than or equal to m x n, wherein m is the number of high-level test points in the high-level test position of a single stage; n is the stage number of the high-level test bit, so that the test efficiency and the accuracy are improved.
Description
Technical Field
The invention relates to the field of precision electric line design, in particular to a detection line structure and a detection method.
Background
The existing electric lines of a display panel, a touch panel, a Flexible Printed Circuit (FPC) and a chip on film/COF are more and more precisely arranged, as shown in fig. 1, the line structure includes a plurality of circuits 1, each circuit 1 includes a main circuit 10 and terminals 11, the terminals 11 are located at two ends of the main circuit 10 and are electrically connected with other electronic devices through the terminals 11, but as the current line spacing and line width have been developed to micron-level or even nanometer-level, the lines are easily broken, and short circuits occur between adjacent lines, it is necessary to perform electric performance detection on the line structure before putting products into the latter stage production, and it is avoided that products with short circuit or broken circuit problems flow into the latter stage production process. The line detection is usually carried out on the product by using an automatic optical inspection device (AOI) and a precision probe inspection device in the industry, the AOI equipment is expensive, the requirement on the cleanliness of the test is very high, but the misjudgment rate of the micron-scale or even nano-scale line is still higher. The precision probe detection device is expensive and difficult to maintain, and can detect all lines in sequence, so that the time consumption is long, even the phenomenon of multiple misalignment occurs, and the misjudgment rate is high.
Disclosure of Invention
In order to solve the above technical problems, a primary objective of the present invention is to provide a detection circuit structure and a detection method, so as to solve the problems of time consuming detection and high false rate in the prior art.
In order to achieve the above object, the present invention provides a detection line structure, including: each sub-circuit comprises a main circuit, a first terminal and a second terminal, and the first terminal and the second terminal are respectively located at the first end and the second end of the main circuit. The detection circuit structure of the invention is different from the existing detection circuit in that the detection circuit structure further comprises a plurality of connecting lines, and two first terminals of two adjacent sub-circuits and two second terminals of two adjacent sub-circuits are alternately and electrically connected through the connecting lines to form a snake-shaped continuous circuit, which is also called a snake-shaped circuit.
In an optional scheme, a test bit which can be divided into several stages is further provided on the serpentine circuit, and the test bit includes: the test circuit comprises a first level test bit and a high level test bit, wherein the first level test bit comprises a first level test point arranged at two ends of a serpentine circuit, the high level test bit comprises a high level test point connected with a first terminal and/or a second terminal, and the high level test bit comprises but is not limited to a second level test bit. And the second-stage test points in the second-stage test positions divide the snake-shaped circuit in the first-stage test positions into a plurality of circuit intervals.
Similarly, in the specific scheme, the circuit between the adjacent second-level test points may be further divided into a plurality of circuit sections by a plurality of third-level test points, and so on, the adjacent high-level test point 100 of the same-level test bit is continuously divided into smaller circuit sections until the adjacent high-level test point is connected to the adjacent first terminal or second terminal. It should be noted that when the number of sub-lines is small, only the second-level test points may be set, and the number of levels of the specific high-level test points needs to be determined according to the number of sub-lines.
If the number of sub-circuits contained in the serpentine circuit is large, a higher-level test bit can be arranged between two adjacent second-level test points, and a plurality of higher-level test points are arranged in the higher-level test bit of each level to divide the serpentine circuit into groups further, so that the test times can be shortened. Generally, the high level test points in a serpentine circuit satisfy the following relationship with the wires: s is approximately equal to mn(ii) a Wherein S is the number of the sub-lines, and m is the number of the high-level test points in the single-level high-level test positions; n is the number of stages of the high-level test bits, and it should be noted that the high-level test bits include the second-level test bits.
The application also provides a detection method for rapidly testing the fault position of the circuit based on the circuit structure, which comprises the following steps:
connecting two first-stage test points with a first power supply and a second power supply respectively, wherein the first power supply and the second power supply have potential difference, for example, two test probes of a universal meter are used for providing the first power supply and the second power supply respectively;
when the circuit parameter is abnormal, such as the current is zero, the open circuit condition in the snake-shaped circuit is determined.
After the power supply connected with the first-stage test point is disconnected, the adjacent second-stage test points are respectively connected with the first power supply and the second power supply, and when the circuit parameters are abnormal, the condition that the adjacent second-stage test points are disconnected is determined.
Optionally, the detection method further comprises:
the detection method for detecting a plurality of levels of test points comprises the steps of firstly, respectively connecting adjacent test points of a test position at a lower level with a first power supply and a second power supply to determine the adjacent test points with abnormal circuit parameters; and then, respectively connecting the adjacent test points in the higher-level test position between the adjacent test points with abnormal circuit parameters with the first power supply and the second power supply to determine the adjacent test points in the higher-level test position with abnormal circuit parameters until determining the sub-circuit with abnormal circuit parameters. For example, to test the location of a failed circuit in an adjacent third level test point, the location of the failed circuit in the adjacent second level test point to which the failed circuit belongs needs to be tested first.
According to the detection circuit structure and the detection method for quickly positioning the open circuit position of the circuit, the first-level test points are arranged at the two ends of the serpentine circuit, the high-level test points of the high-level test positions are arranged on the first terminal and/or the second terminal, and the voltage with potential difference is accessed to the two ends of the serpentine circuit and other test points to perform grading test, so that the fault sub-circuit of the serpentine circuit can be quickly positioned, the test time C is less than or equal to m x n, wherein m is the number of the high-level test points in the single-level high-level test positions; n is the stage number of the high-level test bit, so that the test efficiency and the accuracy are improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a conventional detection circuit structure;
FIG. 2 is a schematic diagram of a first embodiment of the detection circuit structure of the present invention
FIG. 3 shows a schematic diagram of a second embodiment of the detection circuit structure of the present invention;
fig. 4 shows a schematic configuration diagram of a third embodiment of the detection line configuration of the present invention.
Wherein the figures include the following reference numerals:
1. a circuit; 2. a sub-line; 10. a main circuit; 11. a terminal;
20. a main line; 21. a first terminal; 22. a second terminal;
100. a high-level test point; 101. a first level test point; 102. a second level test point;
103. a third level test point; 104. a fourth level test point; 200. and connecting the wires.
Detailed Description
It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present invention will be described in detail below with reference to the embodiments with reference to the attached drawings.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
To achieve the above objective, referring to fig. 2 to 3, the present invention provides a detection circuit structure.
As shown in fig. 2, the detection line structure of the present embodiment includes: the circuit comprises a plurality of sub-lines 2 arranged side by side, wherein each sub-line 2 comprises a main line 10, a first terminal 21 and a second terminal 22, and the first terminal 21 and the second terminal 22 are respectively positioned at the first end and the second end of the main line 10. The detection line structure further includes a plurality of connection lines 200, and the two first terminals 21 of the two adjacent sub-lines 2 and the two second terminals 22 of the two adjacent sub-lines 2 are alternately electrically connected through the connection lines 200 to form a serpentine circuit.
As shown in fig. 3, in the present embodiment, a test bit (indicated by a dotted line in the figure) which can be divided into several stages is disposed on the serpentine circuit, and the test bit includes: the test circuit comprises a first-level test bit and a high-level test bit, wherein the first-level test bit comprises a first-level test point 101 arranged at two ends of a serpentine circuit, and the high-level test bit comprises a high-level test point 100 connected with a first terminal 21 and/or a second terminal 22. The second test point 102 in the second test bit divides the serpentine circuit in the first test point 101 into several circuit sections. In this embodiment, the circuit between the adjacent second-level test points 102 may be further divided into a plurality of circuit sections by a plurality of third-level test points 103, and so on, the adjacent high-level test points 100 of the same level of test bit are continuously divided into smaller circuit sections until the adjacent high-level test points 100 connect the adjacent first terminals 21 or second terminals 22.
During specific testing, voltages with potential differences are loaded on the first-level test points 101 at two ends of the serpentine circuit respectively, whether the circuit has faults such as open circuit or not can be judged at one time, and parameters of the voltage test circuit with the potential differences can be loaded on the high-level test points 100, so that the fault positions can be quickly positioned and judged.
Specifically, two test probes of the multimeter can be used to provide voltages with potential difference, and the voltages are directly contacted with the first-level test point 101 and the high-level test point 100 of the serpentine circuit respectively so as to test the resistance value, the current value or the voltage value of the serpentine circuit.
Taking the test current value as an example, under normal conditions, any first-level test point 101 and any high-level test point 100 connected by the serpentine circuit are all paths, and then when the probe of the multimeter contacts two first-level test points 101, the current value should not be zero. When the current value is zero, it is proved that the open circuit condition exists in the serpentine circuit, at this time, the probes can be respectively contacted with two adjacent second-stage test points 102, and when the adjacent second-stage test points 102 with the current value of zero are detected, the open circuit condition exists between the adjacent second-stage test points 102. In this way, the test point classification of the serpentine circuit has only two stages, and can be used for the case that the number of the sub-circuits 2 is small, such as less than 10.
If the number of the sub-line 2 is large, a higher-level test bit may be further disposed between two adjacent second-level test points 102, and a plurality of higher-level test points 100 are disposed in the higher-level test bit of each level, so as to further divide the groups of the serpentine circuits, which is convenient for shortening the test times. In general, the high level test point 100 in a serpentine circuit satisfies the following relationship with sub-line 2: s is approximately equal to mn(ii) a Wherein S is the number of the sub-lines 2, and m is the number of the high-level test points 100 in the single-level high-level test positions; n is the number of levels of the advanced test bits.
In a preferred embodiment, the difference between m and n is | m-n | ≦ 2, and when S is a fixed value, the closer the values of m and n, the minimum value of the number of tests C.
In the most preferred embodiment, m is n, and the number of tests C is the smallest.
If the relationship of m-n cannot be formed, in a preferred embodiment, m-n is 1, in this case, the number of stages n of the high-stage test points 100 is reduced, and thus the wiring margin space can be saved, and the raw material can be saved.
Alternatively, the high-level test point 100 may be provided only on the first terminal 21 or only on the second terminal 22.
Preferably, as shown in fig. 4, the high-level test point 100 is provided on both the first terminal 21 and the second terminal 22.
Referring to fig. 2 and fig. 3, an embodiment of the present application provides a detection method based on the above detection circuit structure for locating a circuit fault location, including:
connecting two first-stage test points 101 with a first power supply and a second power supply respectively, wherein the first power supply and the second power supply have potential difference, for example, two test probes of a universal meter are used for providing the first power supply and the second power supply respectively;
when the circuit parameter is abnormal, for example, when the current is zero, the power supply connected with the first-stage test point 101 is disconnected, and then the adjacent second-stage test points 102 are respectively connected with the first power supply and the second power supply, and when the circuit parameter is abnormal, the condition that the adjacent second-stage test points 102 are disconnected is determined.
Optionally, the testing method further includes detecting a situation of a disconnection location between a plurality of adjacent high-level test points 100 disposed between the second-level test points 102, and a connection manner of the high-level test points 100 may refer to a specific description of the embodiment in fig. 2.
Optionally, the detection method further comprises:
the detection method for detecting the plurality of high-level test points 100 comprises the following steps of firstly, respectively connecting the adjacent high-level test points 100 of a lower level with a first power supply and a second power supply to determine the adjacent high-level test points 100 of the lower level with abnormal circuit parameters; and then, respectively connecting the adjacent high-level test point 100 with the first power supply and the second power supply in the high-level test points 100 with the first level and the second level to determine the adjacent high-level test point 100 with the first level and the second level until determining the sub-line 2 with the abnormal circuit parameters. For example, to test the location of a failed circuit in an adjacent third level test point 103, the location of the failed circuit in the adjacent second level test point 102 needs to be tested first.
Referring to fig. 3, taking four levels of test bits as an example, the four levels of test bits respectively include a first level test point 101, a second level test point 102, a third level test point 103, and a fourth level test point 104. Taking the test current value as an example, under normal conditions, the current value should not be zero after the probe of the multimeter contacts the two first-level test points 101. When the current value is zero, the snake-shaped circuit is proved to have an open circuit condition. At this time, the probes are respectively contacted with the adjacent second-stage test points 102, and when the adjacent second-stage test points 102 with the current value of zero are detected, the circuit between the adjacent second-stage test points 102 is proved to have an open circuit condition. And then the probes are respectively contacted with the adjacent third-level test points 103 in the adjacent second-level test points 102 with the current value of zero, and when the adjacent third-level test points 103 with the current value of zero are detected, the circuit between the adjacent third-level test points 103 is proved to have an open circuit condition. Then, the probes are respectively contacted with the adjacent fourth test points 104 in the adjacent third test points 103 with the current value of zero, and when the adjacent fourth test points 104 with the current value of zero are detected, the circuit breaking condition of the circuit between the adjacent fourth test points 104 is proved, so that the specific breaking position is determined.
The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A detection line structure comprising: the detection circuit structure comprises a plurality of parallel sub-circuits (2), wherein each sub-circuit (2) comprises a main circuit (10), a first terminal (21) and a second terminal (22), the first terminal (21) and the second terminal (22) are respectively positioned at the first end and the second end of the main circuit (10), the detection circuit structure further comprises a plurality of connecting lines (200), and the connecting lines (200) are alternately and electrically connected with the two first terminals (21) of the two adjacent sub-circuits (2) and the two second terminals (22) of the two adjacent sub-circuits (2) to form a snake-shaped circuit; the serpentine circuit is characterized in that a plurality of stages of test bits are arranged on the serpentine circuit.
2. The sense line structure of claim 1, wherein the test bit comprises: the test circuit comprises a first-level test position and a high-level test position, wherein the first-level test position comprises a first-level test point (101) arranged at two ends of a snake-shaped circuit, and the high-level test position comprises a high-level test point (100) connected with a first terminal (21) and/or a second terminal (22).
3. The test line structure according to claim 2, characterized in that the high-level test points (100) and the sub-lines (2) satisfy the following relationship: s is approximately equal to mn(ii) a Wherein S is the number of the sub-lines (2), and m is the number of the high-level test points (100) in the single-level high-level test positions; n is the number of levels of the advanced test bits.
4. The detection line structure of claim 3, wherein the difference | m-n | ≦ 2 between m and n.
5. The test line structure of claim 3, wherein m-n.
6. The sensing circuit structure of claim 1, wherein said sensing circuit parameter is a resistance value, a current value, or a voltage value.
7. The test line structure of claim 2, wherein said high-level test point (100) is provided only on said first terminal (21) or only on said second terminal (22).
8. Test line structure according to claim 2, characterized in that the high-level test point (100) is provided on both the first terminal (21) and the second terminal (22).
9. A method for inspecting a wiring structure according to any one of claims 1 to 8, comprising:
connecting two first-stage test points (101) with a first power supply and a second power supply respectively, wherein the first power supply and the second power supply have potential difference, for example, two test probes of a universal meter are used for providing the first power supply and the second power supply respectively;
when the circuit parameters are abnormal, for example, when the current is zero, after a power supply connected with the first-stage test point (101) is disconnected, the adjacent second-stage test points (102) are respectively connected with the first power supply and the second power supply, and when the circuit parameters are abnormal, the condition that the adjacent second-stage test points (102) are disconnected is determined.
10. The detection method according to claim 9,
further comprising: the detection method for detecting the plurality of high-level test points (100) comprises the steps of firstly, respectively connecting a first power supply and a second power supply to adjacent high-level test points (100) of a lower level so as to determine the adjacent high-level test points (100) of the lower level with abnormal circuit parameters; and then, respectively connecting the adjacent higher-level test point (100) of the lower level of the abnormal circuit parameter with a first power supply and a second power supply to determine the adjacent higher-level test point (100) of the higher level of the abnormal circuit parameter until determining the sub-circuit (2) of the abnormal circuit parameter.
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| CN202110643915.4A CN113484718A (en) | 2021-06-09 | 2021-06-09 | Detection circuit structure and detection method |
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| CN102981094A (en) * | 2012-11-23 | 2013-03-20 | 深圳莱宝高科技股份有限公司 | Panel testing device |
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