CN113473708A - Manufacturing method of circuit board structure - Google Patents
Manufacturing method of circuit board structure Download PDFInfo
- Publication number
- CN113473708A CN113473708A CN202010236226.7A CN202010236226A CN113473708A CN 113473708 A CN113473708 A CN 113473708A CN 202010236226 A CN202010236226 A CN 202010236226A CN 113473708 A CN113473708 A CN 113473708A
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- Prior art keywords
- circuit board
- manufacturing
- holes
- plasma processing
- circuit
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 30
- 238000012545 processing Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 18
- 238000004140 cleaning Methods 0.000 claims abstract description 14
- 230000000149 penetrating effect Effects 0.000 claims abstract description 10
- 238000005553 drilling Methods 0.000 claims abstract description 9
- 230000005672 electromagnetic field Effects 0.000 claims abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- 239000011889 copper foil Substances 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 239000003292 glue Substances 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 31
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 239000011347 resin Substances 0.000 description 7
- 229920005989 resin Polymers 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 229920001971 elastomer Polymers 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229920001568 phenolic resin Polymers 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000002893 slag Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000805 composite resin Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011532 electronic conductor Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
The invention discloses a manufacturing method of a circuit board structure, and relates to the field of circuit board manufacturing. The method comprises the following steps: drilling a circuit board substrate containing the low-dielectric-constant material layer to form a hole penetrating through the low-dielectric-constant material layer; placing the circuit board substrate in a plasma processing chamber which accords with high vacuum conditions; supplying a plasma processing gas into the plasma processing chamber, the plasma processing gas comprising CF4、O2And N2(ii) a Applying 5000-9000W of RF source power to electrode plates in the plasma processing chamber to form an electromagnetic field between adjacent electrode plates so as to promote gas ionization to form plasma; the holes of the substrate of the circuit board are cleaned by using the plasma, the cleaning temperature of the holes is 70-90 ℃, and the cleaning time of the holes is 25-75 minutes. After the low-dielectric-constant material layer is drilled, the residual glue residues in the hole can be effectively removed.
Description
Technical Field
The invention relates to the field of circuit board manufacturing, in particular to a manufacturing method of a circuit board structure.
Background
A Printed Circuit Board (PCB) is a Circuit Board formed by patterning electronic wiring connecting Circuit components according to Circuit design and then reproducing electronic conductors on an insulator through processes such as specific machining and processing, and is mainly intended to allow the electronic components disposed on the Circuit Board to function through a Circuit on the Circuit Board.
In the conventional multi-layer PCB manufacturing process, there are different methods for processing via holes, such as drilling through each PCB layer at a time by mechanical drilling, that is, drilling through the via holes together with a resin layer (e.g., phenolic resin or epoxy resin) and a copper foil layer. The interlayer connection is formed by stacking and pressing a plurality of laminates and then perforating at a predetermined position to form a through hole. Then, a copper-clad electroplating is carried out to form a conductive copper metal film, the conductive copper metal film is arranged on the hole wall and the periphery of the via hole, then, steps of resin hole plugging, copper covering and the like are carried out, and further, line etching is carried out, so that the required circuit board and line configuration are achieved.
With the trend of miniaturization of electronic products and the development of 5G products, low dielectric constant materials are used in multilayer PCBs, i.e., low dielectric constant material layers are used as a part of multilayer PCBs, which have high advantages in signal transmission.
However, the physicochemical properties of low dielectric constant materials can lead to: after the drilling of the low-k material layer is completed, the drilling smear (mainly the smear) remained in the hole is difficult to be removed by the traditional chemical desmearing method.
Disclosure of Invention
Aiming at the defects in the prior art, the invention solves the technical problems that: after the low dielectric constant material layer is drilled, how to effectively remove the glue residue remained in the hole.
In order to achieve the above object, the present invention provides a method for manufacturing a circuit board structure, comprising the steps of:
s101: providing a circuit board substrate comprising a low dielectric constant material layer;
s102: drilling a circuit board substrate containing the low-dielectric-constant material layer to form a hole penetrating through the low-dielectric-constant material layer;
s103: placing the circuit board substrate in a plasma processing chamber which accords with high vacuum conditions;
s104: supplying a plasma processing gas into the plasma processing chamber, the plasma processing gas comprising CF4、O2And N2；
S105: applying 5000-9000W of RF source power to electrode plates in the plasma processing chamber to form an electromagnetic field between adjacent electrode plates so as to promote gas ionization to form plasma;
s106: the holes of the substrate of the circuit board are cleaned by using the plasma, the cleaning temperature of the holes is 70-90 ℃, and the cleaning time of the holes is 25-75 minutes.
Based on the above technical solution, the RF source power in S105 is 8000W.
On the basis of the technical scheme, the cleaning temperature of the holes in the S106 is 80 ℃ or about 85 ℃.
On the basis of the technical scheme, the cleaning time of the holes in the S106 is 30 minutes, 35 minutes, 40 minutes, 50 minutes or 65 minutes.
On the basis of the above technical solution, the specific process of S104 includes:
s1041: supply N2And O2，N2And O2Supplied at a volumetric flow rate ratio of 1: 0.5-30;
s1042: supplying CF4、N2、O2，CF4And O2Supplied at a volumetric flow rate ratio of 1: 0.5-10; CF4 and N2 are supplied at a volumetric flow ratio of between 1:0.25 and 0.5;
s1043: supply of O2，O2The ratio of the total volumetric flow rate of (a) to the total volumetric flow rate in S1041 is between about 0.8 and 1.2;
s1044: supply N2And O2，N2And O2Supplied at a volumetric flow ratio of between about 1:0.5 and 1: 30.
On the basis of the above technical solution, the following steps are further included after S1044:
s1045: supply N2And Ar and H2Mixed gas of (2), N2And the mixed gas is supplied at a volume flow ratio of between 1:0.5 and 5.
Based on the above technical solution, the degree of vacuum corresponding to the high vacuum condition in S103 is 0.15 to 0.25 Torr.
On the basis of the technical scheme, the circuit board base material in the S101 comprises an upper board surface, a multilayer board and a lower board surface which are sequentially arranged from top to bottom; the multilayer board comprises a plurality of layers which are sequentially stacked from top to bottom, and each layer is formed by etching at least one copper foil substrate through an inner layer circuit; an insulating layer is arranged between the adjacent laminates, wherein at least one insulating layer is a low dielectric constant material layer.
On the basis of the above technical solution, the holes in S102 include: the through holes penetrate through the upper plate surface, the multilayer plate and the lower plate surface; and a layer hole penetrating through at least one layer of low dielectric constant material layer but not penetrating through the circuit board base material.
Compared with the prior art, the invention has the advantages that:
the invention uses ionization of strong electric field to make plasma processing gas pass through radio frequency source power to form plasma under the condition of high temperature and high vacuum degree. The resin residue is converted into volatile gas by plasma physical bombardment and chemical reaction, so as to achieve the effect of cleaning the rubber slag in the drill hole. The plasma treatment not only has good adhesive removing capability, but also can improve the reliability of the circuit board.
Drawings
FIG. 1 is a flow chart of a method for fabricating a circuit board structure according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a circuit board structure according to an embodiment of the invention.
In the figure: 1-multilayer board, 10-circuit board substrate, 11-upper board surface, 12-lower board surface, 13-through hole and 14-layer hole.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
As used in this embodiment, "about" means that the corresponding value or range of values cannot be within twenty percent, preferably within ten percent, and more preferably within five percent.
Referring to fig. 1, the method for manufacturing a circuit board structure according to an embodiment of the present invention includes the following steps:
s101: a circuit board substrate including a low dielectric constant material layer is provided.
Referring to fig. 2, the circuit board substrate 10 in S101 includes an upper board surface 11, a multilayer board 1, and a lower board surface 12, which are sequentially arranged from top to bottom. The multilayer board 1 includes a plurality of boards stacked in this order from top to bottom, each of which is made by cutting at least one copper clad laminate (copper clad laminate may be one in which a copper foil is laid on each of both surfaces of an insulating substrate) to a suitable size and etching inner layer lines. An insulating layer is arranged between the adjacent laminates, wherein at least one insulating layer is a low dielectric constant material layer.
In some embodiments, the material of the low-k material layer is resin, and the resin may be selected from: epoxy Resin, Phenolic Resin, Polyimide Resin, BT Resin (bismalemide Resin), or composite Resin material.
S102: drilling holes in the circuit board substrate containing the low-dielectric-constant material layer to form holes penetrating through the low-dielectric-constant material layer.
Referring to fig. 2, the holes of the circuit board substrate including the low-k material layer in S102 include:
(1) through holes 13 penetrating the upper board surface 11, the multilayer board 1 and the lower board surface 12, that is, through holes penetrating each board structure of the circuit board substrate 10.
(2) A layer hole 14 extending through at least one of the low-k material layers but not through the circuit board substrate 10.
S103: the circuit board substrate is placed in a plasma processing chamber.
The specific process of S103 is as follows: the circuit board substrate is placed in a plasma processing chamber, which may be configured with a vacuum pump to evacuate air from the chamber, thereby maintaining the circuit board substrate in a high vacuum condition corresponding to a vacuum degree of about 0.15 to 0.25Torr, preferably about 0.17Torr and about 0.2Torr (1 Torr: 133.3223684 Pa.).
S104: supplying a plasma processing gas into the plasma processing chamber.
The plasma processing gas in S104 includes CF4、O2And N2Preferably, the plasma treatment gas may further include Ar, He or H2And cleaning the gas to facilitate cleaning.
In some embodiments, the plasma processing gas comprises N2And O2And N is2And O2Is supplied at a volumetric flow ratio of between about 1:0.5 and 30, preferably about 1:1.5, about 1:5, about 1:10, about 1:15 or about 1: 22.
In some embodiments, the plasma processing gas comprises CF4And O2And CF4And O2Supplied at a volumetric flow ratio of between about 1:0.5 to 10; preferably about 1:1.5, about 1:5, about 1:7.8 or about 1: 10.
In some embodiments, the specific process of S104 is:
s1041: supply N2And O2，N2And O2Supplied at a volumetric flow ratio of between about 1:0.5 to 30;
s1042: supplying CF4、N2、O2，CF4And O2Supplied at a volumetric flow ratio of between about 1:0.5 to 10; CF4 and N2 are supplied at a volumetric flow ratio of between about 1:0.25 to 0.5;
s1043: supply of O2，O2The ratio of the total volumetric flow rate of (a) to the total volumetric flow rate in S1041 is between about 0.8 and 1.2;
s1044: supply N2And O2，N2And O2Supplied at a volumetric flow ratio of between about 1:0.5 and 1: 30;
s1045: supply N2And Ar and H2Mixed gas of (2), N2And the mixed gas is supplied at a volumetric flow ratio of between about 1:0.5 and 5.
S105: RF (Radio Frequency) source power is applied to electrode plates in a plasma processing chamber, and an electromagnetic field is formed between adjacent electrode plates to promote ionization of gas to form plasma.
The range of the RF source power in S105 is about 5000-9000W, preferably about 5000W, about 8000W or about 9000W, the degumming rate is high at 8000W, and the service life of the equipment is long.
S106: the holes of the substrate of the circuit board are cleaned by plasma.
The temperature for cleaning the holes in S106 is about 70-90 deg.c, preferably about 80 deg.c or about 85 deg.c, at which the intermolecular motion is active. .
The cleaning time of the holes in S106 is about 25-75 minutes, preferably about 25 minutes, about 30 minutes, about 35 minutes, about 40 minutes, about 50 minutes or about 65 minutes.
Preferably, after removing the glue residue in the hole, a copper plating process may be further performed on the inner wall of the hole, and in some embodiments, the process includes a chemical copper process and an electroplating copper process, but the invention is not limited thereto.
As can be seen from the above embodiments, the present invention forms plasma by passing plasma processing gas through the rf source power under the high temperature and high vacuum condition by using the ionization effect of the strong electric field. The resin residue is converted into volatile gas by plasma physical bombardment and chemical reaction, so as to achieve the effect of cleaning the rubber slag in the drill hole. The plasma treatment not only has good adhesive removing capability, but also can improve the reliability of the circuit board.
Further, the present invention is not limited to the above-mentioned embodiments, and it will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the principle of the present invention, and these modifications and improvements are also considered to be within the scope of the present invention. Those not described in detail in this specification are within the skill of the art.
Claims (9)
1. A manufacturing method of a circuit board structure is characterized by comprising the following steps:
s101: providing a circuit board substrate comprising a low dielectric constant material layer;
s102: drilling a circuit board substrate containing the low-dielectric-constant material layer to form a hole penetrating through the low-dielectric-constant material layer;
s103: placing the circuit board substrate in a plasma processing chamber which accords with high vacuum conditions;
s104: supplying a plasma processing gas into the plasma processing chamber, the plasma processing gas comprising CF4、O2And N2；
S105: applying 5000-9000W of RF source power to electrode plates in the plasma processing chamber to form an electromagnetic field between adjacent electrode plates so as to promote gas ionization to form plasma;
s106: the holes of the substrate of the circuit board are cleaned by using the plasma, the cleaning temperature of the holes is 70-90 ℃, and the cleaning time of the holes is 25-75 minutes.
2. A method of manufacturing a circuit-board structure according to claim 1, characterized in that: the RF source power in S105 is 8000W.
3. A method of manufacturing a circuit-board structure according to claim 1, characterized in that: the temperature of the holes cleaned in S106 is 80 ℃ or about 85 ℃.
4. A method of manufacturing a circuit-board structure according to claim 1, characterized in that: the wash time for the holes in S106 was 30 minutes, 35 minutes, 40 minutes, 50 minutes, or 65 minutes.
5. The method for manufacturing a circuit board structure according to claim 1, wherein the specific process of S104 comprises:
s1041: supply N2And O2，N2And O2Supplied at a volumetric flow rate ratio of 1: 0.5-30;
s1042: supplying CF4、N2、O2，CF4And O2Supplied at a volumetric flow rate ratio of 1: 0.5-10; CF4 and N2 are supplied at a volumetric flow ratio of between 1:0.25 and 0.5;
s1043: supply of O2，O2The ratio of the total volumetric flow rate of (a) to the total volumetric flow rate in S1041 is between about 0.8 and 1.2;
s1044: supply N2And O2，N2And O2Supplied at a volumetric flow ratio of between about 1:0.5 and 1: 30.
6. The method for manufacturing a circuit board structure according to claim 5, further comprising the following steps after S1044:
s1045: supply N2And Ar and H2Mixed gas of (2), N2And the mixed gas is supplied at a volume flow ratio of between 1:0.5 and 5.
7. A method of manufacturing a circuit-board structure according to claim 1, characterized in that: the degree of vacuum corresponding to the high vacuum condition in S103 is 0.15 to 0.25 Torr.
8. A method of manufacturing a circuit-board structure according to any of claims 1to 7, characterized in that: the circuit board base material in the S101 comprises an upper board surface (11), a multilayer board (1) and a lower board surface (12) which are sequentially arranged from top to bottom; the multilayer board (1) comprises a plurality of layers which are sequentially stacked from top to bottom, and each layer is formed by etching at least one copper foil substrate through an inner layer circuit; an insulating layer is arranged between the adjacent laminates, wherein at least one insulating layer is a low dielectric constant material layer.
9. The method for fabricating a circuit board structure according to claim 8, wherein the holes in S102 comprise: a through hole (13) penetrating through the upper plate surface (11), the multilayer plate (1) and the lower plate surface (12); and a layer hole (14) penetrating through the at least one low dielectric constant material layer but not through the circuit board substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010236226.7A CN113473708A (en) | 2020-03-30 | 2020-03-30 | Manufacturing method of circuit board structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010236226.7A CN113473708A (en) | 2020-03-30 | 2020-03-30 | Manufacturing method of circuit board structure |
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| Publication Number | Publication Date |
|---|---|
| CN113473708A true CN113473708A (en) | 2021-10-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010236226.7A Pending CN113473708A (en) | 2020-03-30 | 2020-03-30 | Manufacturing method of circuit board structure |
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| Country | Link |
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| CN (1) | CN113473708A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW512448B (en) * | 1999-05-11 | 2002-12-01 | Applied Materials Inc | Sequential sputter and reactive precleans of vias and contacts |
| CN102833952A (en) * | 2012-09-18 | 2012-12-19 | 东莞市若美电子科技有限公司 | Adhesive-removal method for printed circuit board HDI (high density interconnection) product |
| TW201534410A (en) * | 2014-02-11 | 2015-09-16 | Applied Materials Inc | Cleaning process for cleaning amorphous carbon deposition residuals using low RF bias frequency applications |
| US20180211845A1 (en) * | 2016-12-31 | 2018-07-26 | L'Air Liquide, Société Anonyme pour I'Etude et I'Exploitation des Procédés Georges Claude | Methods of minimizing plasma-induced sidewall damage during low k etch processes |
| CN109168265A (en) * | 2018-10-25 | 2019-01-08 | 铜陵市超远科技有限公司 | A kind of high-frequency microwave plate high density interconnection board manufacturing method |
-
2020
- 2020-03-30 CN CN202010236226.7A patent/CN113473708A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW512448B (en) * | 1999-05-11 | 2002-12-01 | Applied Materials Inc | Sequential sputter and reactive precleans of vias and contacts |
| CN102833952A (en) * | 2012-09-18 | 2012-12-19 | 东莞市若美电子科技有限公司 | Adhesive-removal method for printed circuit board HDI (high density interconnection) product |
| TW201534410A (en) * | 2014-02-11 | 2015-09-16 | Applied Materials Inc | Cleaning process for cleaning amorphous carbon deposition residuals using low RF bias frequency applications |
| US20180211845A1 (en) * | 2016-12-31 | 2018-07-26 | L'Air Liquide, Société Anonyme pour I'Etude et I'Exploitation des Procédés Georges Claude | Methods of minimizing plasma-induced sidewall damage during low k etch processes |
| CN109168265A (en) * | 2018-10-25 | 2019-01-08 | 铜陵市超远科技有限公司 | A kind of high-frequency microwave plate high density interconnection board manufacturing method |
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Application publication date: 20211001 |
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