CN113471284A - N极性GaN晶体管结构的制备方法和半导体结构 - Google Patents
N极性GaN晶体管结构的制备方法和半导体结构 Download PDFInfo
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Abstract
本发明的实施例提供了一种N极性GaN晶体管结构的制备方法和半导体结构,涉及半导体技术领域,通过沉积形成Ga极性的外延功能层,并在外延功能层上键合形成支撑衬底,然后将该外延结构倒置后去除结构衬底和缓冲层,在暴露出的外延功能层远离支撑衬底的一侧制作源极、漏极和栅极,以形成N极性的GaN晶体管结构。其中,N极性GaN晶体管的外延结构由直接生长的Ga极性外延层上下倒置获得,其材料质量相比直接外延生长的N极性材料更高,能够得到高电阻的GaN绝缘层和陡峭界面的异质结,因而可增强N极性GaN晶体管的耐高压能力、减小器件导通损耗,提升器件整体性能。
Description
技术领域
本发明涉及GaN基电子器件领域,具体而言,涉及一种N极性GaN晶体管结构的制备方法和半导体结构。
背景技术
极性是三五族氮化物半导体材料非常重要的性质之一。传统GaN基电子及光电器件均基于Ga极性材料。然而,得益于与传统Ga极性材料相反的极化电场,基于N极性GaN材料的电子器件可具有更低的接触电阻、更强的耐高电压能力、更高的功率密度和效率、更灵活的结构设计优势和尺寸微缩优势。近年来,N极性Ga(Al)N晶体管在功率开关和射频放大领域的出色表现,逐渐引起学术界和产业界极大的兴趣。在功率开关方面,N极性HEMT器件展示了超低的动态导通电阻(~5%)和极高的击穿电压(>2000V);在射频放大领域,N极性HEMT器件在94GHz频率下实现了超高的功率密度(8W/mm)和功率附加效率(27.8%),远优于当前任何同类Ga极性器件。
高质量N极性GaN材料的制备是当前N极性器件的一大挑战。目前N极性GaN材料多基于在蓝宝石或者SiC衬底上采用金属有机气相外延或者分子束外延的方法直接生长得到,材料的表面粗糙度高、晶体质量差、杂质浓度高,难以得到具有陡峭界面的AlGaN/GaN异质结和高电阻的GaN绝缘层,导致N极性GaN高电子迁移率晶体管存在沟道电阻高、器件关态漏电大的问题。
发明内容
本发明的目的包括,例如,提供了一种N极性GaN晶体管结构的制备方法和半导体结构,其能够得到具有高电阻GaN绝缘层和陡峭界面的异质结的N极性GaN高电子迁移率晶体管,提升器件性能。
本发明的实施例可以这样实现:
第一方面,本发明提供一种N极性GaN晶体管结构的制备方法,包括:
在结构衬底的一侧沉积形成缓冲层;
在所述缓冲层远离所述结构衬底的一侧沉积形成刻蚀阻挡势垒层;
在所述刻蚀阻挡势垒层远离所述结构衬底的一侧沉积形成上下倒置的N极性晶体管的外延功能层,以使所述外延功能层远离所述结构衬底的一侧为Ga极性面;
在所述外延功能层远离所述结构衬底的一侧键合形成支撑衬底;
去除所述结构衬底,并暴露出所述缓冲层;
去除所述缓冲层,并暴露出所述刻蚀阻挡势垒层;
在所述外延功能层远离所述支撑衬底的一侧制作源极、漏极和栅极,以形成N极性GaN晶体管。
在可选的实施方式中,去除所述缓冲层,并暴露出所述刻蚀阻挡势垒层的步骤,所述制备方法还包括:
去除所述刻蚀阻挡势垒层,并暴露出所述外延功能层。
在可选的实施方式中,在所述刻蚀阻挡势垒层远离所述结构衬底的一侧沉积形成上下倒置的N极性晶体管的外延功能层的步骤,包括:
在所述刻蚀阻挡势垒层上沉积形成Ga极性的沟道层;
在所述沟道层上沉积形成Ga极性的势垒层;
在所述势垒层上沉积形成Ga极性的隔离层;
在所述隔离层上沉积形成Ga极性的绝缘层。
在可选的实施方式中,在所述隔离层上沉积形成绝缘层的步骤之后,所述制备方法还包括:
在所述绝缘层上沉积形成p型掺杂层。
在可选的实施方式中,在所述外延功能层远离所述结构衬底的一侧键合形成支撑衬底的步骤,包括:
在所述外延功能层上沉积形成键合层;
将所述支撑衬底键合在所述键合层上。
在可选的实施方式中,所述刻蚀阻挡势垒层为AlxGa1-xN,其中x为Al的组分,且0<x≤1。
在可选的实施方式中,所述刻蚀阻挡势垒层的厚度为至少为1nm。
第二方面,本发明提供一种半导体结构,采用如前述实施方式任一项所述的N极性GaN晶体管结构的制备方法制作而成,包括:
刻蚀阻挡势垒层;
位于所述刻蚀阻挡势垒层一侧的外延功能层,其中所述外延功能层的靠近所述刻蚀阻挡势垒层的一侧为N极性面,所述外延功能层远离所述刻蚀阻挡势垒层的一侧为Ga极性面;
位于所述外延功能层的Ga极性面一侧的支撑衬底;
位于所述外延功能层的N极性面一侧的源极、漏极和栅极;
其中,所述外延功能层包括在所述刻蚀阻挡势垒层上沉积形成的沟道层、在所述沟道层上沉积形成的势垒层、在所述势垒层上沉积形成的隔离层以及在所述隔离层上沉积形成的绝缘层。
在可选的实施方式中,所述外延功能层还包括位于所述绝缘层上设p型掺杂层。
本发明实施例的有益效果包括,例如:
本发明实施例提供的N极性GaN晶体管结构的制备方法,通过沉积形成Ga极性的外延功能层,并在外延功能层上键合形成支撑衬底,然后将该外延结构倒置后去除结构衬底和缓冲层,在暴露出的外延功能层远离支撑衬底的一侧制作源极、漏极和栅极,以形成N极性GaN晶体管。其中,由于N极性GaN晶体管的外延结构由直接生长的Ga极性外延层上下倒置获得,其材料质量相比直接外延生长的N极性材料更高,能够得到高电阻的GaN绝缘层和陡峭界面的异质结,因而可增强N极性GaN晶体管的耐高压能力、减小器件导通损耗。相较于现有技术,本发明采用先生长Ga极性外延结构再通过键合和衬底及缓冲层去除的方法,可解决直接外延生长N极性GaN晶体管结构材料质量差的难题,提升N极性晶体管的整体工作性能。
附图说明
为了更清楚地说明本发明实施例的技术方案,下面将对实施例中所需要使用的附图作简单地介绍,应当理解,以下附图仅示出了本发明的某些实施例,因此不应被看作是对范围的限定,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他相关的附图。
图1为本发明实施例提供的N极性GaN晶体管结构的制备方法的步骤框图;
图2至图6为本发明实施例提供的N极性GaN晶体管结构的制备方法的工艺流程图;
图7为本发明实施例提供的半导体结构的结构示意图;
图8为本发明实施例提供的半导体结构与其他器件的集成结构示意图。
图标:100-半导体结构;110-支撑衬底;111-键合层;130-外延功能层;131-沟道层;133-势垒层;135-隔离层;137-绝缘层;139-p型掺杂层;150-刻蚀阻挡势垒层;160a-源极;160b-漏极;160c-栅极;170-缓冲层;180-结构衬底。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。通常在此处附图中描述和示出的本发明实施例的组件可以以各种不同的配置来布置和设计。
因此,以下对在附图中提供的本发明的实施例的详细描述并非旨在限制要求保护的本发明的范围,而是仅仅表示本发明的选定实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
应注意到:相似的标号和字母在下面的附图中表示类似项,因此,一旦某一项在一个附图中被定义,则在随后的附图中不需要对其进行进一步定义和解释。
在本发明的描述中,需要说明的是,若出现术语“上”、“下”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系,或者是该发明产品使用时惯常摆放的方位或位置关系,仅是为了便于描述本发明和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本发明的限制。
此外,若出现术语“第一”、“第二”等仅用于区分描述,而不能理解为指示或暗示相对重要性。
正如背景技术中所公开的,得益于与传统Ga极性材料相反的极化电场,基于N极性材料的电子器件可具有更低的接触电阻、更强的耐高电压能力、更高的功率密度和效率、更灵活的结构设计优势和尺寸微缩优势。而直接生长的Ga极性GaN材料综合质量好,通常优于直接生长的N极性GaN材料,即采用Ga极性生长得到的GaN材料的表面粗糙度低、晶体质量好、杂质浓度低、背景电子浓度低。
现有技术中,N极性GaN材料通常是基于在蓝宝石或者SiC衬底上采用金属有机气相外延或者分子束外延的方法直接生长得到,这种方法得到的GaN材料表面粗糙度高、晶体质量差、杂质浓度高、背景电子浓度高,以制造N极性高电子迁移率晶体管所需要的高电阻绝缘层和陡峭的异质结界面,导致N极性的GaN材料优势难以在器件应用中完全发挥出来。
为了解决上述问题,本发明提供了一种N极性GaN晶体管结构的制备方法和半导体结构,能够得到具有高电阻GaN绝缘层和陡峭界面的异质结N极性GaN高电子迁移率晶体管,提升器件性能。需要说明的是,在不冲突的情况下,本发明的实施例中的特征可以相互结合。
具体实施例
参见图1,本实施例提供了一种N极性GaN晶体管结构的制备方法,采用先生长Ga极性外延结构,再通过键合和衬底及缓冲层170去除的方法,得到倒置后的N极性器件,并且使得N极性半导体器件具有更好的材料质量。
本实施例提供的N极性GaN晶体管结构的制备方法,用于制备形成半导体结构100,该半导体结构100适用于N极性GaN基高电子迁移率晶体管(HEMT,High Electron MobilityTransistor)器件。其中,基于该半导体结构100可以是增强型N极性GaN基HEMT结构,也可以是耗尽型N极性GaN基HEMT结构。其中,基于该半导体结构100制备形成的HEMT器件,其结构可参考现有的HEMT器件。
本实施例提供的N极性GaN晶体管结构的制备方法,包括以下步骤:
S1:在结构衬底180的一侧沉积形成缓冲层170。
结合参见图2,其中,结构衬底180可以是Si、Sapphire、SiC、GaN中的一种或多种的组合,或任何其他能够生长III族氮化物的材料。结构衬底180的沉积方法可以采用CVD(Chemical Vapor Deposition,化学气相沉积)、VPE(Vapour Phase Epitaxy,气相外延)、MOVPE(Metal-organic Vapor Phase Epitaxy,金属有机物气象外延生长)、LPCVD(LowPressure Chemical Vapor Deposition,低压力化学气相沉积)、PECVD(Plasma EnhancedChemical Vapor Deposition,等离子体增强化学气相沉积)、PLD(Pulsed LaserDeposition,脉冲激光沉积)、原子层外延、MBE(Molecular Beam Epitaxy,分子束外延)、溅射、蒸发等。
在本实施例中,结构衬底180优选采用Si(111)材料,从而方便后续制程中实现衬底剥离。
在本实施例中,缓冲层170在生长中作为后续GaN外延结构与结构衬底180之间的过渡层,解决GaN薄膜与结构衬底180材料间的晶格失配和热膨胀系数失配等问题。此处缓冲层170可以采用GaN、AlN、InAlN、AlGaN、InAlGaN或其它半导体材料中的至少一种材料。优选地,在结构衬底180采用Si(111)材料的基础上,缓冲层170可以采用AlGaN或AlN中的至少一种。
S2:在缓冲层170远离结构衬底180的一侧沉积形成刻蚀阻挡势垒层150。
在本实施例中,刻蚀阻挡势垒层150主要由于在后续刻蚀制程中起到阻挡作用,以形成自然阻挡层,以阻挡刻蚀。刻蚀阻挡势垒层150可以优选采用AlxGa1-xN,其中x为Al的组分,且0<x≤1。当然,此处刻蚀阻挡势垒层150需要缓冲层170靠近势垒层一侧的材料异质,以实现刻蚀缓冲层170时刻蚀阻挡势垒层150能够作为刻蚀停止层,且刻蚀阻挡势垒层150的材料选用仅仅是举例说明,并不起到限定作用,但凡是在此处能够实现刻蚀停止的作用的材料,均在本发明的保护范围之内。
需要说明是,为了避免刻蚀阻挡势垒层150影响后续的金属电极的制作,此处刻蚀阻挡势垒层150的厚度较薄。具体地,刻蚀阻挡势垒层150的厚度为至少1nm,优选为2nm。
S3:在刻蚀阻挡势垒层150远离结构衬底180的一侧沉积形成上下倒置的N极性晶体管的外延功能层130。
结合参见图3,具体地,利用常规的沉积方法,在刻蚀阻挡势垒层150上沉积形成上下倒置的N极性晶体管的外延功能层130。其中,外延功能层130包括依次沉积的沟道层131、势垒层133、隔离层135、绝缘层137和p型掺杂层139。同时,为了保证整个结构沉积过程中的统一性,缓冲层170和刻蚀阻挡势垒层150也均为Ga极性生长方式,且外延功能层130远离结构衬底180的一侧为Ga极性面,外延功能层130远离支撑衬底110的一侧为N极性面。
需要说明的是,本实施例中均采用MOVPE或MBE的方法直接依次生长出缓冲层170、刻蚀阻挡势垒层150和外延功能层130等外延结构。
在本实施例中,步骤S3具体包括以下子步骤:
S31:在刻蚀阻挡势垒层150上沉积形成Ga极性的沟道层131。
具体地,沟道层131用于提供二维电子气(2DEG)运动的沟道,沟道层131的制备材料包括氮化物,例如,包括GaN、AlN、InAlN、AlGaN、InAlGaN或其它半导体材料中的至少一种材料,优选地,沟道层131可以是GaN或者低Al组分的AlGaN材料。
S32:在沟道层131上沉积形成Ga极性的势垒层133。
具体地,势垒层133覆盖在沟道层131上,用于与沟道层131形成异质结,且势垒层133的制备材料包括三元氮化物,例如,包括AlN、InAlN、AlGaN、InAlGaN或其它半导体材料中的至少一种材料。此处势垒层133具有比沟道层131更宽的能隙,例如当沟道层131材料为GaN时,势垒层133可以选择InAlN、AlGaN或AlN。
S33:在势垒层133上沉积形成Ga极性的隔离层135。
具体地,隔离层135用于隔离势垒层133和后续沉积的绝缘层137,其可以是非故意掺杂生长的GaN材料。
S34:在隔离层135上沉积形成Ga极性的绝缘层137。
具体地,绝缘层137具有高电阻特性,可通过在GaN材料生长中碳的自掺杂或者铁的故意掺杂来实现。
需要说明的是,常规直接在衬底上生长的N极性GaN材料,由于背景电子浓度高,采用碳的自掺杂或铁的故意掺杂通常难以实现具有较高电阻的绝缘层。
S35:在绝缘层137上沉积形成p型掺杂层139。
具体地,p型掺杂层139可以采用常规的p-GaN材料,可以提高器件的纵向耐高压能力。
需要说明的是,此处p型掺杂层139为外延功能层130的最外层结构,在其他较佳的实施例中,也可以省去步骤S45,从而省去p型掺杂层139,使得绝缘层137作为外延功能层130的最外层结构。
在本实施例中,在倒置器件后,p型掺杂层139为外延功能层130的最外层结构,此时p型掺杂层139暴露在外,能够方便掺杂后的退火激活。例如,当p型掺杂层139为Mg掺杂的Ga(Al)N时,必须要暴露在高温下进行退火才能实现p型导电。如果按常规的直接在衬底上先生长N极性的p型掺杂层139再生长N极性晶体管的外延功能层130,则p型掺杂层139埋在外延功能层130下,使得退火难以激活掺杂源实现p型导电。
还需要说明的是,本实施例中步骤S41至步骤S45均采用MOVPE或MBE的方法直接生长出Ga极性的外延层结构,其中Ga极性方向由结构衬底180朝向p型掺杂层139。
S4:在外延功能层130远离结构衬底180的一侧键合形成支撑衬底110。
结合参见图4,具体而言,在外延功能层130上沉积形成键合层111,将支撑衬底110键合在键合层111上。即在p型掺杂层139远离结构衬底180的一侧表面沉积形成键合层111[10],通过直接键合或者胶接键合等方法将外延功能层130与支撑衬底110键合。支撑衬底110的材料可以为Si、SOI、碳化硅、金刚石等。同时,键合层111的材料的选择与键合工艺相关。例如当选择与SOI衬底直接键合时,键合层111可以采用氧化硅或者氮化硅材料。
需要说明的是,此处通过键合的方法,可以与导热性较高的材料(SiC、金刚石等)结合,从而提高了器件的散热能力和热学可靠性。此外,SOI衬底上还可以提前制备Si基CMOS器件等其他器件,本实施例中通过键合的方法,可实现Si的SOI衬底相结合,在SOI衬底上还可以集成Si基CMOS器件等其他器件,从而实现了不同器件的集成。
S5:去除结构衬底180,并暴露出缓冲层170。
结合参见图5,具体而言,在完成支撑衬底110的制作后,将器件倒置,并剥离结构衬底180。此时N极性方向由支撑衬底110朝向刻蚀阻挡势垒层150。通过剥离结构衬底180,暴露出缓冲层170的N极性面,结构衬底180的剥离方法与所选用的材料相关,例如结构衬底180采用Si(111),可直接通过化学腐蚀的方法去除。当然,此处也可以采用其他常规的衬底剥离方法,例如激光剥离。
S6:去除缓冲层170,并暴露出刻蚀阻挡势垒层150。
结合参见图6,具体而言,首先刻蚀去除缓冲层170,从而暴露出刻蚀阻挡,得到N极性GaN基HEMT器件结构,此处刻蚀阻挡势垒层150可以实现自终止刻蚀工艺。
需要说明的是,此处刻蚀阻挡势垒层150可以去除,也可以不去除。
S7:在外延功能层130远离支撑衬底110的一侧制作源极160a、漏极160b和栅极160c。
结合参见图7,具体地,当刻蚀阻挡势垒层150去除后,在沟道层131远离支撑衬底110的一侧表面按照常规工艺制作源极160a、漏极160b和栅极160c,其中栅极160c位于源极160a和漏极160b之间。当刻蚀阻挡势垒层150未去除时,则在刻蚀阻挡势垒层150的表面制作源极160a、漏极160b和栅极160c。
需要说明的是,制作完成金属电极后,即得到N极性的N极性GaN基HEMT结构,其可以根据金属电极的制作差别而形成增强型N极性GaN基HEMT结构或耗尽型N极性GaN基HEMT结构。当形成耗尽型N极性GaN基HEMT结构,优选需去除刻蚀阻挡势垒层150。
还需要说明的是,当此处未去除刻蚀阻挡势垒层150时,该层还可以作为制作源极160a、漏极160b和栅极160c是减小器件漏电的势垒间层。
请继续参见图7,本实施例还提供了一种半导体结构100,采用如前述的N极性GaN晶体管结构的制备方法制作而成,该半导体结构100包括刻蚀阻挡势垒层150、位于刻蚀阻挡势垒层150一侧的外延功能层130、位于外延功能层130的Ga极性面一侧的支撑衬底110、位于外延功能层130的N极性面一侧的源极160a、漏极160b和栅极160c,其中外延功能层130的靠近刻蚀阻挡势垒层150的一侧为N极性面,外延功能层130远离刻蚀阻挡势垒层150的一侧为Ga极性面。
具体地,本实施例中的半导体结构100为N极性GaN基HEMT结构,其中N极性方向由支撑衬底110朝向外延功能层130。
在本实施例中,外延功能层130包括沟道层131、势垒层133、隔离层135、绝缘层137和p型掺杂层139,其中p型掺杂层139键合在支撑衬底110上,p型掺杂层139与支撑衬底110之间还形成有键合层111,以实现键合。绝缘层137位于p型掺杂层139远离支撑衬底110的一侧,隔离层135位于绝缘层137远离支撑衬底110的一侧,势垒层133位于隔离层135远离支撑衬底110的一侧,沟道层131位于势垒层133远离支撑衬底110的一侧。此处外延功能层130的具体沉积方法可参考前述说明。
在本实施例其他实施例中,也可以将刻蚀阻挡势垒层150去除,即该半导体结构100包括外延功能层130、位于外延功能层130的Ga极性面一侧的支撑衬底110、位于外延功能层130的N极性面一侧的源极160a、漏极160b和栅极160c。即能够直接在沟道层131的表面制备形成源极160a、漏极160b和栅极160c。
参见图8,在本实施例中,外延功能层130键合在支撑衬底110上,同时支撑衬底110上还集成有Si基CMOS器件或栅极160c驱动电路,从而能够实现不同器件之间的集成。
综上所述,本实施例提供了一种N极性GaN晶体管结构的制备方法和半导体结构100,通过沉积形成Ga极性的外延功能层130,并在外延功能层130上键合形成支撑衬底110,然后将该外延结构倒置后去除结构衬底180和缓冲层170,在暴露出的外延功能层130远离支撑衬底110的一侧制作源极160a、漏极160b和栅极160c,以形成半导体器件。其中,由于采用了Ga极性生长形成外延功能层130,而直接生长的Ga极性GaN材料综合质量通常优于直接生长的N极性GaN材料,故通过直接生长Ga极性的外延功能层130,能够得到表面光滑、低杂质浓度、高晶体质量的GaN材料,而由于半导体结构100的N极性与Ga极性方向相反,通过倒置后去除结构衬底180和缓冲层170的方式,得到N极性面的外延功能层130,从而得到N极性的外延结构,并制作形成N极性的半导体器件。本实施例采用先生长Ga极性外延结构再通过键合和衬底及缓冲层170去除的方法,使得N极性半导体器件具有更好的材料质量和器件性能。
以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到的变化或替换,都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应以所述权利要求的保护范围为准。
Claims (9)
1.一种N极性GaN晶体管结构的制备方法,其特征在于,包括:
在结构衬底的一侧沉积形成缓冲层;
在所述缓冲层远离所述结构衬底的一侧沉积形成刻蚀阻挡势垒层;
在所述刻蚀阻挡势垒层远离所述结构衬底的一侧沉积形成上下倒置的N极性晶体管的外延功能层,以使所述外延功能层远离所述结构衬底的一侧为Ga极性面;
在所述外延功能层远离所述结构衬底的一侧键合形成支撑衬底;
去除所述结构衬底,并暴露出所述缓冲层;
去除所述缓冲层,并暴露出所述刻蚀阻挡势垒层;
在所述外延功能层远离所述支撑衬底的一侧制作源极、漏极和栅极,以形成N极性GaN晶体管。
2.根据权利要求1所述的N极性GaN晶体管结构的制备方法,其特征在于,去除所述缓冲层,并暴露出所述刻蚀阻挡势垒层的步骤之后,所述制备方法还包括:
去除所述刻蚀阻挡势垒层,并暴露出所述外延功能层。
3.根据权利要求1所述的N极性GaN晶体管结构的制备方法,其特征在于,在所述刻蚀阻挡势垒层远离所述结构衬底的一侧沉积形成上下倒置的N极性晶体管的外延功能层的步骤,包括:
在所述刻蚀阻挡势垒层上沉积形成Ga极性的沟道层;
在所述沟道层上沉积形成Ga极性的势垒层;
在所述势垒层上沉积形成Ga极性的隔离层;
在所述隔离层上沉积形成Ga极性的绝缘层。
4.根据权利要求3所述的N极性GaN晶体管结构的制备方法,其特征在于,在所述隔离层上沉积形成绝缘层的步骤之后,所述制备方法还包括:
在所述绝缘层上沉积形成p型掺杂层。
5.根据权利要求1所述的N极性GaN晶体管结构的制备方法,其特征在于,在所述外延功能层远离所述结构衬底的一侧键合形成支撑衬底的步骤,包括:
在所述外延功能层上沉积形成键合层;
将所述支撑衬底键合在所述键合层上。
6.根据权利要求1所述的N极性GaN晶体管结构的制备方法,其特征在于,所述刻蚀阻挡势垒层为AlxGa1-xN,其中x为Al的组分,且0<x≤1。
7.根据权利要求6所述的N极性GaN晶体管结构的制备方法,其特征在于,所述刻蚀阻挡势垒层的厚度为至少为1nm。
8.一种半导体结构,采用如权利要求1-7任一项所述的N极性GaN晶体管结构的制备方法制作而成,其特征在于,包括:
刻蚀阻挡势垒层;
位于所述刻蚀阻挡势垒层一侧的外延功能层,其中所述外延功能层的靠近所述刻蚀阻挡势垒层的一侧为N极性面,所述外延功能层远离所述刻蚀阻挡势垒层的一侧为Ga极性面;
位于所述外延功能层的Ga极性面一侧的支撑衬底;
位于所述外延功能层的N极性面一侧的源极、漏极和栅极;
其中,所述外延功能层包括在所述刻蚀阻挡势垒层上沉积形成的沟道层、在所述沟道层上沉积形成的势垒层、在所述势垒层上沉积形成的隔离层以及在所述隔离层上沉积形成的绝缘层。
9.根据权利要求8所述的一种半导体结构,其特征在于,所述外延功能层还包括位于所述绝缘层上设p型掺杂层。
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