CN113470709A

CN113470709A - Temperature sensing circuit and sensing method thereof

Info

Publication number: CN113470709A
Application number: CN202010247617.9A
Authority: CN
Inventors: 佐藤贵彦
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2020-03-31
Filing date: 2020-03-31
Publication date: 2021-10-01
Anticipated expiration: 2040-03-31
Also published as: CN113470709B

Abstract

In one aspect of the present invention, a temperature sensing circuit and a sensing method are provided, the sensing circuit is suitable for a memory device. The temperature sensing circuit comprises an oscillator, a counting circuit, a control circuit, a sensing circuit and a selection circuit. The oscillator provides an oscillating signal. The counting circuit counts the oscillation signal to generate a first counting signal and generates a second counting signal. The control circuit performs logic operation on the second counting signal to generate an enabling signal and a sensing adjustment signal. The sensing circuit divides the reference voltage according to the sensing adjustment signal to generate a reference temperature voltage, and compares the reference temperature voltage with the monitoring voltage according to the enabling signal to generate a determination signal. The selection circuit dynamically selects one of the oscillation signal and the first count signal according to the determination signal, and generates a pulse of the refresh request signal according to the dynamically selected one of the oscillation signal and the first count signal.

Description

Temperature sensing circuit and sensing method thereof

Technical Field

The present invention relates to a memory device, and more particularly, to a temperature sensing circuit for providing a refresh request signal and a sensing method thereof.

Background

A Dynamic Random Access Memory (DRAM) includes a plurality of memory cells (memory cells) for storing bits of data, each bit being determined according to a level of a voltage potential accumulated on a capacitor of the memory cell. The charge accumulated on the capacitor is gradually discharged to cause difficulty in the determination of the potential after a certain period of time. The period from when the charge on the capacitor starts to discharge to when the logic potential ("0" or "1") of the data cannot be determined with certainty is called a refresh time. The refresh request signal must be provided at intervals shorter than the refresh time to refresh (refresh) the memory cells and retain (hold) the data. And the refresh interval (refresh interval) refers to a time interval between two refresh request signals.

In a DRAM, memory cells have different retention times (retention times) with respect to different temperatures, thereby accommodating different refresh intervals. For example, when the temperature of the DRAM memory cell is reduced from 55 ℃ to 20 ℃, the retention time is increased by about 4 times, which is suitable for 4 times of refresh interval. Thus, the prior art utilizes multiple temperature thresholds to divide the operating temperature into multiple zones, each zone having a different refresh interval. The operating temperature is divided into three temperature zones, for example, using two temperature thresholds of 55 ℃ and 20 ℃: more than 55 ℃, less than 55 ℃ and more than 20 ℃, and less than 20 ℃, and the time interval of the temperature section of less than 55 ℃ and more than 20 ℃ is adjusted to be 4 times of the temperature section of more than 55 ℃, and the time interval of less than 20 ℃ is adjusted to be 16 times of the temperature section of more than 55 ℃, so as to provide the refresh request signals of different refresh intervals according to different temperatures.

However, current consumption of the prior art slightly above the temperature threshold increases. For example, in a temperature slightly higher than 55 ℃ but not changing the refresh interval, and a temperature slightly higher than 20 ℃ but not changing the refresh interval, since the refresh interval has not changed, the refresh frequency of the refresh request signal is 4 times higher than 55 ℃ and 20 ℃, respectively, resulting in larger refresh current consumption. Alternatively, more temperature thresholds are used to divide the operating temperature into more temperature segments, however, more counters, temperature sensing circuits and selectors are required to be added to the circuit. In addition to increasing cost, more counters will also cause the counter bits to be reduced, resulting in a lower refresh interval resolution.

Disclosure of Invention

Therefore, the present invention provides a temperature sensing circuit capable of providing an average refresh interval corresponding to a temperature with high resolution without increasing a clock frequency and current consumption.

In one aspect of the present invention, a temperature sensing circuit is provided for use in a memory device. The temperature sensing circuit comprises an oscillator, a counting circuit, a control circuit, a sensing circuit and a selection circuit. The oscillator is used for providing an oscillation signal. The counting circuit is coupled to the oscillator, and is used for counting the oscillation signal to generate a first counting signal and generating a second counting signal. The control circuit is coupled to the counting circuit and used for performing logic operation on the second counting signal to generate an enabling signal and a sensing adjustment signal. The sensing circuit is coupled with the control circuit, divides the reference voltage according to the sensing adjustment signal to generate a reference temperature voltage, and compares the reference temperature voltage with the monitoring voltage according to the enabling signal to generate a decision signal. The selection circuit is coupled to the oscillator, the counting circuit and the sensing circuit, dynamically selects one of the oscillation signal and the first counting signal according to the decision signal, and generates a pulse of the refresh request signal according to the dynamically selected one of the oscillation signal and the first counting signal.

In another aspect of the present invention, a sensing method is provided for a memory device. The storage device has a temperature sensing circuit having an oscillator, a counting circuit, a control circuit, a sensing circuit and a selection circuit. The sensing method comprises the following steps: providing an oscillating signal; the oscillation signal is counted to generate a first count signal and a second count signal. The second counting signal is logically operated to generate an enabling signal and a sensing adjustment signal. The reference voltage is divided according to the sensing adjustment signal to generate a reference temperature voltage, and the reference temperature voltage is compared with the monitoring voltage according to the enabling signal to generate a decision signal. One of the oscillation signal and the first count signal is dynamically selected according to the determination signal, and the pulse of the refresh request signal is generated according to the dynamically selected one of the oscillation signal and the first count signal.

Based on the above, the temperature sensing circuit of the present invention can dynamically adjust the ratio of the pulses with different refresh interval times in the refresh request signal according to the temperature of the memory cell to provide a high average refresh interval and a high resolution of the average refresh interval with respect to the temperature without increasing the clock frequency and the current consumption.

In order to facilitate an understanding of the foregoing features and advantages of the invention, exemplary embodiments are described below with reference to the accompanying drawings. It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the invention as claimed.

It should be understood, however, that this summary may not contain all aspects and embodiments of the disclosure, and is therefore not meant to be limiting or restrictive in any way. In addition, the present invention will encompass improvements and modifications apparent to those skilled in the art.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.

FIG. 1 is a block diagram of a temperature sensing circuit according to an embodiment of the present invention;

FIG. 2 is a circuit diagram of a temperature sensing circuit according to an embodiment of the present invention;

FIG. 3 is a control timing diagram of the temperature sensing circuit according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating a conversion table of the count signal CNT _ N and the sensing adjustment signal ST in the control circuit according to an embodiment of the present invention;

FIG. 5 is a timing diagram illustrating the generation of refresh request signals according to one embodiment of the present invention;

FIG. 6A is a table illustrating an estimated average interval statistic for refresh requests, in accordance with one embodiment of the present invention;

FIG. 6B is an X-Y plot of an estimated average interval of refresh requests versus temperature, in accordance with one embodiment of the present invention;

FIG. 7 is a block diagram of a temperature sensing circuit according to another embodiment of the present invention;

FIG. 8 is a circuit diagram of a temperature sensing circuit according to another embodiment of the present invention;

FIG. 9 is a timing diagram of a temperature sensing circuit according to another embodiment of the present invention;

FIG. 10A is a table illustrating an estimated average interval statistic for refresh requests, in accordance with another embodiment of the present invention;

FIG. 10B is an X-Y plot of an estimated average interval of refresh requests versus temperature, shown in accordance with another embodiment of the present invention;

FIG. 11A is a table illustrating an estimated average interval statistic for refresh requests in accordance with yet another embodiment of the present invention; FIG. 11B is an X-Y plot of an estimated average interval of refresh requests versus temperature, shown in accordance with yet another embodiment of the present invention;

FIG. 12 is a flow chart illustrating a method of operating a temperature sensing circuit according to an embodiment of the invention.

Description of the reference numerals

10. 20: temperature sensing circuit

110: oscillator

120: counting circuit

130: control circuit

140: sensing circuit

150: selection circuit

210-230: counter with a memory

240: voltage divider circuit

250: switch string

251 to 252: selector device

260: monitoring voltage generating circuit

270: comparator with a comparator circuit

280: latch device

CNT _1, CNT _ N, CNT _ 4: counting signal

COUNT: refresh pulse counting

D1: diode with a high-voltage source

DET: determining a signal

EN: enabling signal

GND: ground voltage

IC: current source

OSC: oscillating signal

R1-R8: voltage dividing resistor

REFREQ: refresh request signal

S1210-S1250: step (ii) of

ST: sensing an adjustment signal

And (4) SUM: sum of refresh pulses

SW 1-SW 7: switch with a switch body

T0-T3: time of day

VC: compared voltage

VMON: monitoring voltage

VREF: reference voltage

VRT: reference temperature voltage VT 20-VT 80: default temperature voltage

Detailed Description

Referring to fig. 1, a temperature sensing circuit 10 is adapted for use in a memory device (not shown). The temperature sensing circuit 10 includes an oscillator 110, a counting circuit 120, a control circuit 130, a sensing circuit 140, and a selection circuit 150. In this embodiment, the temperature sensing circuit 10 is configured to provide a refresh request signal REFREQ to a refresh circuit (not shown) in the memory device to drive the refresh circuit to refresh memory cells (not shown) in the memory device. In the present invention, the temperature sensing circuit 10 counts the oscillation signal OSC to generate the reference temperature voltage VRT corresponding to each temperature of the memory cell, and dynamically adjusts the average refresh interval of the refresh request signal REFREQ by comparing the monitor voltage VMON corresponding to the current temperature of the memory cell with the reference temperature voltage VRT corresponding to each temperature, so that the refresh request signal REFREQ has a relatively high average refresh interval and provides a refresh interval having high resolution with respect to temperature without increasing the frequency of the oscillation signal OSC.

Please refer to fig. 1 and fig. 2 simultaneously. The oscillator 110 is used for providing an oscillation signal OSC to the counting circuit 120 and the selection circuit 150. In an embodiment, the oscillator 110 may be a conventional voltage-controlled oscillator (VCO), and the oscillation signal OSC may be a pulse signal with a fixed frequency, but the invention is not limited thereto.

The counting circuit 120 is coupled to the oscillator 110, and the counting circuit 120 receives the oscillation signal OSC and counts the oscillation signal OSC to generate the counting signals CNT _1 and CNT _ N. In an embodiment, the counting circuit 120 may count the number of pulses of the oscillation signal OSC, and the counting circuit 120 may be a conventional synchronous counter or other counters, but the invention is not limited thereto. Specifically, in one embodiment, the counting circuit 120 includes counters 210-230.

The counter 210 is coupled to the oscillator 110 for receiving and counting the number of pulses of the oscillation signal OSC to generate a count signal CNT _ 4. In one embodiment, the counter 210 generates one pulse of the count signal CNT _4 every time it counts 4 rising edges of the oscillation signal OSC, so that the period of the count signal CNT _4 is 4 times the period of the oscillation signal OSC. And the count of the counter 210 is returned to 0 each time the counter 210 counts 4 pulses of the oscillation signal OSC.

The counter 220 is coupled between the counter 210 and the selection circuit 150 for receiving and counting the number of pulses of the count signal CNT _4 to generate the count signal CNT _ 1. In one embodiment, the counter 220 generates one pulse of the count signal CNT _1 every time it counts 4 rising edges of the count signal CNT _4, so that the period of the count signal CNT _1 is 4 times that of the count signal CNT _4, and the period of the count signal CNT _1 is 16 times that of the oscillation signal OSC. And the count of the counter 210 is returned to 0 each time the counter 220 counts 4 count signals CNT _ 4.

The counter 230 is configured to receive and count a number of pulses of the oscillation signal OSC to generate the count signal CNT _ N. In one embodiment, the counter 230 generates one pulse of the count signal CNT _ N every time it counts N rising edges of the oscillation signal OSC, so that the period of the count signal CNT _ N is N times the period of the oscillation signal OSC. And the count of the counter 230 is returned to 0 each time the counter 230 counts N oscillation signals OSC. In one embodiment, N may be a multiple of 16, such as 16, 64.

It should be noted that the

counters

210 and 220 are used to assist the selection circuit 150 in adjusting the refresh interval of the refresh request signal REFREQ, and the counter 230 is used to generate the selected reference temperature voltage VRT through the control circuit 130, which will be described in detail later. In addition, the invention does not limit the way of the counters 210-230 to count signals.

The control circuit 130 is coupled to the counting circuit 120. in one embodiment, the control circuit 130 can be a central processing unit, a microprocessor, an application specific integrated circuit, a field programmable logic gate array, or the like, or a combination thereof. Wherein the control circuit 130 is programmed to perform the functions or steps that will be described below: the control circuit 130 receives the count signal CNT _ N and performs a logic operation on the count signal CNT _ N to generate an enable signal EN and a sensing adjustment signal ST.

In one embodiment, when the control circuit 130 detects that the number of pulses of the oscillation signal OSC is equal to a predetermined number according to the count signal CNT _ N, the control circuit 130 enables (enable) the enable signal EN and provides the enable signal EN to the sensing circuit 140. Specifically, in one embodiment, each time the control circuit 130 receives a pulse of the count signal CNT _ N, i.e., when the counter 230 counts 16 pulses of the oscillation signal OSC, the control circuit 130 enables the enable signal EN provided to the sensing circuit 140 to be at a high logic level (high logic level) so as to enable the sensing circuit 140.

Referring to fig. 2 and 4, in an embodiment, the control circuit 130 performs a logic conversion on the count signal CNT _ N according to a default conversion table, such as fig. 4, to generate the sensing adjustment signal ST, wherein a logic value of the sensing adjustment signal ST corresponds to a plurality of default temperatures of the memory. Specifically, referring to fig. 4, in an embodiment, the count signal CNT _ N has 4 bits, i.e., bit 0A-bit 3A, and the sensing adjustment signal ST has 3 bits, i.e., bit 0B-bit 2B. For example, when the count signal CNT _ N is 6, that is, 0110, the control circuit 130 performs a logic conversion on the count signal CNT _ N according to fig. 4 to obtain the values of bit 0A-bit 2A of the count signal CNT _ N to generate the sensing adjustment signal ST, so that the sensing adjustment signal ST is 6 (that is, 110). When the count signal CNT _ N is 7, that is, 0111, the control circuit 130 performs a logic conversion on the count signal CNT _ N according to fig. 4, and takes the values of bit 0A-bit 2A of the count signal CNT _ N, that is, 111, to generate the sensing adjustment signal ST, but the logic conversion defaults to convert 111 to 000, so that the sensing adjustment signal ST is 0 (that is, 000).

Referring to the conversion table of fig. 4 and the timing sequence of the count signal CNT _ N and the sensing adjustment signal ST in fig. 5, the logic value of each count signal CNT _ N corresponds to the logic value of the sensing adjustment signal ST. In one embodiment, when the count signal CNT _ N is 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, the control circuit 130 performs a logic operation to generate the sensing adjustment signal ST to be 0, 1, 2, 3, 4, 5, 6, 0, 1, 2, 3, 0, 1, 0. However, the invention is not limited thereto.

Referring to fig. 2, the sensing circuit 140 is coupled to the control circuit 130 and receives the enable signal EN, the sensing adjustment signal ST and the reference voltage VREF. The sensing circuit 140 divides the reference voltage VREF according to the sensing adjustment signal ST to generate the reference temperature voltage VRT, and the sensing circuit 140 compares the reference temperature voltage VRT with the monitor voltage VMON according to the enable signal EN to generate the determination signal DET. In one embodiment, the sensing circuit 140 includes a voltage divider circuit 240, a switch string 250, a monitor voltage generation circuit 260, a comparator 270, and a latch 280.

Specifically, the sensing circuit 140 may divide the reference voltage VREF by the voltage dividing circuit 240 and turn on one of the switches in the switch string 250 according to the sensing adjustment signal ST to generate the reference temperature voltage VRT. The sensing circuit 140 can generate the monitor voltage VMON through the monitor voltage generating circuit 260, and enable the comparator 250 through the enable signal EN to compare the reference temperature voltage VRT with the monitor voltage VMON, and generate the compared voltage VC according to the comparison result and provide the compared voltage VC to the latch 280. The sensing circuit 140 latches (latch) the compared voltage VC through the latch 280 to generate the determination signal DET and provides it to the selection circuit 150.

The voltage dividing circuit 240 has a plurality of voltage dividing resistors R1-R8 connected in series, wherein the voltage dividing resistors R1-R8 are coupled between the reference voltage VREF and the ground voltage GND, and generate a plurality of default temperature voltages VT 20-VT 80 by dividing the voltage difference between the reference voltage VREF and the ground voltage GND. The divided voltage between the voltage dividing resistors R1 and R2 is a default temperature voltage VT20, the divided voltage between the voltage dividing resistors R2 and R3 is a default temperature voltage VT30, the divided voltage between the voltage dividing resistors R3 and R4 is a default temperature voltage VT40, the divided voltage between the voltage dividing resistors R4 and R5 is a default temperature voltage VT50, the divided voltage between the voltage dividing resistors R5 and R6 is a default temperature voltage V60, the divided voltage between the voltage dividing resistors R6 and R7 is a default temperature voltage VT70, and the divided voltage between the voltage dividing resistors R7 and R8 is a default temperature voltage VT 80.

The switch string 250 is coupled to the control circuit 130 and the voltage divider circuit 240, and has a plurality of switches SW 1-SW 7. The first end of each of the switches SW 1-SW 7 receives one of the default temperature voltages VT 20-VT 80. In one embodiment, the first terminal of the switch SW1 receives the default temperature voltage VT20, the first terminal of the switch SW2 receives the default temperature voltage VT30, the first terminal of the switch SW3 receives the default temperature voltage VT40, the first terminal of the switch SW4 receives the default temperature voltage VT50, the first terminal of the switch SW5 receives the default temperature voltage VT60, the first terminal of the switch SW6 receives the default temperature voltage VT70, and the first terminal of the switch SW7 receives the default temperature voltage VT 80. The second terminals of all of the switches SW 1-SW 7 are coupled to each other. The switch string 250 turns on one of the switches SW 1-SW 7 according to the sensing adjustment signal ST, and provides one of the default temperature voltages VT 20-VT 80 corresponding to the turned-on one of the switches SW 1-SW 7 to the second ends of the switches SW 1-SW 7, so as to generate the reference temperature VRT. In one embodiment, when the switch SW1 is turned on, the reference temperature voltage VRT is equal to the default temperature voltage VT20, and so on. In one embodiment, the correspondence between the logic value of the sensing adjustment signal ST and the reference temperature voltage VRT is VRT [10 × 8-i ] ═ ST [ i ], and i is 0-6. For example, when i is 0, VRT [80]) ST [0 ]. In one embodiment, the detailed correspondence relationship between the logic value of the sensing adjustment signal ST and the reference temperature voltage VRT is as the following table one.

< TABLE I >

ST	0	1	2	3	4	5	6
								VRT	VT	80	VT 70	VT 60	VT 50	VT 40	VT 30	VT 20

The monitor voltage generating circuit 260 is used for providing a monitor voltage VMON. In one embodiment, the monitor voltage generating circuit 260 includes a constant current source IC and a diode D1. The constant current source IC is used for providing a constant current, and the diode D1 is coupled between the constant current source IC and the ground voltage GND for generating the monitor voltage VMON according to the constant current. The present invention is not limited to the type of current source IC.

The comparator 270 is coupled to the switch string 250 and the monitor voltage generating circuit 260, and is used for comparing the reference temperature voltage VRT with the monitor voltage VMON according to the enable signal EN so as to generate the compared voltage VC. In one embodiment, the comparator 270 has a positive input terminal, a negative input terminal, an enable terminal, and an output terminal. The positive input terminal of the comparator 270 is coupled to the monitor voltage generating circuit 260 to receive the monitor voltage VMON, and the negative input terminal of the comparator 270 is coupled to the switch string 250 to receive the reference temperature voltage VRT. The enable terminal of the comparator 270 is coupled to the control circuit 130 for receiving an enable signal EN to determine whether to perform the comparison operation. When the enable signal EN is disabled (e.g., at a low logic level), the comparator 270 does not compare the reference temperature voltage VRT with the monitor voltage VMON. When the enable signal EN is enabled (e.g., at a high logic level), the comparator 270 compares the reference temperature voltage VRT with the monitor voltage VMON, and outputs a comparison result as the compared voltage VC. When the monitor voltage VMON is less than the reference temperature voltage VRT, the comparator 270 outputs a disabled compared voltage VC (e.g., a low logic level). When the monitor voltage VMON is greater than the reference temperature VRT, the comparator 270 outputs an enabled compared voltage VC (e.g., a high logic level).

The latch 280 is coupled to the comparator 270 for latching the compared voltage VC to generate the determination signal DET and provide the determination signal DET to the selection circuit 150. In one embodiment, when the enable signal EN is disabled, the latch 280 takes the hold state as the determination signal DET and outputs the determination signal DET to the selection circuit 150. When the enable signal EN is enabled, the latch 280 latches the comparison voltage VC and outputs the refresh determination signal DET to the selection circuit 150.

Referring to fig. 1 and 2, the selection circuit 150 is coupled to the oscillator 110, the counting circuit 120 and the sensing circuit 140, and the selection circuit 150 dynamically selects one of the oscillation signal OSC and the counting signal CNT _1 according to the determination signal DET, and generates a pulse of the refresh request signal REFREQ according to the dynamically selected oscillation signal OSC and the counting signal CNT _ 1. In one embodiment, the selection circuit 150 includes

selectors

251 and 252, the selector 251 is coupled between the oscillator 110 and the sensing circuit 140, and the selector 252 is coupled between the counting circuit 120 and the sensing circuit 140. The

selectors

251 and 252 are alternately activated according to the logic level of the determination signal DET to jointly generate the refresh request signal REFREQ, which is described later.

In one embodiment, when the determination signal DET is enabled, the selector 251 outputs a pulse of the oscillation signal OSC and the selector 252 does not output a signal, and when the determination signal DET is disabled, the selector 252 outputs a pulse of the count signal CNT _1 and the selector 251 does not output a signal, so as to jointly generate the refresh request signal REFREQ.

FIG. 3 is a control timing diagram of the temperature sensing circuit according to an embodiment of the invention. Referring to fig. 2 and 3, in an embodiment, the period of the count signal CNT _4 is 4 times of the oscillation signal OSC, the period of the count signal CNT _1 is 4 times of the count signal CNT _4, and the period of the count signal CNT _ N is 4 times of the count signal CNT _ 1. Therefore, in one embodiment, the period of the count signal CNT _ N is 64 times the period of the oscillation signal OSC. The control circuit 130 logically converts the count signal CNT _ N according to the conversion table of fig. 4 to generate the sensing adjustment signal ST. The switch string 250 of the sensing circuit 140 turns on one of the switches SW 1-SW 7 according to the sensing adjustment signal ST to receive one of the default temperature voltages VT 20-VT 80 and generate the reference temperature voltage VRT. Taking fig. 3 as an example, the timing sequence from left to right, the value of the reference temperature voltage VRT is equal to the default temperature voltages VT60, VT50, VT80 and VT70 in sequence. The monitor voltage generation circuit 260 in the sensing circuit 140 generates the monitor voltage VMON. In this embodiment, the monitor voltage VMON corresponds to a default temperature voltage VT55 (not shown) between the default temperature voltages VT60 and VT 50.

Between time T0 and time T1, the enable signal EN is disabled, the comparator 270 does not compare the reference temperature voltage VRT with the monitor voltage VMON, and the determination signal DET is disabled (e.g., at a low logic level).

At time T1, the enable signal EN is enabled, and the comparator 270 compares the reference temperature voltage VRT with the monitor voltage VMON. Since the reference temperature voltage VRT (equal to VT50 at this time) is greater than the monitor voltage VMON, the comparator 270 generates the enabled compared voltage VC (not shown), and the latch 280 generates the enabled determination signal DET (e.g., a high logic level) since the enable signal EN is enabled.

Then, between time T1 and time T2, since the enable signal EN is disabled, the comparator 270 does not compare the reference temperature voltage VRT with the monitor voltage VMON, and the latch 280 latches the previously enabled compared voltage VC, so that the latch 280 maintains the logic level of the enabled determination signal DET.

At time T2, the enable signal EN is enabled, and the comparator 270 compares the reference temperature voltage VRT with the monitor voltage VMON. Since the reference temperature voltage VRT (equal to VT80 at this time) is less than the monitor voltage VMON, the comparator 270 generates the disabled compared voltage VC (not shown), and since the enable signal EN is enabled, the latch 280 generates the disabled decision signal DET.

Next, between the time T2 and the time T3, since the enable signal EN is disabled, the comparator 270 does not compare the reference temperature voltage VRT with the monitor voltage VMON, and the latch 280 latches the previously disabled compared voltage VC, so that the latch 280 maintains the logic level of the disabled determination signal DET.

Referring to fig. 2 and 3, the selection circuit 150 dynamically selects one of the oscillation signal OSC and the count signal CNT _1 according to the determination signal DET, and generates the refresh request signal REFREQ according to the dynamically selected one of the oscillation signal OSC and the count signal CNT _ 1. For example, between the time T0 and the time T1, the determination signal DET is disabled, so the selector 252 in the selection circuit 150 outputs the pulse of the count signal CNT _1 and the selector 251 does not output the signal. Between time T1 and time T2, the determination signal DET is enabled, so that the selector 251 in the selection circuit 150 outputs a pulse of the oscillation signal OSC while the selector 252 does not output a signal. Between the time T2 and the time T3, the determination signal DET is disabled, and therefore the selector 252 in the selection circuit 150 outputs the pulse of the count signal CNT _1 and the selector 251 does not output the signal.

FIG. 5 is a timing diagram illustrating the generation of refresh request signals according to an embodiment of the present invention. FIG. 6A is a table illustrating average interval statistics for estimated refresh requests, in accordance with one embodiment of the present invention. Referring to fig. 2, 4, 5 and 6A, in an embodiment, the control circuit 130 performs a logic conversion on the count signal CNT _ N according to the conversion table of fig. 4 to generate the sensing adjustment signal ST, which corresponds to the count signal CNT _ N and the sensing adjustment signal ST in fig. 5. The switch string 250 of the sensing circuit 140 turns on one of the switches SW 1-SW 7 according to the sensing adjustment signal ST to receive one of the default temperature voltages VT 20-VT 80 and thereby generate the reference temperature voltage VRT, which corresponds to the sensing adjustment signal ST and the reference temperature voltage VRT shown in fig. 5. When the monitor voltage VMON is between the default temperature voltages VT50 and VT60 (e.g., VT55), and when the reference temperature voltage VRT is between the default temperature voltages VT20 VT50, the sensing circuit 140 enables the determination signal DET (i.e., a high logic level H); when the reference temperature voltage VRT is the default temperature voltage VT60 VT80, the sensing circuit 140 disables the determination signal DET (i.e., the low logic level L). When the determination signal DET is disabled, the selector 252 in the selection circuit 150 outputs a pulse of the count signal CNT _1 and the selector 251 does not output a signal; when the determination signal DET is enabled, the selector 251 in the selection circuit 150 outputs a pulse of the oscillation signal OSC while the selector 252 does not output a signal. Therefore, the

selectors

251 and 252 are alternately activated according to the logic level of the determination signal DET to jointly generate the refresh request signal REFREQ, which corresponds to the determination signal DET and the refresh request signal REFREQ in fig. 5. In one embodiment, the refresh pulse COUNT of the refresh request signal REFREQ for each time period is as shown in FIG. 5, and the total SUM SUM of the refresh pulses of the refresh request signal REFREQ for the whole period (i.e. the COUNT signal CNT _ N is from the logic values 0 to 15) is 91, as shown in FIG. 6A, which is the total SUM 91 of the refresh pulses corresponding to the temperature of 55 ℃. In another scenario, when the monitor voltage VMON is between the default temperature voltages VT60 and VT70 (e.g., VT65), the determination signal corresponding to the reference temperature voltage VRT being the default temperature voltage VT60 changes to the high logic level H. Therefore, the SUM of refresh pulses SUM becomes 121 accordingly, please refer to fig. 6A in which the temperature of 65 ℃ corresponds to the SUM of refresh pulses SUM 121.

Referring to fig. 6A, taking the memory as the temperature 55 ℃, the refresh pulse COUNT [1] (i.e., the refresh request signal refresh in a single time period in the whole period is the number of the refresh pulse COUNT COUNTs of 1 pulse) is 11, the refresh pulse COUNT [16] (i.e., the refresh request signal refresh in a single time period in the whole period is the number of the refresh pulse COUNT COUNTs of 16 pulses) is 5, the refresh pulse SUM is 91, the average number of refresh pulses is 5.69 (i.e., the refresh pulse SUM is divided by 16), the average refresh interval is 2.81 (i.e., 16 is divided by the average number of refresh pulses), and other temperatures are analogized and will not be described again. As shown in fig. 6A, the temperature sensing circuit 10 can provide the refresh request signal REFREQ with different average refresh intervals when the memory has different temperatures.

FIG. 6B is an X-Y plot of the average interval of estimated refresh requests versus temperature, shown in accordance with one embodiment of the present invention. Referring to fig. 6A and 6B, the temperature sensing circuit 10 provides different average refresh intervals every 10 ℃ in temperatures of 20 ℃ to 80 ℃, thereby achieving high refresh interval resolution. In other words, the temperature sensing circuit 10 can dynamically adjust the ratio of the refresh pulse count [1] and the refresh pulse count [16] in the whole period according to the memory temperature to adjust the average refresh interval, thereby improving the resolution of the average refresh interval to the temperature. The current consumption can be further reduced since no further selection circuits, counters and temperature sensors (not shown) need to be added for multi-temperature step-by-step control.

FIG. 7 is a block diagram of a temperature sensing circuit according to another embodiment of the present invention. Fig. 7 is substantially the same as fig. 1, and will not be described again. Fig. 7 is different from fig. 1 in that the counting circuit 120 in the temperature sensing circuit 20 in fig. 7 also receives the refresh request signal REFREQ and generates the counting signal CNT _ N according to the refresh request signal REFREQ.

FIG. 8 is a circuit diagram of a temperature sensing circuit according to another embodiment of the present invention. Fig. 8 is substantially the same as fig. 2, and will not be described again. The difference between fig. 8 and fig. 2 is that the counter 230 in the temperature sensing circuit 20 in fig. 8 is used for receiving and counting the number of pulses of the refresh request signal REFREQ to generate the count signal CNT _ N. In another embodiment, the counter 230 generates a pulse of the count signal CNT _ N every time it counts 1 rising edge of the refresh request signal REFREQ, so that the period of the count signal CNT _ N is 1 time the refresh request signal REFREQ.

FIG. 9 is a timing diagram of a temperature sensing circuit according to another embodiment of the present invention. Referring to fig. 9, in another embodiment, the counter 230 in the temperature sensing circuit 20 is configured to receive and count the number of pulses of the refresh request signal REFREQ to generate the count signal CNT _ N. The control circuit 130 in the temperature sensing circuit 20 performs logic conversion on the count signal CNT _ N according to the conversion table of fig. 4 to generate the sensing adjustment signal ST and generate the enable signal EN. Referring to fig. 9, the count signal CNT _ N and the sensing adjustment signal ST are shown. The switch string 250 of the sensing circuit 140 of the temperature sensing circuit 20 turns on one of the switches SW 1-SW 7 according to the sensing adjustment signal ST to receive one of the default temperature voltages VT 20-VT 80 and generate the reference temperature voltage VRT, which corresponds to the sensing adjustment signal ST and the reference temperature voltage VRT shown in fig. 9. When the monitor voltage VMON is between the default temperature voltages VT50 and VT60 (e.g., VT55), and when the reference temperature voltage VRT is between the default temperature voltages VT20 VT50, the sensing circuit 140 disables the determination signal DET; when the reference temperature voltage VRT is the default temperature voltage VT 60-VT 80, the sensing circuit 140 enables the determination signal DET. When the determination signal DET is enabled, the selector 252 in the selection circuit 150 outputs a pulse of the count signal CNT _1 and the selector 251 does not output a signal; when the determination signal DET is disabled, the selector 251 in the selection circuit 150 outputs a pulse of the oscillation signal OSC while the selector 252 does not output a signal. Therefore, the

selectors

251 and 252 are alternately activated according to the logic level of the determination signal DET to jointly generate the refresh request signal REFREQ, which corresponds to the determination signal DET and the refresh request signal REFREQ in fig. 9. In another embodiment, the refresh interval of the refresh request signal REFREQ for each time period is as shown in fig. 9, and the total refresh interval of the refresh request signal REFREQ for the entire cycle (i.e., the count signal CNT _ N is from the logic value 0 to 15) is 61.

FIG. 10A is a statistical table illustrating the average interval of estimated refresh requests according to another embodiment of the present invention. Referring to fig. 10A, taking the memory as the temperature of 55 ℃, the refresh pulse count [16] is 3, the refresh pulse count [1] is 13, the average refresh interval is 3.81, and so on for other temperatures, which will not be described again. Therefore, as shown in fig. 10A, in another embodiment, when the memory has different temperatures, the temperature sensing circuit 20 may provide the refresh request signal REFREQ with different average refresh intervals.

FIG. 10B is an X-Y plot of an estimated average interval of refresh requests versus temperature, shown in accordance with another embodiment of the present invention. Referring to fig. 10A and 10B, the temperature sensing circuit 20 provides different average refresh intervals every 10 ℃ in the temperature range of 20 ℃ to 80 ℃, thereby achieving high refresh interval resolution. In other words, the temperature sensing circuit 20 can dynamically adjust the ratio of the refresh pulse count [16] to the refresh pulse count [1] in the whole period according to the memory temperature to adjust the average refresh interval, thereby improving the resolution of the average refresh interval to the temperature. The current consumption can be further reduced since no further selection circuits, counters and temperature sensors (not shown) need to be added for multi-temperature step-by-step control.

FIG. 11A is a statistical table illustrating the average interval of estimated refresh requests according to yet another embodiment of the present invention. FIG. 11B is an X-Y plot of an estimated average interval of refresh requests versus temperature, shown in accordance with yet another embodiment of the present invention. Referring to fig. 11A and 11B, the difference between fig. 6A, 6B, 10A and 10B is that the step (step) between the default temperatures of the

temperature sensing circuit

10 or 20 in fig. 11A and 11B is adjustable instead of fixing the step to 10 ℃. In yet another embodiment, a smaller step, e.g., 5 deg.C, may be used at temperatures around room temperature, and a higher resolution of average refresh interval versus temperature may be obtained around room temperature. For example, as shown in FIGS. 11A and 11B, in yet another embodiment, the step size is only 5 ℃ between 30 ℃ and 50 ℃, and the step size is greater than 5 ℃ outside of 30 ℃ to 50 ℃, which means that the resolution of the average refresh interval versus temperature between 30 ℃ and 50 ℃ is improved. That is, the present invention may also adjust the step between the plurality of default temperature voltages VT20 through VT80 of the temperature sensing circuit 10 or the temperature sensing circuit 20, so that the resolution of the average refresh interval of the refresh request signal REFREQ at different temperatures is different. In other words, the resolution may be non-uniform, so that the present invention can change the resolution of a specific temperature section without variation in the number of circuit components.

FIG. 12 is a flow chart illustrating a method of operating a temperature sensing circuit according to an embodiment of the invention. Referring to fig. 12, in step S1210, the oscillator 110 provides an oscillation signal OSC. In step S1220, the counting circuit 120 counts the oscillation signal OSC to generate a counting signal CNT _1, and the counting circuit 120 generates a counting signal CNT _ N. Next, in step S1230, the control circuit 130 performs a logic operation on the count signal CNT _ N to generate the enable signal EN and the sensing adjustment signal ST. In step S1240, the sensing circuit 140 divides the reference voltage VREF according to the sensing adjustment signal ST to generate the reference temperature voltage VRT, compares the reference temperature voltage VRT with the monitor voltage VMON according to the logic level of the enable signal EN, and generates the determination signal DET according to the comparison result. In step S1250, the selection circuit 150 dynamically selects one of the oscillation signal OSC and the count signal CNT _1 according to the determination signal DET, and generates a pulse of the refresh request signal REFREQ according to the dynamically selected one of the oscillation signal OSC and the count signal CNT _ 1.

In summary, the temperature sensing circuit and the sensing method thereof of the present invention can dynamically adjust the average refresh interval of the refresh request signal to improve the resolution of the average refresh interval to the temperature. The invention adjusts the proportion of the refresh pulse of different refresh intervals in the whole period by dynamically selecting the oscillation signal and the counting signal, thereby adjusting the average refresh interval and further improving the resolution of the average refresh interval to the temperature. Because the multi-temperature step-by-step control is performed without adding more selection circuits, counters and temperature sensors, the current consumption can be further reduced, and the frequency of the oscillation signal does not need to be increased. Furthermore, according to an embodiment of the present invention, the resolution of the average refresh interval to the temperature may be configured non-uniformly, thereby improving the resolution to the target temperature region.

It will be apparent to those skilled in the art that various modifications and variations can be made in the structure of the disclosed embodiments without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims

1. A temperature sensing circuit, suitable for use in a memory device, comprising:

an oscillator for providing an oscillation signal;

a counting circuit coupled to the oscillator for counting the oscillation signal to generate a first counting signal and for generating a second counting signal;

the control circuit is coupled with the counting circuit and used for carrying out logic operation on the second counting signal so as to generate an enabling signal and a sensing adjustment signal;

a sensing circuit, coupled to the control circuit, for dividing a reference voltage according to the sensing adjustment signal to generate a reference temperature voltage, and comparing the reference temperature voltage with a monitoring voltage according to the enable signal to generate a decision signal; and

a selection circuit coupled to the oscillator, the counting circuit and the sensing circuit, the selection circuit dynamically selecting one of the oscillation signal and the first counting signal according to the decision signal, and generating a pulse of a refresh request signal according to the dynamically selected one of the oscillation signal and the first counting signal.

2. The temperature sensing circuit of claim 1, wherein the counting circuit comprises:

a first counter coupled to the oscillator for receiving the oscillation signal and counting a number of pulses of the oscillation signal to generate a third count signal;

a second counter coupled between the first counter and the selection circuit for receiving the third counting signal and counting the number of pulses of the third counting signal to generate the first counting signal; and

the third counter is used for receiving the oscillation signal and counting the pulse number of the oscillation signal to generate the second counting signal.

3. The temperature sensing circuit of claim 1, wherein the control circuit enables the enable signal whenever the control circuit detects that the number of pulses of the oscillating signal is equal to a first preset number according to the second count signal.

4. The temperature sensing circuit of claim 1, wherein the control circuit logically converts the second count signal according to a default conversion table to generate the sensing adjustment signal, wherein logical values of the sensing adjustment signal correspond to a plurality of default temperature voltages of the memory device.

5. The temperature sensing circuit of claim 1, wherein the sensing circuit comprises:

the voltage dividing circuit is provided with a plurality of voltage dividing resistors which are connected in series with each other, are coupled with the reference voltage and generate a plurality of default temperature voltages by dividing the reference voltage;

a switch string coupled to the control circuit and the voltage divider circuit, having a plurality of switches, wherein a first terminal of each of the plurality of switches receives one of a plurality of default temperature voltages, and second terminals of all of the plurality of switches are coupled to each other, and the switch string turns on one of the plurality of switches according to the sensing adjustment signal to generate the reference temperature voltage;

a monitor voltage generating circuit for providing the monitor voltage;

a comparator coupled to the switch string and the monitor voltage generating circuit for determining whether to compare the reference temperature voltage with the monitor voltage according to the enable signal to generate a compared voltage;

the latch is coupled with the comparator and used for determining whether to latch the compared voltage according to the enabling signal so as to generate a determination signal.

6. The temperature sensing circuit of claim 5, wherein the monitor voltage generation circuit comprises:

a constant current source for providing a constant current; and

and the diode is coupled with the constant current source and used for generating the monitoring voltage according to the constant current.

7. The temperature sensing circuit of claim 1, wherein the selection circuit comprises:

a first selector coupled between the oscillator and the sensing circuit; and

a second selector coupled between the counting circuit and the sensing circuit,

wherein the first selector and the second selector are alternately activated according to a logic level of the decision signal to jointly generate the refresh request signal.

8. The temperature sensing circuit according to claim 7, wherein the first selector outputs a pulse of the oscillation signal and the second selector does not output a signal when the decision signal is enabled, and the second selector outputs a pulse of the first count signal and the first selector does not output a signal when the decision signal is disabled to collectively generate the refresh request signal.

9. The temperature sensing circuit of claim 1, wherein the counting circuit comprises:

the third counter is used for receiving the refresh request signal and counting the pulse number of the refresh request signal to generate the second counting signal.

10. The temperature sensing circuit of claim 4, wherein the resolution of the average refresh interval of the refresh request signal at different temperatures is made different by adjusting the step between the plurality of default temperature voltages.

11. A sensing method for a memory device having a temperature sensing circuit with an oscillator, a counting circuit, a control circuit, a sensing circuit and a selection circuit, the sensing method comprising:

providing an oscillating signal;

counting the oscillation signals to generate a first count signal and generating a second count signal;

performing logic operation on the second counting signal to generate an enabling signal and a sensing adjustment signal;

dividing a reference voltage according to the sensing adjustment signal to generate a reference temperature voltage, and comparing the reference temperature voltage with a monitoring voltage according to the enabling signal to generate a decision signal; and

one of the oscillation signal and the first count signal is dynamically selected according to a determination signal, and a pulse of a refresh request signal is generated according to the dynamically selected one of the oscillation signal and the first count signal.

12. The sensing method of claim 11, wherein the step of counting the oscillation signals to generate a first count signal and generating a second count signal comprises:

receiving the oscillation signal and counting the number of pulses of the oscillation signal to generate a third counting signal;

receiving the third counting signal and counting the number of pulses of the third counting signal to generate the first counting signal; and

receiving the oscillation signal and counting the number of pulses of the oscillation signal to generate the second count signal.

13. The sensing method of claim 11, wherein the control circuit enables the enable signal every time the control circuit detects that the number of pulses of the oscillating signal is equal to a first preset number according to the second count signal.

14. The sensing method as claimed in claim 11, wherein the control circuit logically converts the second count signal according to a default conversion table to generate the sensing adjustment signal, wherein a logical value of the sensing adjustment signal corresponds to a plurality of default temperatures of the memory device.

15. The sensing method of claim 11, wherein the generating a reference temperature voltage according to the sensing adjustment signal and comparing the reference temperature voltage with a monitor voltage according to the enable signal to generate a determination signal comprises:

turning on one of a plurality of switches in the sensing circuit according to the sensing adjustment signal, and generating the reference temperature voltage by dividing the reference voltage;

providing the monitoring voltage;

determining whether to compare the reference temperature voltage with the monitoring voltage according to the enable signal to generate a compared voltage; and

the compared voltage is latched to generate a decision signal.

16. The sensing method of claim 11, wherein the step of providing the monitor voltage comprises:

providing a constant current; and

and generating the monitoring voltage according to the constant current.

17. The sensing method according to claim 11, wherein the selection circuit includes a first selector and a second selector, and the first selector and the second selector are alternately activated depending on a logic level of the decision signal to collectively generate the refresh request signal.

18. The sensing method of claim 17, wherein the first selector outputs a pulse of the oscillation signal and the second selector does not output a signal when the decision signal is enabled, and the second selector outputs a pulse of the first count signal and the first selector does not output a signal when the decision signal is disabled to collectively generate the refresh request signal.

19. The sensing method of claim 11, wherein the counting circuit comprises:

receiving the refresh request signal and counting a number of pulses of the refresh request signal to generate the second count signal.

20. The sensing method of claim 14, wherein the resolution of the average refresh interval of the refresh request signal at different temperatures is made different by adjusting the step between the plurality of default temperature voltages.