CN113468838B - Modeling method and simulation method of three-dimensional cross-point memory array - Google Patents
Modeling method and simulation method of three-dimensional cross-point memory array Download PDFInfo
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Abstract
The invention discloses a three-dimensional cross-point memory arrayA column modeling method and a simulation method belong to the field of electronic information storage, and comprise the following steps: extracting a key storage layer containing a selected unit and a half-selected unit in a storage array according to a row and column address of an access operation to be simulated; for writing operation, cutting out unselected units in each key storage layer, combining line segments directly connected in series at the front ends of the selected word line and the selected bit line, and cutting out a zero-current line segment at the rear side of the selected word line and the selected bit line; for a read operation, every n key storage layers are storedGMDividing adjacent word lines into a word line group, for the word line group not containing the selected word line, utilizing an electric bridge to enable units on the same bit line to be connected in parallel, cutting unselected units, combining the word lines into a super word line, and combining the selected word line and a line segment directly connected with the front end of the selected bit line in series; and modeling according to the compressed key storage layer. The invention can compress the storage array model and reduce the memory space and time overhead of the access operation simulation.
Description
Technical Field
The invention belongs to the field of electronic information storage, and particularly relates to a modeling method and a simulation method of a three-dimensional cross-point storage array.
Background
The memory array is a basic core component for constructing the memory; the memory array is formed by arranging memory cells in a matrix, has row addresses and column addresses, and forms a physical address space.
The cross-point memory array can break through the restriction of Moore's law and realize the minimum 4F on the plane due to the removal of the unit access transistor2Cell area, where F is the array feature size; dynamic random access memory based on single transistor and single capacitor structure, and unit area of dynamic random access memory is 6F2The cross-point memory array effectively improves the storage density under the same characteristic size. The cross-point memory array has a simple geometric structure and only consists of two groups of interconnection lines, namely word lines and bit lines, wherein rows in the array are called word lines, and columns in the array are called bit lines; the memory cells are double-ended devices and are clamped at the cross points between the word lines and the bit lines, the upper electrodes of the memory cells are connected with the word lines, the lower electrodes of the memory cells are connected with the bit lines, the memory cells connected to the same word line are positioned in the same row, and the memory cells connected to the same bit line are positioned in the same rowAnd (4) columns. The microstructure of the resistance type cross-point memory array is simple, the unit structure in the array is a single resistor type or a single selector single resistor type, and the unit category can be a metal oxide resistance type memory unit or a chalcogenide phase-change resistance type memory unit. To reduce interconnect line voltage drops in the array during read and write operations from a geometric dimension perspective, the word and bit lines in the array are typically made very thick, typically three to five times their widths. Three-dimensional integration can further multiply the storage capacity per unit area of a cross-point memory array. The three-dimensional cross-point memory array reduces the area, energy consumption and other hardware expenses of a row-column address decoder at the periphery of the array by alternately sharing the word line layer and the bit line layer between the memory layers.
In order to determine the write operation key indicators (i.e., the effective write voltage of the selected cells and the array power consumption) and the read operation key indicators (i.e., the output current of the selected bit lines and the array power consumption) of the memory array, it is necessary to model the topology of the memory array and simulate the memory array access operation based on the established model. In a conventional array modeling method, a complete network model of a storage array is established by directly taking two ends of a cell in the array as nodes and taking a word line segment or a bit line segment connecting adjacent cells as edges. The array modeling method is simple and direct, but when the storage array size is large, the size of the established array model can be increased rapidly, and the memory space overhead and the time overhead of the operation simulation of the complete array network model are increased rapidly. Particularly, in the three-dimensional cross-point storage array, word lines and bit lines are alternately shared among storage layers, so that interlayer half-selected cells and interlayer sneak currents which are not contained in the two-dimensional cross-point storage array exist in the three-dimensional cross-point storage array, a current coupling effect exists among the storage layers, the degree of nodes at two ends of the cells is increased, the increase of the node degree in the array network enables a kirchhoff current law equation coefficient matrix to be denser, and the space and time overhead of an integrated circuit simulation program for carrying out array operation simulation is increased. Under the restriction of 8GB memory space, a traditional complete array network model cannot simulate the basic read-write access operation of a three-dimensional cross-point memory array with a memory layer of megascale or above.
Disclosure of Invention
Aiming at the defects and improvement requirements of the prior art, the invention provides a modeling method and a simulation method of a three-dimensional cross-point memory array, and aims to only model the array principal component influencing the array access operation in the three-dimensional cross-point memory array, so as to achieve the effect of compressing a memory array model, and further reduce the memory space and time overhead of the array access operation simulation.
To achieve the above object, according to a first aspect of the present invention, there is provided a method for modeling a three-dimensional cross-point memory array, comprising:
for the write operation of the storage array to be simulated, determining the position distribution of selected cells, half-selected cells, unselected cells, selected word lines and selected bit lines in the storage array according to the row and column addresses of the write operation so as to extract a storage layer containing the selected cells and the half-selected cells in the storage array as a key storage layer;
after first array network compression operation is carried out on each key storage layer, an array model for simulating the write operation is constructed by taking two ends of a unit in the key storage layer as points and taking a word line segment and a bit line segment which are connected with adjacent units as edges;
the first array network compression operation comprises: and cutting out the unselected units in the key storage layer, so that the adjacent word line segments or adjacent bit line segments connected with the unselected units in the key storage layer are directly connected in series.
The selected units, the half-selected units and the line segments connecting the units are components which significantly influence key indexes of write operation in the array, the components are regarded as array principal components in the write operation simulation process, and only a key storage layer containing the array principal components is modeled in the write operation modeling process, so that the scale of a three-dimensional cross-point storage array model can be greatly reduced under the condition of not influencing the write operation simulation result.
In the writing operation process of the three-dimensional cross point memory array, the number of unselected elements in the key memory layer is the largest, and the array model can be effectively compressed by optimizing the unselected elements; on the basis of extracting three key storage layers related to the selected storage layer from the complete array, further cutting out unselected units in the key storage layer, so that adjacent line segments originally connected to the unselected units are directly connected in series; because the current passing through the unselected cells is almost zero, after the unselected cells are cut off, the influence on the write operation simulation error can be ignored, but the number of nodes and edges in a key storage layer is effectively reduced, and a three-dimensional cross point storage array model is compressed.
In general, when the method is used for modeling the write operation, modeling is only performed on the key storage layer containing the array principal component, and the unselected units in the key storage layer are further cut out, so that the model can be effectively compressed under the condition of ensuring the write operation simulation precision, and the memory space and time overhead of the array access operation simulation are reduced.
Further, the first array network compression operation further comprises: after cutting out the unselected units, combining the word line segments directly connected in series at the front end of the selected word line, and combining the bit line segments directly connected in series at the front end of the selected bit line;
wherein, the front end of the selected word line is one end of the selected word line facing the word line voltage driver; the front end of the selected bit line is the end of the selected bit line toward the bit line voltage driver.
When the array modeling is carried out aiming at the write operation simulation, word line segments directly connected in series at the front ends of the selected word lines in the key storage layer and bit line segments directly connected in series at the front ends of the selected bit lines in the key storage layer are combined after the unselected units in the key storage layer are cut, so that the number of edges in the array model can be further reduced, and the compression ratio of the array model is improved.
Further, the first array network compression operation further comprises: cutting off a zero-current bit line segment at the rear side of the selected word line and a zero-current word line segment at the rear side of the selected bit line after cutting off unselected units;
the rear side of the selected word line is the side of the selected word line facing away from the word line voltage driver, and the rear side of the selected bit line is the side of the selected bit line facing away from the bit line voltage driver.
According to the invention, after the bit line segment directly connected in series at the front end of the selected word line in the key storage layer and the word line segment directly connected in series at the front end of the selected bit line are combined, the zero-current word line segment and the zero-current bit line segment at the rear side of the selected word line are further cut off, and the array network model can be further compressed under the condition that the simulation precision of the write operation key index is not influenced.
Further, after the serially connected bit line segments are combined, the combined resistance at the front end of the obtained bit line segment is RUBL＝rRl(ii) a After the word line segments connected in series are combined, the combined resistance at the front end of the obtained word line segment is RUWL_W＝(c-nw+1)Rl；
Wherein R islRepresenting a line resistance per unit length, r representing the address of the selected word line, c representing the address of the last one of the selected bit lines, nwIndicating the number of cells in the memory array that are written in parallel at one time.
According to a second aspect of the present invention, there is provided a method of modeling a three-dimensional cross-point memory array, comprising:
for the read operation of the memory array to be simulated, determining the position distribution of selected cells, half-selected cells, unselected cells, selected word lines and selected bit lines in the memory array according to the row and column addresses of the memory array, and extracting a memory layer containing the selected cells and the half-selected cells in the memory array to serve as a key memory layer;
after second array network compression operation is carried out on each key storage layer, an array model for simulating the reading operation is constructed by taking two ends of the units in the key storage layer as points and taking word line segments and bit line segments connecting adjacent units as edges;
the second array network compression operation comprises: according to a preset grouping merging granularity nGMEvery n in the critical storage layerGMThe word lines adjacent to each other in physical position are divided into a word line group, and for the word line group not containing the selected word line, the word lines and the cells are combined in the following way:
merging the word lines into a super word line, and taking the geometric center position of the word line group as the position of the merged super word line;
the electrodes of the cells on the same bit line are connected together by a bridge, the cells on the same bit line are connected in parallel, the whole of the cells connected in parallel on the same bit line are taken as a super cell obtained by merging, and the intersection of the bit line and the super word line is taken as the position of the super cell.
The selected units, the half-selected units and line segments connecting the units are components which significantly influence key indexes of read operation in the array, the components are regarded as array principal components in read operation simulation, and only a key storage layer containing the array principal components is modeled in the process of modeling the read operation, so that the scale of a three-dimensional cross-point storage array model can be greatly reduced under the condition of hardly influencing the simulation result of the read operation.
In the reading operation process of the three-dimensional cross-point storage array, the number of half-selected units in the key storage layer is the largest, and the half-selected units are optimized, so that the model can be effectively compressed; according to the invention, on the basis of extracting the key storage layer, adjacent unselected word lines are grouped according to the preset grouping and merging granularity and the unselected word lines in the group are merged, and a plurality of half-selected units can be merged into a super half-selected unit, so that the number of nodes and edges in the model is effectively reduced, and the three-dimensional cross-point storage array model is further compressed.
Generally speaking, when the method is used for modeling the read operation, modeling is only carried out on the key storage layer containing the array principal component, and further grouping and combining unselected word lines in the key storage layer, so that the array model can be effectively compressed under the condition of ensuring the simulation precision of the read operation, and the memory space and time overhead of the array access operation simulation are reduced.
Further, the second array network compression operation further comprises: before combining word lines, the unselected cells in the key storage layer are trimmed, so that adjacent word line segments or adjacent bit line segments connected with the unselected cells in the key storage layer are directly connected in series.
Because the current passing through the zero-biased unselected units in the array is almost zero, the unselected units in the key storage layer are cut off before the unselected word lines in the key storage layer are grouped and combined, so that the combining process of the unselected word lines can be simplified under the condition of not influencing the simulation precision of reading operation, the number of nodes in a model is further reduced, and the compression ratio of the model is improved.
Further, the second array network compression operation further comprises: after cutting off unselected units in the key storage layer, combining word line segments directly connected in series at the front end of the selected word line, and combining bit line segments directly connected in series at the front end of the selected bit line;
the front end of the selected word line is the end of the selected word line facing the word line voltage driver, and the front end of the selected bit line is the end of the selected bit line facing the bit line voltage driver.
When the array modeling is carried out aiming at the read operation simulation, word line segments directly connected in series at the front ends of the selected word lines in the key storage layer and bit line segments directly connected in series at the front ends of the selected bit lines in the key storage layer are merged after the unselected units in the key storage layer are cut, so that the number of edges in the array model can be further reduced, and the compression ratio of the model is improved.
Further, if the number a of word lines in each memory layer in the memory array is a perfect square number, then
If not, then,
or
For a read operation, the invention can scale the storage layer from A2Is compressed to
The invention is arranged when A is a complete square number
Enabling the total number of word lines in the latter word line layer to be compressedThe number reaches the minimum value
When A is not a complete square number, the invention sets
Or
The total word line number in the compressed word line layer can be minimized
Further, after combining adjacent word line segments connected in series on each super word line, the combined resistance of the obtained unselected word line segments is RUWL_P＝(nr+1)Rl/nGM；
The resistance of the bit line segment connecting the normal cell and the normal cell is Rl；
The resistance of the bit line segment connecting the super cell and the super cell is nGMRl；
The resistances of the bit line segment connecting the super cell and the normal cell and the bit line connecting the super cell and the array boundary cell are all
The equivalent current-voltage relationship of the super cell is as follows:
IWCP＝[nCLkL+(nGM-nCL)kH]sinh(VWCP/α)
wherein R islRepresenting the line resistance per unit length, nrRepresenting the number of cells in the memory array that are read out in parallel at one time, nCLThe number k of low-resistance state units on the same bit line with the super unit in the word line group in which the super unit is positionedLRepresenting the conductivity, k, of the low resistance state cellHDenotes the conductivity of the high-resistance state cell, IWCPIndicating existence of a super cellEffective current, VWCPRepresenting the effective voltage of the super cell and alpha representing the non-linear coefficient.
According to a third aspect of the present invention, there is provided a method of modeling a three-dimensional cross-point memory array, comprising:
if the memory array access operation to be simulated is write operation, establishing an array model for simulating the write operation by using the three-dimensional cross-point memory array modeling method provided by the first aspect of the invention;
if the memory array access operation to be simulated is a read operation, an array model for simulating the read operation is established by using the three-dimensional cross-point memory array modeling method provided by the second aspect of the invention.
The invention only carries out modeling aiming at the array principal component, and based on the influence of different operations on the distribution of unselected units and half-selected units in the array, adopts a modeling mode of read-write separation to carry out array modeling on write operation and read operation respectively, cuts the unselected units in the modeling of the write operation, and carries out grouping combination on unselected word lines in the modeling of the read operation, thereby effectively compressing the model of the three-dimensional cross-point memory array on the basis of adapting to the array model frame of the read-write operation, and reducing the memory space and time overhead of the array access operation simulation.
According to a fourth aspect of the present invention, there is provided a method of simulating an access operation of a three-dimensional cross-point memory array, comprising:
establishing an array model for simulating the access operation by using the modeling method of the three-dimensional cross-point memory array provided by the third aspect of the invention;
according to the operation type of the access operation, after applying corresponding bias operation to the array model for simulating the access operation, generating an SPICE netlist for simulating the access operation;
and simulating the access operation by using the SPICE netlist as input and using an SPICE simulation tool to obtain key indexes of the access operation.
According to a fifth aspect of the present invention, there is provided a computer readable storage medium comprising a stored computer program; the computer program, when executed by the processor, controls an apparatus on a computer-readable storage medium to perform a method for modeling a three-dimensional cross-point memory array provided by the present invention and/or a method for simulating an access operation of a three-dimensional cross-point memory array provided by the present invention.
Generally, by the above technical solution conceived by the present invention, the following beneficial effects can be obtained:
(1) when the three-dimensional cross-point memory array is modeled, only the main component of the array is modeled according to the address of the access operation, and the scale of a three-dimensional cross-point memory array network model can be effectively reduced under the condition of ensuring the simulation precision of the three-dimensional cross-point memory array access operation, so that the memory space and time overhead of the array access operation simulation are reduced.
(2) On the basis of analyzing the array principal components only, based on the influence of different operations on the distribution of unselected units and half-selected units in the array, the invention adopts a modeling mode of read-write separation to respectively model write operation and read operation, and cuts the unselected units in the array when modeling the write operation; when modeling is carried out on the read operation, unselected word lines in the array are grouped and combined, so that the model of the three-dimensional cross point storage array can be further compressed on the basis of the array model framework adaptive to the read-write operation, and the memory space and time overhead of the array access operation simulation are reduced.
(3) The method for simulating the access operation of the three-dimensional cross-point memory array can simulate the read-write basic operation of the three-dimensional cross-point memory array with the memory layer size of megascale or above under the 8GB memory space limit.
Drawings
FIG. 1 is a schematic diagram of the distribution of different memory cells during a conventional voltage-biased write operation applied to a complete three-dimensional cross-point memory array model; the storage layer with the selected unit is a storage layer with a k-th storage layer, wherein (a) the distribution schematic diagram of different storage units in the storage layer with the selected unit is located, (b) the distribution schematic diagram of different storage units in the k + 1-th storage layer, (c) the distribution schematic diagram of different storage units in the k-1-th storage layer, (d) the distribution schematic diagram of different storage units in the k + 2-th storage layer, and (e) the distribution schematic diagram of different storage units in the k-2-th storage layer;
FIG. 2 is a schematic diagram of the distribution of different memory cells during a prior art voltage-biased read operation applied to a complete three-dimensional cross-point memory array model; the storage layer with the selected unit is a storage layer with a k-th storage layer, wherein (a) the distribution schematic diagram of different storage units in the storage layer with the selected unit is located, (b) the distribution schematic diagram of different storage units in the k + 1-th storage layer, (c) the distribution schematic diagram of different storage units in the k-1-th storage layer, (d) the distribution schematic diagram of different storage units in the k + 2-th storage layer, and (e) the distribution schematic diagram of different storage units in the k-2-th storage layer;
FIG. 3 is a schematic diagram of a three-dimensional cross-point memory array modeling method for write operations according to embodiment 1 of the present invention; wherein (a) is the result of modeling for the storage layer in which the selected cell is located, i.e., the k-th storage layer, (b) is the result of modeling for the (k + 1) -th storage layer, and (c) is the result of modeling for the (k-1) -th storage layer;
FIG. 4 is a schematic diagram of a three-dimensional cross-point memory array modeling method for a read operation according to embodiment 2 of the present invention; the method comprises the following steps of (a) grouping and merging schematic diagrams for unselected word lines in a storage layer where a selected unit is located, namely a k storage layer, (b) grouping and merging schematic diagrams for unselected word lines in a k +1 storage layer, (c) grouping and merging schematic diagrams for unselected word lines in a k-1 storage layer, (d) modeling results for the k storage layer, (e) modeling results for the k +1 storage layer, and (f) modeling results for the k-1 storage layer;
fig. 5 is a flowchart of an access operation simulation method for a three-dimensional cross-point memory array according to embodiment 4 of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
In the present application, the terms "first," "second," and the like (if any) in the description and the drawings are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.
Before explaining the technical scheme of the present invention in detail, the distribution of memory cells in different states in each layer of a three-dimensional cross-point memory array when different bias operations are applied to the array is briefly described as follows:
in a three-dimensional cross-point memory array, each memory layer is constituted by word lines and bit lines with memory cells sandwiched therebetween; the memory cell is a two-end structure and is positioned at the intersection of a word line and a bit line, the upper electrode of the memory cell is connected to the word line, and the lower electrode of the memory cell is connected to the bit line;
the word line and the bit line in the storage layer can be selected by applying complete read-write bias voltage to the word line and the bit line of the storage array; if the word line and the bit line connected with the memory cell are selected, the memory cell is a selected cell; if the voltage difference applied by the word line and the bit line connected with the memory cell is half of the read-write voltage, the memory cell is a half-selected cell; if the bias voltages applied to the word line and the bit line connected with the memory cell are the same, the memory cell is an unselected cell.
Fig. 1 shows an example of a write operation performed on a three-dimensional cross-point memory array, in which, as shown in fig. 1 (a), a k-th memory layer is selected to be written, and two cells, i.e., a third column and a fourth column of a first row in the k-th memory layer, are selected to perform the write operation in parallel. At this time, half-selected cells exist only on the same row or column as the selected cells; and interlayer half select cells exist only on selected rows and selected columns of the (k + 1) th and (k-1) th storage layers, as shown in (b) and (c) of fig. 1; there are only unselected cells in other storage layers, e.g., only unselected cells on the k +2 storage layer and the k-2 storage layer, as shown in fig. 1 (d) and (e).
Fig. 2 shows an example of performing a read operation on a three-dimensional cross-point memory array, and as shown in (a) of fig. 2, a k-th memory layer in the three-dimensional cross-point memory array is selected to be read, that is, two cells of a third column and a fourth column of a first row in the k-th memory layer are selected to perform the read operation in parallel. At this time, only unselected cells except for the selected cells on the selected bit lines, and half selected cells exist only in the k storage layer, and the k +1 storage layer and the k-1 storage layer, as shown in (b) and (c) of FIG. 2; only unselected cells in the storage layer having a distance greater than or equal to two from the selected storage layer, for example, only unselected cells on the k +2 th and k-2 th storage layers, as shown in (d) and (e) of fig. 2.
When the read-write operation is executed on the three-dimensional cross-point storage array, the selected unit and the half-selected unit and the line segment connecting the selected unit and the half-selected unit can obviously influence the key indexes of the access operation, the traditional array modeling method does not distinguish the units in different bias states, directly takes two ends of the units in the array as nodes and takes a word line segment or a bit line segment connecting adjacent units as edges to establish a complete network model of the storage array, and based on the complete network model, in the access operation simulation process, the memory space and time cost are too large, so that the read-write basic operation of the three-dimensional cross-point storage array with the storage layer scale of megascale and above can not be simulated under the limitation of 8GB memory space. In order to solve the technical problem, the invention provides a modeling method and a simulation method of a three-dimensional cross-point memory array, and the overall idea is as follows: the selected unit, the half-selected unit and a line segment connecting the selected unit and the half-selected unit are taken as array principal components, modeling is only carried out on the array principal components, so that the scale of a model is effectively compressed, a read-write separation modeling mode is adopted to respectively model write operation and read operation on the basis of the influence of different operations on the distribution of unselected units and the half-selected units in the array, and the unselected units are cut when the array model for simulating the write operation is established; when the array model for simulating the read operation is established, unselected word lines in the array model are grouped and combined according to a certain granularity, so that the model of the three-dimensional cross point storage array can be compressed on the basis of adapting to the array model framework of the read-write operation, and the memory space and time overhead of the array access operation simulation are reduced.
The following are examples.
Example 1:
a method of modeling a three-dimensional cross-point memory array, comprising:
for the write operation of the memory array to be simulated, determining the position distribution of selected cells, half-selected cells, unselected cells, selected word lines and selected bit lines in the memory array according to the row and column addresses of the write operation, so as to extract a memory layer containing the selected cells and the half-selected cells in the memory array, namely a memory layer containing the array principal components, as a key memory layer;
after the first array network compression operation is carried out on each key storage layer, an array model for simulating the write operation is constructed by taking two ends of the cells in the key storage layer as points and taking word line segments and bit line segments connecting adjacent cells as edges.
The embodiment only models the storage layer containing the array principal component, so that the modeling and the storage layer not containing the array principal component can be avoided, the number of nodes and edges in the array network is reduced, and the scale of the three-dimensional cross-point storage array model is effectively reduced; taking the write operation shown in FIG. 1 as an example, the present embodiment only needs to model for the k, k +1 and k-1 storage layers, where k is the selected storage layer; without modeling all storage tiers.
Considering that the number of unselected cells in the key storage layer is the largest in the writing operation process of the three-dimensional cross-point memory array, the array model can be effectively compressed by optimizing the unselected cells, and the same bias voltage is applied to the word line connected to the upper electrode of the unselected cell and the bit line connected to the lower electrode of the unselected cell, so that the unselected cell is zero-biased, and the cell current can be ignored; and the unselected units in the key storage layer are directly cut off, and the error brought by the simulation of the writing operation can be ignored. Therefore, in this embodiment, the first array network compression operation includes: cutting out unselected units in the key storage layer to enable adjacent word line segments or adjacent bit line segments connected to the unselected units in the key storage layer to be directly connected in series;
from the perspective of a network topology structure, the connection degree of top and bottom nodes of any unit in the three-dimensional cross point storage array is not more than four; after the unselected cells in the key storage layer are trimmed, the degrees of the two terminals of the unselected line segments originally connected to the unselected cells can be reduced to two, and therefore, the adjacent line segments can become connected in series. On the basis of extracting the key storage layer, the embodiment further cuts out the unselected units in the key storage layer, effectively reduces the number of nodes and edges in the key storage layer, and further compresses the three-dimensional cross-point storage array model.
To further compress the three-dimensional cross-point memory array model, in this embodiment, the first array network compression operation on the key memory layer further includes: after cutting out the unselected units, combining the word line segments directly connected in series at the front end of the selected word line, and combining the bit line segments directly connected in series at the front end of the selected bit line;
wherein, the front end of the selected word line is one end of the selected word line facing the word line voltage driver; the front end of the selected bit line is the end of the selected bit line toward the bit line voltage driver.
After the unselected units in the key storage layer are cut out, the word line segments directly connected in series at the front ends of the selected word lines in the key storage layer and the bit line segments directly connected in series at the front ends of the selected bit lines in series are combined, so that the number of edges in the model can be further reduced, and the compression rate of the model is improved.
To further compress the three-dimensional cross-point memory array model, in this embodiment, the first array network compression operation on the key memory layer further includes: cutting off a zero-current word line segment and a zero-current bit line segment floating at the rear side after the unselected units are cut off, namely cutting off a zero-current bit line segment at the rear side of the selected word line and a zero-current word line segment at the rear side of the selected bit line;
the rear side of the selected word line is the side of the selected word line, which is back to the word line voltage driver, and the rear side of the selected bit line is the side of the selected bit line, which is back to the bit line voltage driver;
after combining the word line segment directly connected in series at the front end of the selected word line segment in the key storage layer and the bit line segment directly connected in series at the front end of the selected bit line, the zero-current word line segment and the zero-current bit line segment floating at the back side are further cut off, and the model can be further compressed under the condition of not influencing the simulation precision of write operation.
Taking the write operation shown in fig. 1 as an example, the present embodiment only needs to model the k, k +1 and k-1 storage layers, and perform the above-mentioned first array network compression operation on the three storage layers, where the compressed storage layers are respectively shown as (a), (b) and (c) in fig. 3;
after the unit line resistances are combined, the total equivalent line resistance can be represented analytically, which is as follows:
after merging the adjacent bit line segments connected in series, the merged resistance of the obtained bit line segment is RUBL＝rRl(ii) a After combining the adjacent word line segments in series, the combined resistance of the obtained word line segment is RUWL_W＝(c-nw+1)Rl；
Wherein R islRepresenting a line resistance per unit length, r representing the address of the selected word line, c representing the address of the last one of the selected bit lines, nwIndicating the number of cells in the memory array that are written in parallel at one time.
Example 2:
a method of modeling a three-dimensional cross-point memory array, comprising:
for the write operation of the memory array to be simulated, determining the position distribution of selected cells, half-selected cells, unselected cells, selected word lines and selected bit lines in the memory array according to the row and column addresses of the write operation, so as to extract a memory layer containing the selected cells and the half-selected cells in the memory array, namely a memory layer containing the array principal components, as a key memory layer;
and after the second array network compression operation is carried out on each key storage layer, an array model for simulating reading operation is constructed by taking two ends of the units in the key storage layer as points and taking word line segments and bit line segments connecting adjacent units as edges.
The embodiment only models the storage layer containing the array principal component, so that the storage layer not containing the array principal component can be prevented from being modeled and stored, and the scale of the three-dimensional cross-point storage array model is effectively reduced; taking the read operation shown in fig. 2 as an example, the present embodiment only needs to model the k, k +1 and k-1 storage layers, and does not need to model all storage layers.
Considering that the number of half-selected units in the key storage layer is the largest in the read operation process of the three-dimensional cross-point storage array, and the model can be effectively compressed by optimizing the half-selected units, in this embodiment, the network compression operation of the second array includes: according to a preset grouping merging granularity nGMEvery n in the critical storage layerGMThe adjacent word lines are divided into a word line group, and for the word line group not containing the selected word line, namely the word line group only containing unselected word lines, the word lines and the cells in the word line group are combined in the following way:
merging the word lines into a super word line, and taking the geometric center position of the word line group as the position of the merged super word line;
the upper electrodes of the cells on the same bit line are connected together by a bridge, the cells on the same bit line are connected in parallel, the cells connected in parallel on the same bit line are used as the super cells obtained by combination, and the intersection of the bit line and the super word line is used as the position of the super cell.
On the basis of extracting the key storage layer, the embodiment groups unselected word lines according to the preset grouping and merging granularity and performs word line merging in the group, and can merge a plurality of half-selected units into a super half-selected unit, so that the number of nodes and edges in the array network model is effectively reduced, and the three-dimensional cross-point storage array model is further compressed; for the word line group where the selected word line is located, although finer grouping and merging granularity may be further adopted, this will significantly increase the resistance parameter of the three-dimensional cross-point array model, and complicate the array model, therefore, after grouping the word lines in the key storage layer, the embodiment does not merge the word lines and cells for the word line group where the selected word line is located.
Considering that the current passing through the zero-biased unselected cell is almost zero, the unselected cell in the key storage layer is directly cut off, and the influence on the analog accuracy of the read operation can be ignored, therefore, in this embodiment, the second array network compression operation further includes: before combining the word lines, cutting off unselected units in the key storage layer to enable adjacent word line segments or adjacent bit line segments connected by the unselected units in the key storage layer to be directly connected in series, thereby simplifying the combining process of the unselected word lines without influencing the simulation precision of reading operation, further reducing the number of nodes in a model and improving the compression ratio of the model.
In order to further compress the model, in this embodiment, the second array network compression operation further includes: after cutting off unselected units in the key storage layer, combining word line segments directly connected in series at the front end of the selected word line, and combining bit line segments directly connected in series at the front end of the selected bit line;
wherein, the front end of the selected word line is one end of the selected word line facing the word line voltage driver; the front end of the selected bit line is the end of the selected bit line toward the bit line voltage driver.
After the unselected units in the key storage layer are cut out, the word line segments directly connected in series at the front ends of the selected word lines in the key storage layer and the bit line segments directly connected in series at the front ends of the selected bit lines in series are combined, so that the number of edges in the model can be further reduced, and the compression rate of the model is improved.
In this embodiment, the packet merging granularity nGMThat is, the number of adjacent word lines in each word line group affects the actual size of the storage layer after the array network is compressed; for ease of grouping, nGMUsually a submultiple of the number a of word lines in a memory layer, the number a of word lines is usually an integer power of 2, and after grouping and merging the word lines in the critical memory layer, there is a total of word line layers
A super word line and nGMA common word line. Thus, for a read operation, the storage layer scales from A2Is compressed to
In order to compress the model to the maximum extent, in the present embodiment, the packet merging granularity n is set as followsGM：
If the number A of word lines in each memory layer in the memory array is a perfect square number, then
Thereby minimizing the total word line number in the compressed word line layer
If not, then,
or
Thereby minimizing the total word line number in the compressed word line layer
It should be noted that the above relates to the packet merging granularity nGMThe setting mode of (n) is only a preferred embodiment of the present invention, and should not be construed as a limitation to the present invention, and in some other embodiments of the present invention, the grouping and merging granularity n may be determined in other manners according to actual memory and computing resources, etcGMThe specific value of (a).
Taking the read operation shown in fig. 2 as an example, the present embodiment only needs to model the k, k +1 and k-1 storage layers, perform the above-mentioned second array network compression operation on the three storage layers, and perform grouping and merging processes on unselected word lines in each storage layer as shown in (a), (b) and (c) of fig. 4, and the compressed storage layers are respectively shown in (d), (e) and (f) of fig. 4.
Based on the grouping and merging operation, the embodiment can divide the whole three-dimensional cross-point memory array model into a parsing part in the word line group and a numerical part outside the word line group; by deducing an analytical expression of the array resistance network in the word line group, the analog overhead of array operation can be reduced; and a numerical model is established among the unselected word line groups, so that the original connection relation of the three-dimensional cross point array network can be maintained.
In the embodiment, in a three-dimensional cross point array model obtained by grouping and compressing according to word lines, units are divided into two types, namely ordinary units and super units, namely unmerged ordinary units and merged super units; in this embodiment, the merged line segments are also divided into two types, the first type being an internal line segment between two super cells; the second type is the boundary line segment between the super cell and the normal cell, or between the boundary super cell and the voltage source. For each word line group to be merged in a three-dimensional cross-point memory array, the locally resolved portion of the resistive switching is analyzed as follows.
After combining the adjacent word line segments connected in series on each super word line, the resistance of the obtained word line segment is RUWL_P＝(nr+1)Rl/nGM；
The resistance of the bit line segment connecting the normal cell and the normal cell is Rl；
The resistance of the bit line segment connecting the super cell and the super cell is nGMRl；
The resistances of the bit line segment connecting the super cell and the normal cell and the bit line connecting the super cell and the array boundary cell are all
The super unit is formed by parallel combination of common half-selected units on a group of adjacent unselected word lines; the equivalent current-voltage relationship of the super cell is as follows:
IWCP＝[nCLkL+(nGM-nCL)kH]sinh(VWCP/α)
wherein R islRepresenting the line resistance per unit length, nrRepresenting the number of cells in the memory array that are read out in parallel at one time, nCLThe number k of low-resistance state units on the same bit line with the super unit in the word line group of the super unitLRepresenting the conductivity, k, of the low resistance state cellHDenotes the conductivity of the high-resistance state cell, IWCPRepresenting the effective current, V, of the super cellWCPRepresenting the effective voltage of the super cell and alpha representing the non-linear coefficient.
In order to make the address numbering of the nodes and lines simpler in the grouping, merging and transforming process of the array network, optionally, in this embodiment, the address of the super cell obtained by grouping and merging is mapped to the address of the first cell located on the same bit line in the same word line group; the address of the super word line obtained by grouping and merging is mapped to the address of the first word line in the word line group;
it should be noted that, this is only an optional embodiment, and should not be construed as the only limitation of the present invention, in some other embodiments of the present invention, the address of the super word line obtained by grouping and merging may also be mapped to the address of any mth word line in the word line group, and accordingly, the address of the super cell obtained by grouping and merging is mapped to the address of the mth cell located on the same bit line in the same word line group.
Example 3:
a method of modeling a three-dimensional cross-point memory array, comprising:
if the memory array access operation to be simulated is a write operation, establishing an array model for simulating the write operation by using the three-dimensional cross-point memory array modeling method provided in the above embodiment 1;
if the memory array access operation to be simulated is a read operation, an array model for simulating the read operation is established by using the three-dimensional cross-point memory array modeling method provided in embodiment 2.
The embodiment only carries out modeling on the array principal component, and respectively carries out modeling on write operation and read operation by adopting an array modeling mode of read-write separation based on the influence of different operations on the distribution of unselected units and half-selected units in the array, and cuts the unselected units in the array when modeling the write operation; when modeling is carried out on the read operation, the unselected word lines are grouped and combined, so that the three-dimensional cross point storage array model can be effectively compressed on the basis of adapting to the array model framework of the read-write operation, and the memory space and time overhead of the array access operation simulation is reduced.
Example 4:
a method for simulating an access operation of a three-dimensional cross-point memory array, as shown in fig. 5, comprises:
establishing an array model for simulating the access operation by using the modeling method of the three-dimensional cross-point memory array provided in the above embodiment 3;
according to the operation type of the access operation, after applying corresponding bias operation to the array model for simulating the access operation, generating an SPICE netlist for simulating the access operation;
taking the SPICE netlist as input, and simulating the access operation by using an SPICE simulation tool to obtain key indexes of the access operation; for write operation, the key indexes output after simulation are the effective write voltage of the storage unit and the array power consumption; for a read operation, the key indicators of the simulated output are the output current of the selected bit line and the array power consumption.
According to the method, the array principal components influencing key indexes of memory access operation are selected to construct an array network model according to the applied operation types and operation parameters, different array models are established for write operation and read operation, and finally write operation simulation and read operation simulation are respectively executed on the two different array network models. The array model is compressed, but the compressed array model shares the data stored in the same array. Therefore, when the three-dimensional cross-point memory array is subjected to operation simulation, the required memory space overhead and time overhead are small, and the basic read-write operation of the three-dimensional cross-point memory array with the memory layer size of megascale or more can be simulated under the limitation of 8GB memory space.
Example 5:
a computer readable storage medium comprising a stored computer program; the computer program, when executed by the processor, controls an apparatus on which the computer-readable storage medium is stored to perform the method for modeling a three-dimensional cross-point memory array provided in any one of embodiments 1 to 3 above and/or the method for simulating an access operation of a three-dimensional cross-point memory array provided in embodiment 4 above.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A method of modeling a three-dimensional cross-point memory array, comprising:
for the write operation of the storage array to be simulated, determining the position distribution of selected cells, half-selected cells, unselected cells, selected word lines and selected bit lines in the storage array according to the row and column addresses of the write operation so as to extract a storage layer containing the selected cells and the half-selected cells in the storage array as a key storage layer;
after first array network compression operation is carried out on each key storage layer, an array model for simulating the write operation is constructed by taking two ends of a unit in the key storage layer as points and taking a word line segment and a bit line segment which are connected with adjacent units as edges;
the first array network compression operation comprises: and cutting out the unselected units in the key storage layer, so that the adjacent word line segments or adjacent bit line segments connected with the unselected units in the key storage layer are directly connected in series.
2. The method of modeling a three-dimensional crosspoint memory array of claim 1, wherein said first array network compression operation further comprises: after cutting out the unselected units, combining the word line segments directly connected in series at the front end of the selected word line, and combining the bit line segments directly connected in series at the front end of the selected bit line;
wherein, the front end of the selected word line is one end of the selected word line facing the word line voltage driver; the front end of the selected bit line is the end of the selected bit line toward the bit line voltage driver.
3. The method of modeling a three-dimensional crosspoint memory array of claim 2, wherein said first array network compression operation further comprises: cutting off a zero-current bit line segment at the rear side of the selected word line and a zero-current word line segment at the rear side of the selected bit line after cutting off unselected units;
the rear side of the selected word line is the side of the selected word line facing away from the word line voltage driver, and the rear side of the selected bit line is the side of the selected bit line facing away from the bit line voltage driver.
4. A method of modeling a three-dimensional cross-point memory array, comprising:
for the read operation of the memory array to be simulated, determining the position distribution of selected cells, half-selected cells, unselected cells, selected word lines and selected bit lines in the memory array according to the row and column addresses of the memory array to extract a memory layer containing the selected cells and the half-selected cells in the memory array as a key memory layer;
after second array network compression operation is carried out on each key storage layer, an array model for simulating the reading operation is constructed by taking two ends of a unit in the key storage layer as points and taking a word line segment and a bit line segment which are connected with adjacent units as edges;
the second array network compression operation comprises: according to a preset grouping merging granularity nGMEvery n in the critical storage layerGMThe word lines adjacent to each other in physical position are divided into a word line group, and for the word line group not containing the selected word line, the word lines and the cells are combined in the following way:
merging the word lines into a super word line, and taking the geometric center position of the word line group as the position of the super word line obtained by merging;
the electrodes of the cells on the same bit line are connected together by a bridge, the cells on the same bit line are connected in parallel, the whole of the cells connected in parallel on the same bit line are taken as a super cell obtained by merging, and the intersection of the bit line and the super word line is taken as the position of the super cell.
5. The method of modeling a three-dimensional crosspoint memory array of claim 4, wherein said second array network compression operation further comprises: before combining the word lines, cutting out the unselected units in the key storage layer, so that the adjacent word line segments or adjacent bit line segments connected with the unselected units in the key storage layer are directly connected in series.
6. The method of modeling a three-dimensional crosspoint memory array of claim 5, wherein said second array network compression operation further comprises: after cutting off unselected units in the key storage layer, combining word line segments directly connected in series at the front end of the selected word line, and combining bit line segments directly connected in series at the front end of the selected bit line;
the front end of the selected word line is the end of the selected word line facing the word line voltage driver, and the front end of the selected bit line is the end of the selected bit line facing the bit line voltage driver.
7. The method of modeling a three-dimensional cross-point memory array as claimed in any of claims 4-6 wherein if the number of wordlines A in each memory layer in said memory array is a perfect square number, then
If not, then the mobile terminal can be switched to the normal mode,
or
8. A method of modeling a three-dimensional cross-point memory array, comprising:
if the memory array access operation to be simulated is a write operation, establishing an array model for simulating the write operation by using the three-dimensional cross-point memory array modeling method of any one of claims 1 to 3;
if the memory array access operation to be simulated is a read operation, then an array model for simulating the read operation is created using the three-dimensional cross-point memory array modeling method of any of claims 4-7.
9. A method for simulating an access operation of a three-dimensional cross-point memory array, comprising:
establishing an array model for simulating the access operation using the method of modeling a three-dimensional cross-point memory array of claim 8;
according to the operation type of the access operation, after corresponding voltage bias operation is applied to the array model, an SPICE netlist used for simulating the access operation is generated;
and simulating the access operation by using the SPICE netlist as input and using a SPICE simulation tool to obtain the key indexes of the access operation.
10. A computer-readable storage medium comprising a stored computer program; the computer program, when executed by a processor, controls an apparatus on which the computer-readable storage medium is located to perform a method of modeling a three-dimensional cross-point memory array according to any one of claims 1 to 8, and/or a method of simulating an access operation of a three-dimensional cross-point memory array according to claim 9.
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