CN113468092A

CN113468092A - High-speed SPI communication device

Info

Publication number: CN113468092A
Application number: CN202010249408.8A
Authority: CN
Inventors: 陈晓明; 王秀艳
Original assignee: BYD Semiconductor Co Ltd
Current assignee: BYD Semiconductor Co Ltd
Priority date: 2020-03-31
Filing date: 2020-03-31
Publication date: 2021-10-01
Anticipated expiration: 2040-03-31
Also published as: CN113468092B

Abstract

The invention discloses a high-speed SPI communication device, comprising: the SRAM storage module is connected with the host through the AHB bus interface module and is used for loading communication data; and the SPI module is connected with the SRAM storage module, is connected with the slave through an SPI bus interface, and is used for acquiring data to be transmitted from the SRAM storage module in a time-sharing mode by utilizing ping-pong data transmission operation when the host transmits the data to the slave and continuously transmitting the data to be transmitted to the slave. The high-speed SPI high-speed device can realize continuous data sending and large-amount data processing, and is small in occupied area, low in power consumption and high in utilization rate.

Description

High-speed SPI communication device

Technical Field

The invention relates to the technical field of communication, in particular to a high-speed SPI communication device.

Background

A conventional low-speed SPI (Serial Peripheral Interface) receives and transmits data, and reads and writes a read/write buffer of the SPI through a bus. In the conventional high-speed SPI, on the basis of the low-speed SPI, asynchronous rx _ fifo (receive _ first input first output, receive-first in first out) and tx _ fifo (transport _ first input first output, transmit-first in first out) are added to realize continuous read and write operations on data.

The traditional high-speed SPI communication working principle is as follows: the asynchronous FIFO sends and receives data in SCLK time domain, after synchronous signal processing, in system clock time domain, completes interactive work with SPI (such as informing SPI to complete receiving and sending), and can read and write FIFO data through system bus. In general, asynchronous rx _ FIFO and tx _ FIFO are added to a circuit structure, but in order to save chip area, the size of FIFO is generally limited to 256 bytes, and large data communication cannot be realized (the circuit area after asynchronous FIFO DC synthesis written by using RTL (Register Transfer Level) is twice as large as that of an SRAM (Static Random-Access Register) equivalent unit). Meanwhile, a certain time is required from the loading of data by tx _ fifo to the transmission of the shift register, which results in a relatively low slave SPI communication frequency and fails to satisfy the high frequency data communication of various electronic devices at present (at this time, many chips use four-wire SPI to work to increase the communication speed, but occupy 3 more IO ports, increasing the chip area).

Disclosure of Invention

The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, an object of the present invention is to provide a high-speed SPI communication device, which can continuously transmit data and process a large amount of data, and has a small occupied area, low power consumption, and a high utilization rate.

To achieve the above object, the present invention provides a high-speed SPI communication device, comprising: the SRAM storage module is connected with the host through the AHB bus interface module and used for loading communication data; and the SPI module is connected with the SRAM storage module, is connected with a slave through an SPI bus interface, and is used for acquiring data to be transmitted from the SRAM storage module in a time-sharing mode by utilizing ping-pong data transmission operation when the host transmits the data to the slave, and continuously transmitting the data to be transmitted to the slave.

According to the high-speed SPI high-speed device disclosed by the embodiment of the invention, a large amount of data processing can be realized through the cooperation between the SRAM storage module and the SPI module, the occupied area is small, the power consumption is low, and the utilization rate is high; the data to be sent is acquired from the SRAM storage module in a time-sharing mode through ping-pong data transmission operation, uninterrupted and continuous data sending in an SCLK time domain can be achieved, and the highest communication frequency of the host and the slave can reach 2 frequency division of a system clock.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

Fig. 1 is a block diagram of a high-speed SPI communication device according to an embodiment of the present invention;

FIG. 2 is a block diagram of a high-speed SPI communication device in accordance with one embodiment of the present invention;

FIG. 3 is a block diagram of the control unit of one embodiment of the present invention;

FIG. 4 is a schematic diagram of a clock conversion circuit according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of the controller of one embodiment of the present invention;

FIG. 6 is a timing diagram of an example of an SPI module of the present invention for sending data;

FIG. 7(a) is a timing diagram of an example SPI module transmitting data according to the present invention;

FIG. 7(b) is a schematic diagram of an exemplary SPI module interacting with an SRAM memory module in accordance with the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.

A high-speed SPI communication device according to an embodiment of the present invention is described below with reference to the drawings.

Fig. 1 is a block diagram of a high-speed SPI communication device according to an embodiment of the present invention.

As shown in fig. 1, the high-speed SPI communication device includes: an SRAM memory module 30, an SPI module 40.

The SRAM memory module 30 is connected to a host through the AHB bus interface module 10, and is used for loading communication data; the SPI module 40 is connected to the SRAM memory module 30, connected to the Slave through the SPI bus interface module 20, and configured to acquire data to be transmitted from the SRAM memory module 30 by using a ping-pong data transmission operation when the Master transmits data, i.e., a Master Output Slave Input, to the Slave, and continuously transmit the data to be transmitted to the Slave.

Alternatively, referring to fig. 1, the SPI module 40 may be connected to the host through the AHB bus interface module 10. The SPI module 40 may also be configured to receive data sent by the Slave and load the received data into the SRAM memory module 30 when the Slave sends data, i.e., MISO (Master Input Slave Output), to the Master.

In this embodiment, the SRAM memory module may be a 4Kbyte SRAM, which can be reused in another module by simple address decoding, which can improve the utilization rate, and the circuit area of the 4Kbyte SRAM is half smaller than the FIFO area of the same capacity.

The high-speed SPI high-speed device can realize a large amount of data processing through the cooperation between the SRAM storage module and the SPI module, and has small occupied area, low power consumption and high utilization rate; the data to be transmitted is acquired from the SRAM storage module in a time sharing mode through ping-pong data transmission operation, uninterrupted and continuous data transmission in an SCLK time domain can be achieved, and the highest communication frequency of a host and a slave can reach 2 frequency division of a system clock, and of course, the advantage can be more fully embodied in the application of a high-frequency chip (such as a multifunctional MCU chip) (for example, the slave communication frequency is 24M, the host is a high-frequency chip of a 98M system clock, the highest communication frequency of the host can reach 48M, and the transmitting and receiving time sequences of the host SPI and the slave SPI can both meet the communication requirements of the other party).

As an example, the SPI module 40 is further configured to: when the host sends data to the slave, first request information is sent to the SRAM storage module 30, a sending address corresponding to the SRAM storage module 30 is obtained according to the request information, and data needing to be sent is obtained from a storage space corresponding to the sending address by using ping-pong data transmission operation; and/or when the slave sends data to the host, sending second request information to the SRAM memory module 30, acquiring a receiving address corresponding to the SRAM memory module 30 according to the second request information, and loading the received data into a storage space corresponding to the receiving address.

Specifically, referring to fig. 1, the SPI module 40 may obtain the data to be sent from the address corresponding to the SRAM memory module by sending the corresponding request message to the SRAM memory module 30, and may load the data to be sent in the SRAM memory module 30 in a "ping-pong" time-sharing manner using 2 write buffers, so as to achieve continuous and uninterrupted data sending in the SCLK time domain. When the SPI module 40 completes receiving a data, it immediately sends a corresponding request message to the SRAM memory module 30 to write the data in the read buffer to the corresponding address of the SRAM memory module 30. The above interworking of each data is to send request information from the SPI module 40 to the SRAM memory module 30, and then to finish the data processing, only 1 system clock time needs to be spent, thereby realizing high-efficiency, large-batch communication.

As an example, as shown in fig. 2, the SPI module 40 includes: a transmission shift register 41 and a control unit 43.

Referring to fig. 2, the transmission shift register 41 is connected to the SPI bus interface module 20; the control unit 43 is connected to the transmission shift register 41, and is configured to acquire data to be transmitted from the SRAM memory module 30 by using a ping-pong data transfer operation when the master transmits data to the slave, and load the data to be transmitted to the transmission shift register 41.

Optionally, the SPI module 40 may further include a receiving shift register 42, and the receiving shift register 42 is connected to the SPI bus interface module 20; the control unit 43 is connected to the receiving shift register 42, and is configured to load the data transmitted from the slave to the SRAM memory module 30 from the receiving shift register 42, if the SRAM memory module 30 determines that there is no system bus access, with only 1 system clock time.

Therefore, when the master sends data to the slave, the control unit 43 acquires the data to be sent from the SRAM memory module 30 by using the ping-pong data transfer operation, so that when the data to be sent is loaded into the sending shift register, the communication frequency can be divided by 2 of the system clock without waiting time. When the control unit 43 sends data from the slave to the master, if the SRAM memory module 30 determines that there is no system bus access, it only needs to spend 1 system clock time to store the received SPI data in the SRAM space of the corresponding address, thereby achieving high-efficiency and large-batch communication.

As an example, as shown in fig. 3, the control unit 43 includes: a clock conversion circuit 431, a first buffer 432, a second buffer 433, an update _ en signal generator 434, and a controller 435.

Referring to fig. 3, the clock conversion circuit 431 is used to convert the SPI intrinsic clock signal SCLK into the SPI operating clock signal SCLK _ COMB; the first buffer 432 is used for buffering data; the second buffer 433 is used for buffering data; the update _ en signal generator 434 is connected to the clock conversion circuit 431, and the update _ en signal generator 434 is configured to generate an update _ en signal, where the update _ en signal is inverted once every other rising edge in the SPI working clock signal SCLK with a preset value, and the preset value is determined by a read-write bit width of the SRAM memory module 30, for example, if the SRAM memory module 30 can read and write according to 8 bits, 16 bits, and 32 bits, the preset value may be corresponding to 8, 16, and 32. The controller 435 is respectively connected to the SRAM memory module 30, the update _ en signal generator 434, the first buffer 432 and the second buffer 433, and the controller 435 is configured to: when update _ en is equal to 1, loading the current cache data in the first buffer 432 to the sending shift register 41, acquiring the data currently required to be sent from the SRAM memory module 30, and caching the data currently required to be sent to the second buffer 433; when update _ en is equal to 0, the current buffered data in the second buffer 433 is loaded to the sending shift register 41, and the data that needs to be sent currently is obtained from the SRAM memory module 30, and the data that needs to be sent currently is buffered to the first buffer 432.

Taking the value of the preset value as 8 as an example, in the high-speed SPI communication device, every 8 SCLKs can complete one data reception, and then 1 system clock can load the data into the SRAM memory module 30. Specifically, when sending data, the SPI module 40 acquires data to be sent from the SRAM memory module 30 in a time-sharing manner by using ping-pong data transmission operation, so as to realize continuous SCLK transmission of data to the slave; when receiving data, the SPI module 40 sends a REQ request to the SRAM memory module 30, and when the SRAM memory module 30 determines that there is no system bus access, it only needs 1 system clock to store the received SPI data in the SRAM space of the corresponding address.

As an example, as shown in fig. 4, the clock conversion circuit 431 includes: a first not gate 4311, a first data selector 4312.

Referring to fig. 4, an input terminal of the first not gate 4311 is used for inputting the SPI intrinsic clock signal SCLK; the control terminal of the first data selector 4312 is used to input SPI clock polarity cpol (clock polarity) and clock phase cpha (clock phase), the first input terminal of the first data selector 4312 is connected to the output terminal of the first not gate 4311, the second input terminal of the first data selector 4312 is used to input SPI intrinsic clock signal SCLK, and the output terminal of the first data selector 4312 is used to output SPI working clock signal SCLK _ COMB.

Specifically, to simplify the communication timing of the SPI and reduce the area of the SPI module 40, the SPI module 40 may operate based on the converted SPI operating clock signal SCLK _ COMB. Referring to fig. 4, according to the difference between the CPHA and the CPOL, the SPI intrinsic clock signal SCLK obtains the SPI working clock signal SCLK _ COMB through the clock conversion circuit 431, and the rising edge of the SPI working clock signal SCLK _ COMB can be used for receiving data and the falling edge of the SPI working clock signal SCLK _ COMB can be used for sending data.

As one example, as shown in fig. 5, the controller 435 includes: a second not gate 4351, an or gate 4352, a first analog switch 4353, a third not gate 4354, an and gate 4355, a second analog switch 4356, and a second data selector 4357.

Referring to fig. 5, an input terminal of the second not gate 4351 is connected to the update _ en signal generator 434; a first input terminal of the or gate 4352 is connected to the IDLE port of the SPI module 40, and a second input terminal of the or gate 4352 is connected to an output terminal of the second not gate 4351; a first control end of the first analog switch 4353 is connected to an output end of the or gate 4352, an input end of the first analog switch 4353 is connected to the SRAM memory module 30, and an output end of the first analog switch 4353 is connected to the first buffer 432; an input terminal of the third not gate 4354 is connected to an output terminal of the second not gate 4351; first input of AND gate 4355 and SPI module 40

Second input of port connected with gate 4355The input end is connected with the output end of the third not gate 4354, and the output end of the and gate 4355 is connected with the second control end of the first analog switch 4353; a first control end of the second analog switch 4356 is connected to an output end of the third not gate 4354, a second control end of the second analog switch 4356 is connected to an output end of the second not gate 4351, an input end of the second analog switch 4356 is connected to the SRAM memory module 30, and an output end of the second analog switch 4356 is connected to the second buffer 433; a first input terminal of the second data selector 4357 is connected to the output terminal of the first buffer 432, a second input terminal of the second data selector 4357 is connected to the second buffer 433, a control terminal of the second data selector 4357 is connected to the update _ en signal generator 434, and an output terminal of the second data selector 4357 is connected to the transmission shift register 41.

Specifically, as shown in fig. 6, the rising edge update _ en signal at the 8 th clock of SCLK _ COMB is inverted once, and this signal is used for the ping-pong data transfer operation to load the data to be transmitted to the transmission shift register 41. Referring to fig. 5 and 6, when the SPI module 40 is in an IDLE state (i.e., IDLE is 0), once the high-speed SPI communication is started, the SRAM memory module 30 writes the first data to be transmitted into the first buffer 432; after the SPI module 40 starts to transmit data, the first buffer 432 and the second buffer 433 acquire data SRAM _ data _ in to be transmitted from the SRAM memory module 30 in a time-sharing manner, and ensure that the data of the 2 buffers is stable when the update _ en signal is inverted.

Referring to fig. 5 and 6, when the update _ en signal is inverted, the transmitting shift register 41 of the SPI module 40 updates data: updating the first buffer 432 data to the transmit shift register 41 when update _ en is 1; when update _ en is equal to 0, the second buffer 433 is updated to the transmission shift register 41. When update _ en is equal to 0, the first buffer 432 acquires a new data from the SRAM memory module 30; the second buffer 433 obtains a new data from the SRAM block 30 when update _ en is equal to 1. Through the above operation, no waiting time is required for updating the sending data by the SPI module 40, and the data is valid and stable when the data is sent on each falling edge of SCLK _ COMB. When update _ en is switched, the data in the first buffer 432 and the second buffer 433 are stable to ensure the validity of the data in the shift register 41, and when the next data is sent at the falling edge of SCLK _ COMB, the new data is valid and there is no glitch.

For ease of understanding, the communication principle of the high-speed SPI communication device of the embodiment of the present invention is described below in conjunction with fig. 2, fig. 4, fig. 5, fig. 7(a), and fig. 7 (b):

referring to fig. 7(b), when data transmission or data reception is required, the SPI module 40 sends a REQ request to the SRAM memory module 30 (i.e., sends a Tx _ REQ signal when data transmission is required; sends an Rx _ REQ signal when data reception is required); when determining that there is no system bus access currently, the SRAM memory module 30 sends an ACK response (the response corresponding to the Tx _ req signal is Tx _ ACK, and the response corresponding to the Rx _ req signal is Rx _ ACK) within 1 system clock, and completes the processing of transmitting data Tx _ data \ receiving data Rx _ data.

Specifically, referring to fig. 2 and 7(a), when the chip select signal CS _ N is low, the SPI module 40 starts to operate. When the SPI module 40 completes a data reception, the REQ request is sent to the SRAM memory module 30, and when the SRAM memory module 30 does not access the system bus, the SPI request (1 system clock) is responded in time, and the buffer data rx _ data received by the SPI module 40 is stored in the corresponding position of the SRAM memory module 30.

Referring to fig. 2 and 7(a), when the SPI module 40 is in the IDLE state, IDLE is 0, the SPI operating clock signal SCLK _ COMB starts to be generated, and the update _ en signal is inverted every time when the rising edges in SCLK _ COMB reach 8, and the transmission data tx _ data is "ping-pong" loaded to the transmission shift register 41.

In summary, the high-speed SPI communication module according to the embodiment of the present invention may adopt ping-pong data transmission operation through the SPI module, and acquire data to be transmitted from the SRAM memory module in a time-sharing manner, thereby realizing high-speed and large-batch data transmission; when the SPI module finishes receiving a data, the received data can be loaded to the SRAM storage module, and then the data can be received at high speed in a large batch.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims

1. A high speed SPI communication device, comprising:

the SRAM storage module is connected with the host through the AHB bus interface module and used for loading communication data;

and the SPI module is connected with the SRAM storage module, is connected with a slave through an SPI bus interface, and is used for acquiring data to be transmitted from the SRAM storage module in a time-sharing mode by utilizing ping-pong data transmission operation when the host transmits the data to the slave, and continuously transmitting the data to be transmitted to the slave.

2. A high speed SPI communication device according to claim 1, wherein said SPI module comprises:

the transmitting shift register is connected with the slave machine through the SPI bus interface module;

and the control unit is respectively connected with the SRAM storage module and the sending shift register and is used for acquiring data to be sent from the SRAM storage module in a time-sharing mode by utilizing ping-pong data transmission operation when the host sends the data to the slave and loading the data to be sent to the sending shift register.

3. A high-speed SPI communication device according to claim 2, wherein said control unit comprises:

the clock conversion circuit is used for converting the SPI inherent clock signal into an SPI working clock signal;

the first buffer is used for buffering data;

the second buffer is used for buffering data;

the update _ en signal generator is connected with the clock conversion circuit and used for generating an update _ en signal, wherein the update _ en signal is inverted once every preset number of rising edges in the SPI working clock signal;

a controller, connected to the SRAM storage module, the update _ en signal generator, the first buffer, and the second buffer, respectively, the controller being configured to:

when update _ en is equal to 1, loading the current cache data in the first buffer to the sending shift register, acquiring the data which needs to be sent currently from the SRAM storage module, and caching the data which needs to be sent currently to the second buffer,

and when update _ en is equal to 0, loading the current cache data in the second buffer to the sending shift register, acquiring the data which needs to be sent currently from the SRAM storage module, and caching the data which needs to be sent currently to the first buffer.

4. A high-speed SPI communication device according to claim 3, wherein said clock conversion circuitry comprises:

a first not gate, an input terminal of which is used for inputting the SPI inherent clock signal;

the control end of the first data selector is used for inputting SPI clock polarity and clock phase, the first input end of the first data selector is connected with the output end of the first NOT gate, the second input end of the first data selector is used for inputting the SPI inherent clock signal, and the output end of the first data selector is used for outputting the SPI working clock signal.

5. A high speed SPI communication device according to claim 3, wherein said controller comprises:

a second not gate, an input terminal of the second not gate being connected with the update _ en signal generator;

an or gate, a first input end of the or gate being connected to the IDLE port of the SPI module, a second input end of the or gate being connected to the output end of the second not gate;

a first control end of the first analog switch is connected with an output end of the OR gate, an input end of the first analog switch is connected with the SRAM storage module, and an output end of the first analog switch is connected with the first buffer;

a third not gate, an input terminal of the third not gate being connected to an output terminal of the second not gate;

and the first input end of the AND gate and the SPI module

The second input end of the AND gate is connected with the output end of the third NOT gate, and the output end of the AND gate is connected with the second control end of the first analog switch;

a first control end of the second analog switch is connected with an output end of the third not gate, a second control end of the second analog switch is connected with an output end of the second not gate, an input end of the second analog switch is connected with the SRAM storage module, and an output end of the second analog switch is connected with the second buffer;

a first input end of the second data selector is connected with an output end of the first buffer, a second input end of the second data selector is connected with the second buffer, a control end of the second data selector is connected with the update _ en signal generator, and an output end of the second data selector is connected with the transmission shift register.

6. A high speed SPI communication device according to claim 1, wherein said SPI module is further configured to:

when the host sends data to the slave, first request information is sent to the SRAM storage module, a sending address corresponding to the SRAM storage module is obtained according to the request information, and the data needing to be sent is obtained from a storage space corresponding to the sending address by utilizing ping-pong data transmission operation.

7. A high-speed SPI communication device according to claim 3, wherein said predetermined value is 8.