CN113467696B - Multichannel AD data synchronous transmission system - Google Patents
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- CN113467696B CN113467696B CN202110730530.1A CN202110730530A CN113467696B CN 113467696 B CN113467696 B CN 113467696B CN 202110730530 A CN202110730530 A CN 202110730530A CN 113467696 B CN113467696 B CN 113467696B
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Abstract
The invention discloses a multichannel AD data synchronous transmission system, which aims to solve the synchronous design problem caused by the disassembly of a radio frequency front end and an intermediate frequency baseband. The invention is realized by the following technical scheme: the external clock source input clock management module generates a reference clock of the ADC/DAC chip and a multi-frame reference clock according to the sampling rate and provides the reference clock and the multi-frame reference clock for the FPGA; the FPGA phase-locked loop multiplies the logic clock input by the clock management module to obtain a working clock, and keeps the working clock, SYSREF and the logic clock in phase synchronization; the JESD204B interface circuit physical layer parallel/serial conversion unit in the FPGA module uses a high-speed serial transceiver with a crystal oscillator for providing a reference clock, and a clock signal generated by the crystal oscillator is used as a reference clock signal of the physical layer parallel/serial conversion unit; and finally, the synchronous transmission of the FPGA to the multiple ADC/DAC data is realized by processing the key control signal synchronous signals in the FPGA module.
Description
Technical Field
The invention relates to a data acquisition and transmission system for signal processing, in particular to a multichannel AD data synchronous transmission system.
Background
With the development of digital receiving/transmitting technology, the continuous improvement of sampling rate and resolution ratio, the design requirements of multi-channel, high-bandwidth, miniaturized and modularized large-scale data synchronous transmission are more and more urgent. The JESD204B protocol formulated by the solid state technology association is a transmission protocol in which a high-speed analog-to-digital/digital converter is connected to a back-end digital signal processing device through a serial interface link, and has a maximum transmission rate of 12.5Gbps, a small number of interface pins, and supports multi-channel synchronous transmission. For the converter working at 500MSPS and above, the JESD204B sub-1 interface introduces an external reference signal SYSREF to determine the delay, and the reference signal provides a system level standard for the sampling time sequence, has the capability of multi-channel alignment serial channels and delay control, and does not need to use an additional circuit at an external application layer to meet the requirement of deterministic delay in design. However, due to the limitation of the layout density of the circuit board, how to realize the deterministic delay of the multi-channel ADC/DAC and realize the synchronous transmission of large-scale data, complex circuit design and accurate clock synchronous design are required. The multichannel DAC synchronization method generally uses the correlation between the feedback clock and the data of the DAC, acquires asynchronous phase feedback by analyzing the phase difference of the feedback clock, and then resets or compensates the phase to realize the new synchronization of the ADC/DAC. With the continuous rise of the frequency of the feedback clock, the pressure of the signal phase demodulation circuit is larger and larger. Analog and analog-to-digital hybrid circuits often have the disadvantages of complex circuits, susceptibility to temperature effects, inflexibility, and the like. Generally, for a lower speed ADC, it is easier to meet the SYSREF setup and hold time, and for a faster AD chip, a higher device clock rate reduces the SYSREF signal setup and hold time, sometimes requiring the necessary dynamic delay adjustment to meet timing requirements under different conditions. When all clocks in the system have no clock rate twice as high as other clocks, i.e. a plurality of clocks in the system have poor rates, the sampling theorem cannot be satisfied at this time, for example, in a high-speed data acquisition system, the acquisition clock of the AD is often higher than half of the system clock, and the synchronization processing cannot be satisfied at this time. Since the ADC/DAC circuits collect signals from different clock sources, the circuits may be present on the same chip or on different ADC/DAC chips, but all present the same risk.
In the design of synchronous FPGA hardware, the functions of a local clock unit, a clock protocol module, a sending buffer, a receiving buffer, a system time marking and the like are realized in the FPGA. The clock is the most important and special signal in the whole design, and the asynchronous signal input cannot always meet the set-up and hold time of data, so all asynchronous inputs need to be synchronized first. In general, logic within an FPGA device performs data input and output processing once on the rising edge of each clock cycle, and can be used to perform a wide variety of complex processing during the idle time of the rising edges of two clocks. A complex operation process which is time-consuming often cannot be completed in one clock cycle. Synchronous clock message detection circuit or multichannel ultra-high speed MUXDAC/DEMUXADC based on FPGA is usually realized mainly by digital signal processing mode of FPGA. It is difficult to implement a truly random sampling clock in FPGA with digital methods, and in order to get more accurate statistics, the number of samples must be large enough, which requires longer sampling times and arithmetic unit support, both of which are often limited in practical systems. Although the FPGA-based complex algorithm can obtain very high phase detection precision, two inherent defects exist in solving the problem of ADC/DAC synchronization: firstly, complex algorithms and peripheral auxiliary circuits need to be designed; secondly, when the frequency of the feedback clock exceeds the bearing capacity of the input and output pins of the FPGA, the error rate of sampled data is improved, so that the performance of the algorithm phase discrimination method is greatly deteriorated. In actual operation, a power-on reset may cause the divide-by-4 device to count from a fixed phase. However, due to electromagnetic interference, temperature and other reasons, the digital frequency divider device can easily generate phase jump, so that the multi-ADC/DAC is asynchronous, at the moment, the feedback clock has a fixed phase difference, and corresponding fixed phase difference is generated for data transmission. In the traditional JESD204B protocol-based multichannel data synchronous transmission system design, in order to meet clock homology and multichannel deterministic delay of an ADC/DAC and a transceiver device and ensure a strict time sequence relationship between the device clock and the data synchronous clock, the transceiver device and the ADC/DAC are often laid out on the same printed board, and the system requirement that a radio frequency front end and an intermediate frequency baseband are required to be separated into mutually independent structures under partial application scenes cannot be met.
Most high-speed ADCs/DACs currently on the market support the use of the JESD204B subclass 1 interface. The JESD204B protocol specifies three layers, including a physical layer, a link layer, and a transport layer. The physical layer mainly realizes the functions of transmitting and receiving characters such as serial-parallel conversion, de-emphasis and the like; the link layer mainly realizes the recovery and synchronous output functions of 8B/10B encoding and decoding, control byte insertion or detection and other user data; the transport layer mainly realizes the mapping of the data frames and the sample data. The main stream FPGA manufacturer provides JESD204B physical layer and link layer IPcore and provides recommended design scheme, and the corresponding parameters are only required to be set according to the design requirement during application. Two clock signals need to be provided when using IP: the physical layer parallel/serial conversion unit reference clock signal and the device clock processed by the link layer JESD204B protocol require a stable, low jitter reference clock input for the high speed serial transceiver, the device clock processed by the link layer JESD204B protocol is one-fortieth of the serial rate and requires homology to the interfacing AD/DA reference clock to ensure that the SYSREF is properly sampled by the device clock. In the conventional design, the physical layer parallel/serial conversion unit reference clock signal and the device clock processed by the link layer JESD204B protocol are generated on the printed board using the same clock source. When the radio frequency front end and the intermediate frequency baseband are split, if the reference clock signal of the physical layer parallel/serial conversion unit is generated by the clock management unit, a special clock device needs to be added to ensure the jitter and noise performance of the clock signal through long-distance transmission.
Disclosure of Invention
Aiming at the problems, the invention provides a multichannel ADC/DAC synchronous interface circuit which has the advantages of modularized design, convenient expansion, simpler clock circuit design and high applicability, so as to solve the design problem caused by the disassembly of the radio frequency front end and the intermediate frequency baseband and realize a multichannel data synchronous transmission system based on JESD204B protocol.
To achieve the above object, a multi-channel AD data synchronous transmission system includes: the clock management module is input by an external clock source, the large-scale programmable gate array FPGA module is connected with the crystal oscillator and the external clock source at the same time, and the multichannel analog-to-digital converter ADC and the digital-to-analog converter DAC are connected between the clock management module and the FPGA module in parallel, and the clock management module is characterized in that: the external clock source input clock management module generates a reference clock and a multi-frame reference clock (SYSREF) of an ADC/DAC chip according to the sampling rate, provides the reference clock and the multi-frame reference clock SYSREF for each ADC/DAC, inputs a synchronous logic clock of a Field Programmable Gate Array (FPGA), uses a frequency multiplication signal as a device clock for link layer JESD204B protocol processing after being processed by a phase-locked loop in the FPGA, uses a frequency division signal as the multi-frame reference clock SYSREF, and determines phase-locked loop frequency multiplication and frequency division parameters according to the sampling rate and the input synchronous logic clock frequency to realize homology between the device clock for JESD204B protocol processing in the FPGA module and the ADC/DAC reference clock; the JESD204B interface circuit physical layer parallel/serial conversion unit in the FPGA module uses a high-speed serial transceiver with a crystal oscillator providing a reference clock, a clock signal generated by the crystal oscillator is used as a reference clock signal of the physical layer parallel/serial conversion unit, after the system is powered on, a receiving end of the FPGA module resets a SYNC_RX synchronizing signal to send a synchronizing requirement, and an ADC sends a synchronizing code to wait for link establishment; after all receiving channels are successfully built, the FPGA module sets SYNC_RX to inform the ADC, and the ADC sends sampling data to realize the synchronous sampling of multiple channels of the ADC; after the FPGA is powered on and reset, a synchronous code is sent, and a synchronous signal SYNC_TX input by a DAC is detected; after detecting that SYNC_TX synchronous signals input by all the DACs are set, the FPGA sends corresponding data to the JESD204B interface circuit, and converts frame data into high-speed serial data required by the DACs, so that multi-disc DAC data multi-channel synchronous transmission is finally realized.
Compared with the prior art, the invention has the following beneficial effects:
based on JESD204B protocol, the invention adopts an external clock source to input a clock management module, and simultaneously connects a crystal oscillator and an FPGA module of the external clock source, and a multichannel analog-digital converter ADC and a multichannel digital-analog converter DAC which are connected between the clock management module and the FPGA module in parallel are split and designed. Compared with the traditional implementation method based on the FPGA algorithm, theoretical analysis and experiments show that the circuit has no false alarm and no false alarm probability, is a simple and high-reliability multi-channel ADC/DAC synchronous interface circuit, and provides a simple and feasible solution for synchronous monitoring of multiple DE-MUXADC/MUXDAC.
The invention adopts the FPGA module phase-locked loop to multiply the logic clock input by the clock management module to obtain the working clock and divide the frequency to obtain SYSREF, and keeps the phase synchronization of the working clock, the SYSREF and the logic clock so as to ensure that the JESD204B interface circuit and the ADC/DAC interface circuit of the FPGA meet the clock synchronization requirement; after the synchronous logic clock input into the FPGA is processed by a phase-locked loop in the FPGA, the frequency multiplication signal is used as a device clock processed by a link layer JESD204B protocol, the frequency division signal is used as SYSREF, the phase-locked loop frequency multiplication and frequency division parameters are determined according to the sampling rate and the input synchronous logic clock frequency, the homology of the device clock processed by the JESD204B protocol in the FPGA module and the ADC/DAC reference clock is realized, and the introduction of the clock signal not only enables all digital operation processes to be quantized, but also can synchronize various irrelevant operation processes to one beat to cooperate. The method has the advantages that the characteristics of frequency division and frequency multiplication of the clock in the FPGA are utilized, the homology of the processing clock of the FPGA and SYSREF with the ADC/DAC reference clock is guaranteed, and the design difficulty of the clock circuit is reduced while the synchronization of the receiving multi-channel and the sending multi-channel is realized.
The invention adopts the JESD204B interface circuit physical layer parallel/serial conversion unit in the FPGA module, and uses the high-speed serial transceiver with the reference clock provided by the crystal oscillator, and the clock signal generated by the crystal oscillator is used as the reference clock signal of the physical layer parallel/serial conversion unit, so that the addition of a special clock device can be avoided, the wiring difficulty of a printed board is reduced, and the like.
The multichannel data synchronous transmission system designed by the invention has good universality.
Drawings
Fig. 1 is a schematic circuit diagram of a multichannel AD data synchronous transmission system according to the present invention; the proposed schematic diagram of a JESD204B protocol-based multichannel data synchronous transmission system;
fig. 2 is a schematic diagram of the FPGA synchronous interface clock circuit of fig. 1.
Detailed Description
As shown in fig. 1, in the preferred present embodiment described below, a multi-channel AD data synchronous transmission system includes: the clock management module is input by an external clock source, the large-scale programmable gate array FPGA module is connected with the crystal oscillator and the external clock source at the same time, and the multichannel analog-to-digital converter ADC and the digital-to-analog converter DAC are connected between the clock management module and the FPGA module in parallel, and the clock management module is characterized in that: the clock management module generates a reference clock and a multi-frame reference clock (SYSREF) of the ADC/DAC chip according to the sampling rate, provides the reference clock and the multi-frame reference clock SYSREF for each ADC/DAC, and provides a synchronous logic clock for the FPGA module; after a synchronous logic clock input into a Field Programmable Gate Array (FPGA) is processed in the FPGA through a phase-locked loop, a frequency multiplication signal is used as a device clock processed by a link layer JESD204B protocol, a frequency division signal is used as a multi-frame reference clock (SYSREF), phase-locked loop frequency multiplication and frequency division parameters are determined according to a sampling rate and the input synchronous logic clock frequency, and the homology of the device clock processed by the JESD204B protocol in the FPGA module and the ADC/DAC reference clock is realized; the JESD204B interface circuit physical layer parallel/serial conversion unit in the FPGA module uses a high-speed serial transceiver with a crystal oscillator providing a reference clock, a clock signal generated by the crystal oscillator is used as a reference clock signal of the physical layer parallel/serial conversion unit, after the system is powered on, a receiving end of the FPGA module resets a SYNC_RX synchronizing signal to send a synchronizing requirement, and an ADC sends a synchronizing code to wait for link establishment; after all receiving channels are successfully built, the FPGA module sets SYNC_RX to inform the ADC, and the ADC sends sampling data to realize the synchronous sampling of multiple channels of the ADC; after the FPGA is powered on and reset, a synchronous code is sent, and a synchronous signal SYNC_TX input by a DAC is detected; after detecting that SYNC_TX synchronous signals input by all the DACs are set, the FPGA sends corresponding data to a JESD204B interface circuit, and the JESD204B interface circuit converts frame data into high-speed serial data required by the DACs, so that multi-piece DAC data multi-channel synchronous transmission is finally realized.
The ADC/DAC reference clock is provided by the clock management module and the frequency value is determined by the sampling rate and the high-speed serial transceiver phase-locked loop input allowed value range.
The clock source input clock management module isolates the ADC/DAC reference clock from the multilevel clock network or from the multilevel clock and data through the FIFO at the parallel DAC high-speed serial interface, and the multiplexer converts the ADC/DAC reference clock information into an enable signal synchronous with the system clock.
The FPGA phase-locked loop multiplies a logic clock input by the clock management module to obtain a working clock, frequency division is carried out to obtain SYSREF, the working clock, the SYSREF and the logic clock are kept in phase synchronization, the working clock is used as a device clock for JESD204B protocol processing, the SYSREF is used as a multi-frame reference clock for JESD204B protocol processing, and the JESD204B interface circuit clock and the ADC/DAC clock of the FPGA are homologous.
The FPGA synchronous interface clock circuit is based on a serial interface clock circuit of the FPGA, performs synchronous processing on clocks at a DAC high-speed serial interface, samples by clock edges of clk, outputs by a trigger to a rising edge extraction circuit through combinational logic, extracts a bit synchronous clock signal from an asynchronous serial code stream, processes DAC clock sampling of the bit synchronous clock signal into a clock signal synchronous with SysClk, and outputs clock information with a final operation result after a plurality of clock rising edges in rising edge extraction output information. The advantage of such processing is that it facilitates the processing of the internal timing of the circuit, which is beneficial to ensuring the reliability and portability of the circuit.
In the embodiment of the invention, the FPGA of the field programmable gate array is XILINX FPGA, and JESD204B physical layer and link layer circuits are directly developed by using corresponding IPcore; assuming that the reference clock REFCLK frequency point of the field programmable gate array FPGA high-speed serial transceiver can be selected to be 100MHz, 125MHz or 156.25MHz when the link speed is 5Gbps, namely, the crystal oscillator frequency on the field programmable gate array FPGA board card is selected to be one; the device clock TX/RX_CORE_CLK frequency processed by JESD204B protocol is 125MHz and SYSREF frequency is 7.8125MHz, so the FPGA synchronous logic clock frequency can be configured to be 25MHz; the clock management module outputs a 25MHz clock to the FPGA, and TX/RX_CORE_CLK and SYSREF are obtained in the FPGA through a clock unit Clockingwizard.
For ease of understanding, the following describes the clock circuit portion further with reference to fig. 2.
As shown in fig. 2, the FPGA synchronous interface clock circuit includes: the serial transceiver dedicated clock buffer ibufds_gte2 is connected to the local crystal oscillator, the clock unit ClockingWizard, JESD B generating the homologous clock interfaces the JESD204PHY and the link layer JESD204CORE LOGIC, the local crystal oscillator sends differential clock signals into ibufds_gte2, sends reference clock signals into the JESD204B interface physical layer JESD204PHY through ibufds_gte2 differential to single ended, and simultaneously the clock management module outputs a 25MHz homologous clock to the clock unit ClockingWizard, clockingWizard, sends 125MHz LOGIC clocks into the JESD204B interface physical layer JESD204PHY and the link layer JESD204CORE LOGIC through the clock ports TX/rx_core_clk, and inputs 7.8125MHz multi-frame reference clocks SYSREF into the JESD204CORE LOGIC, so that each clock in the FPGA synchronizes the 25MHz clock output by the clock management module.
The clock divider control module includes two main components: serial and parallel clock dividers and their selector controls, the RX portion of each GTX/GTH transceiver has only one CPLL phase locked loop, and the PMA block of each transmitter has a D divider for dividing the clock from the PLL to produce the desired line rate clock, which can be set to either a static configuration for a fixed line rate or a dynamic configuration for a varying line rate. The GTX/GTH transceiver incorporates a PRBS checker to test channel signal integrity, a decoder to support 2 byte, 4 byte and 8 byte data path operations, which generates K code characters and status information output, and may be bypassed if the received data is not 8B/10B encoded, ibufds_gte2 primitive to drive the GTX reference clock. In general, the field programmable gate array FPGA utilizes a phase-locked loop to realize the required clock phase synchronization, reduces the number of required input clocks and clock frequency points, and simultaneously realizes the synchronous transmission of multichannel data based on a JESD204 protocol by processing synchronous signals.
Any feature disclosed in this specification, including any accompanying claims, abstract, and drawings, may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Claims (10)
1. A multi-channel AD data synchronous transmission system comprising: the clock management module is input by an external clock source, the large-scale programmable gate array FPGA module is connected with the crystal oscillator and the external clock source at the same time, and the multichannel analog-to-digital converter ADC and the digital-to-analog converter DAC are connected between the clock management module and the FPGA module in parallel, and the clock management module is characterized in that: the external clock source input clock management module generates a reference clock and a multi-frame reference clock SYSREF of an ADC/DAC chip according to the sampling rate, provides the reference clock and the multi-frame reference clock SYSREF for each ADC/DAC, inputs a synchronous logic clock of a field programmable gate array FPGA, uses a frequency multiplication signal as a device clock processed by a link layer JESD204B protocol after being processed by a phase-locked loop in the FPGA, uses a frequency division signal as the multi-frame reference clock SYSREF, and determines phase-locked loop frequency multiplication and frequency division parameters according to the sampling rate and the input synchronous logic clock frequency to realize homology between the device clock processed by the JESD204B protocol in the FPGA module and the ADC/DAC reference clock; the JESD204B interface circuit physical layer parallel/serial conversion unit in the FPGA module uses a high-speed serial transceiver with a crystal oscillator providing a reference clock, a clock signal generated by the crystal oscillator is used as a reference clock signal of the physical layer parallel/serial conversion unit, after the system is powered on, a receiving end of the FPGA module resets a SYNC_RX synchronizing signal to send a synchronizing requirement, and an ADC sends a synchronizing code to wait for link establishment; after all receiving channels are successfully built, the FPGA module sets SYNC_RX to inform the ADC, and the ADC sends sampling data to realize the synchronous sampling of multiple channels of the ADC; after the FPGA is powered on and reset, a synchronous code is sent, and a synchronous signal SYNC_TX input by a DAC is detected; after detecting that SYNC_TX synchronous signals input by all the DACs are set, the FPGA sends corresponding data to the JESD204B interface circuit, and converts frame data into high-speed serial data required by the DACs, so that multi-disc DAC data multi-channel synchronous transmission is finally realized.
2. The multi-channel AD data synchronous transmission system according to claim 1, wherein: the clock source input clock management module isolates the ADC/DAC reference clock from the multilevel clock network or from the multilevel clock and data through the FIFO at the parallel DAC high-speed serial interface, and the multiplexer converts the ADC/DAC reference clock information into an enable signal synchronous with the system clock.
3. The multi-channel AD data synchronous transmission system according to claim 1, wherein: the FPGA phase-locked loop multiplies the logic clock input by the clock management module to obtain a working clock, divides the frequency to obtain a multi-frame reference clock SYSREF, and keeps the working clock, SYSREF and the logic clock in phase synchronization.
4. The multi-channel AD data synchronous transmission system according to claim 1, wherein: the FPGA synchronous interface clock circuit is based on a serial interface clock circuit of the FPGA, performs synchronous processing on clocks at a DAC high-speed serial interface, samples by clock edges of a clock clk, outputs by a trigger to a rising edge extraction circuit through combinational logic, extracts a bit synchronous clock signal from an asynchronous serial code stream, and performs sampling processing on the DAC clock of the bit synchronous clock signal into a clock signal synchronous with SysClk.
5. The multi-channel AD data synchronous transmission system according to claim 1, wherein: the FPGA is XILINX FPGA, and JESD204B physical layer and link layer circuits are directly developed by using corresponding IP cores (IPcore); the FPGA phase-locked loop multiplies the logic clock input by the clock management module to obtain a working clock, frequency division is carried out to obtain SYSREF, and the working clock, the multi-frame reference clock SYSREF and the logic clock are kept in phase synchronization, so that the JESD204B interface circuit clock of the FPGA is homologous to the ADC/DAC clock.
6. The multi-channel AD data synchronous transmission system according to claim 1, wherein: when the FPGA high-speed serial transceiver works at the link speed of 5Gbps, the reference clock REFCLK frequency point of the FPGA high-speed serial transceiver is selected to be 100MHz, 125MHz or 156.25MHz, namely, one of the crystal oscillator frequencies on the FPGA board card is selected.
7. The multi-channel AD data synchronous transmission system of claim 5 wherein: the device clock TX/RX_CORE_CLK frequency processed by JESD204B protocol is 125MHz, the multi-frame reference clock SYSREF frequency is 7.8125MHz, and the FPGA synchronous logic clock frequency is configured to be 25MHz; the clock management module outputs a 25MHz clock to the FPGA, and TX/RX_CORE_CLK and SYSREF are obtained in the FPGA through a clock unit Clockingwizard.
8. The multi-channel AD data synchronous transmission system according to claim 1, wherein: the FPGA synchronous interface clock circuit comprises: the serial transceiver differential signal buffer IBUFDS_GTE2 is connected with the local crystal oscillator, the clock unit ClockingWizard, JESD B for generating homologous clocks is connected with the JESD204PHY and the link layer JESD204CORE LOGIC, the local crystal oscillator sends differential clock signals into the differential signal buffer IBUFDS_GTE2, sends reference clock signals into the JESD204B interface JESD204PHY through the IBUFDS_GTE2 differential to single-ended, meanwhile, the clock management module outputs a 25MHz homologous clock to the clock unit Clockingwizard, sends working clocks with the frequency of 125MHz into the JESD204B interface physical layer JESD204PHY and the link layer JESD204CORE LOGIC through the clock ports TX/RX_CORE_CLK respectively, and inputs multi-frame reference clocks SYSREF with the frequency of 7.8125MHz into the JESD204CORE LOGIC, so that the clocks in the FPGA are synchronized with 25MHz clock output by the clock management module.
9. The multi-channel AD data synchronous transmission system according to claim 1, wherein: the clock divider control module includes: serial clock divider and parallel clock divider and their selector controls, the RX portion of each FPGA high-speed transceiver GTX/GTH has only one charge pump structured phase-locked loop CPL, the PMA module of each transmitter has a D-divider for dividing the clock from the phase-locked loop PLL to generate the required line-rate clock, and the D-divider sets a static configuration for a fixed line-rate or a dynamic configuration for a varying line-rate.
10. The multi-channel AD data synchronous transmission system according to claim 9, wherein: the FPGA high-speed transceiver GTX/GTH incorporates a PRBS checker to test channel signal integrity and a decoder to support 2 byte, 4 byte and 8 byte data path operations that generates K-code characters and status information output, bypassing the decoder if the received data is not 8B/10B encoded, differential signal buffer ibufds_gte2 primitive driving the GTX reference clock.
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