CN113466898B

CN113466898B - Correlator circuit for GNSS, GNSS receiver and signal receiving method thereof

Info

Publication number: CN113466898B
Application number: CN202110806805.5A
Authority: CN
Inventors: 顾明飞; 杨小勇; 秦奇波
Original assignee: Spreadtrum Semiconductor Chengdu Co Ltd
Current assignee: Spreadtrum Semiconductor Chengdu Co Ltd
Priority date: 2021-07-16
Filing date: 2021-07-16
Publication date: 2022-08-19
Anticipated expiration: 2041-07-16
Also published as: CN113466898A

Abstract

The embodiment of the invention provides a correlator circuit for GNSS, a GNSS receiver and a signal receiving method thereof. The correlator circuit comprises a tracking FIFO module which generates k sampled signals; a chip control module that calculates a slice overflow value; an enable and bit polarity generation module calculating an enable signal and a bit polarity signal; a channel module, wherein each partial correlator receives an enable signal and a bit polarity signal, and thus parallel processing is performed to obtain a calculation result; a channel selection module that receives the calculation result; the multi-path correlation value calculating module is used for sequentially receiving the calculation results output by the channel selecting module in each calculation and accumulating the calculation results to obtain multi-path correlation values; a loop adjustment module that outputs a multi-path correlation value based on the multi-path correlation value. This can effectively avoid repeated operations and greatly reduce the operation time.

Description

Correlator circuit for GNSS, GNSS receiver and signal receiving method thereof

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a correlator circuit for a GNSS, a GNSS receiver, and a method for receiving a signal thereof.

Background

The Global Navigation Satellite System (GNSS) has the advantages of high precision, extremely wide range, no time constraint and the like, and plays an important role in various fields of national defense construction and social economic development.

In the process of receiving satellite navigation signals, the phase of a local code sequence generated in a GNSS receiver and the phase of a received signal must be aligned to realize data reception, wherein the acquisition mainly utilizes a correlator to realize initial value and frequency offset estimation of code phase, the estimation of code phase value and frequency offset is relatively rough, and the tracking utilizes a multi-path correlator to realize accurate calculation of code phase on the basis of acquisition.

However, the multipath correlators of each channel in the GNSS receiver are calculated independently from each other, so that the resource consumption is high, the operation efficiency is poor, and the adaptability to multiple channels is also poor.

Disclosure of Invention

The technical problems solved by the invention are that the GNSS receiver has more resource consumption, poorer operation efficiency and the like.

To solve the above technical problem, an embodiment of the present invention provides a correlator circuit for GNSS, including:

a tracking FIFO module adapted to generate k sampled signals, the k sampled signals being obtained based on sampling of digital signals related to satellite navigation signals, where k is an integer greater than 0;

a chip control module adapted to acquire a local code, segment the local code based on a fixed number of slices, calculate slice overflow values respectively corresponding to the k sampling signals based on code _ nco and nco control words, and update the number of slices used and code _ nco based on the slice overflow values;

an enable and bit polarity generation module adapted to receive the fixed slice number, the used slice number, and the slice overflow value, calculate k control signals respectively corresponding to the k sampling signals based on the three, and calculate a specific enable signal and a bit polarity signal based on any one of the k control signals;

a channel module comprising n channels, each of the n channels comprising m partial correlators, each of the n channels being adapted to receive an enable signal and a bit polarity signal, so as to process respective sampled signals in parallel to obtain a calculation result, wherein n and m are integers greater than 0;

a channel selection module, which is suitable for selecting 1 channel from n channels each time and receiving the calculation result output by partial correlator in the channel;

the multi-path correlation value calculating module is suitable for receiving the calculation results output by the channel selecting module in each round of calculation in sequence and accumulating the calculation results to obtain multi-path correlation values;

and the loop adjusting module is suitable for receiving the multi-path correlation values and judging whether the multi-path correlation values reach a peak value or not, if so, the multi-path correlation values are output, and if not, the loop adjusting module performs loop adjustment on the chip control module and each of the plurality of channels until the multi-path correlation values reach the peak value.

Optionally, the correlator circuit comprises a control module adapted to output the sampled signals to the n channels when the sampled signals stored in the tracking FIFO module exceed a first threshold, stop the n channels from receiving the sampled signals and trigger the multi-path correlation value calculation module to calculate the multi-path correlation values when the time to generate the code _ nco reaches a second threshold, and end one round of calculation until the amount of data reaches a third threshold.

Optionally, the second threshold is an integer multiple of the code _ nco period.

Optionally, the chip control module is adapted to calculate slice overflow values corresponding to the k sampled signals, respectively, based on:

at the current clock beat, the code _ nco _ i [ d + a-1:0] is obtained based on the following formula:

code_nco_i[d+a-1:0]＝code_nco[d-1:0]+code_freq[d-1:0]*b，

updating code _ nco [ d-1:0] to code _ nco _ k [ d-1:0] in the next clock beat;

the slice overflow value, which includes the initial slice overflow value, is set to 0,

a slice overflow value code _ inv _ ovf _ i is obtained based on the following formula:

code_inv_ovf_i＝code_nco_i[d+a-1:d]，

the code _ nco _ i is a specific code _ nco, bits from 0 th bit to d + a-1 th bit in the code _ nco are taken from the code _ nco, bits from d bit to d + a-1 th bit in the code _ nco are taken from the code _ nco _ i [ d + a-1:0], bits from d bit to d + a-1 th bit in the code _ nco are taken from the code _ nco, i is an integer which is greater than 0 and less than or equal to k, a and b are integers which are greater than 0 and less than or equal to k, d is a fixed bit depth which is an integer which is greater than 1, and code _ freq [ d-1:0] is the step controlled by the nco control word.

Optionally, the enable and bit polarity generation module is adapted to set the ith control signal prn _ acc _ i based on the following formula:

active_acc_max＝active_corr+code_inv-1，

when prn _ acc _ i is greater than or equal to active _ acc _ max, making prn _ acc _ i equal to 0, where active _ acc _ max is the maximum number of relevant paths, active _ corr is the number of relevant paths preset in the multi-path relevant value calculation module, and code _ inv is the number of fixed slices.

Optionally, the enable and bit polarity generation module is adapted to obtain the ith control signal prn _ acc _ i based on the following formula:

prn_acc_i＝prn_acc_0+code_inv*i，

prn_acc_0＝(prn_cnt_i+code_inv_ovf_i)mod code_inv；

the ith control signal prn _ acc _ i corresponds to the ith sampling signal, prn _ acc _0 is an initial control signal, prn _ cnt _ i is the number of used slices corresponding to the ith sampling signal, code _ inv _ ovf _ i is a slice overflow value corresponding to the ith sampling signal, and mod represents a modulus value.

Optionally, the enable and bit polarity generation module is adapted to obtain an enable signal prn _ acc _ j _ en _ sap _ i of a jth partial correlator in the m partial correlators with respect to an ith sampling signal based on the following formula:

prn_acc_j_en_sap_i＝prn_acc_en_group_i[j]，

prn_acc_en_group_k[m-1:0]＝

(1< < prn _ acc _0) | (1< < prn _ acc _1) | … … | (1< < prn _ acc _ k), where j is an integer greater than 0 and less than or equal to m, and prn _ acc _ en _ group _ k [ m-1:0] are obtained by shifting bits corresponding to the respective control signals to the left based on 1 and then performing bit-wise or operations in sequence, and prn _ acc _ en _ group _ i [ j ] is an enable signal of the ith sample signal at the jth partial correlator, and is obtained based on prn _ acc _ en _ group _ k [ m-1:0 ].

Optionally, the enabling and bit polarity generating module is adapted to obtain a bit polarity signal prn _ mask _ pair _ j _ sap _ i of a jth partial correlator in the m partial correlators with respect to an ith sampling signal based on the following steps:

the prn _ i _ acc _ bit _ ij is obtained based on the following formula:

prn_i_acc_bit_ij＝prn_i_mask_i，

prn_i_mask_i＝((1<<(prn_acc_i+code_inv_ovf_k-code_inv_ovf_i))&

prn_reg)，

the method comprises the following steps that a prn _ i _ acc _ bit _ ij is an intermediate parameter of a jth partial correlator about an ith sampling signal, a prn _ i _ mask _ i is a mask of the ith sampling signal, a code _ inv _ ovf _ k is a slice overflow value corresponding to the kth sampling signal, and a prn _ reg is a code _ nco stored in a slice register;

performing OR operation on prn _ i _ acc _ bit _0j, prn _ i _ acc _ bit _1j and prn _ i _ acc _ bit _ kj to obtain a selection signal prn _ i _ mask _ bit _ sel _ j of the jth partial correlator relative to the ith sampling signal;

the bit polarity signal prn _ mask _ pair _ j _ sap _ i is obtained based on the following formula:

prn_mask_pair_j_sap_i＝prn_i_mask_bit_sel_j。

optionally, the j-th partial correlator is adapted to obtain a calculation result prn _ acc _ pair _ j based on the following formula:

where sample _ i is a sampling signal corresponding to the ith sampling signal.

Optionally, the multi-path correlation value calculation module is adapted to trigger an initial calculation of one of the n channels when code _ count + code _ inv _ ovf _ k > -C, and to trigger a subsequent calculation of that channel when code _ count < active _ corr-1 and code _ inv _ ovf _ k >0, where code _ count is a count of code _ nco and C is a period of code _ nco.

Optionally, each of the n channels includes a signal processing module adapted to receive the sampled signal, strip a carrier signal in the sampled signal based on the local carrier signal to obtain a baseband signal.

Optionally, the loop adjusting module is adapted to adjust the nco control word at the chip control module based on the multipath correlation values and adjust frequency offsets of the local carrier signals respectively corresponding to the channels of the multiple channels.

The embodiment of the present invention further provides a GNSS receiver, including a navigation front end and a correlator circuit as described in any of the above, where the navigation front end is adapted to convert a satellite navigation signal received by the navigation front end into a digital signal and sample the digital signal to obtain a sampled signal.

Optionally, the GNSS receiver comprises a capturing module adapted to obtain an initial frequency offset of the local carrier signal, the correlator circuit being adapted to strip the carrier signal in the digital signal based on the local carrier signal with the initial frequency offset for the first time.

The embodiment of the invention also provides a method for receiving signals based on the GNSS receiver, which comprises the following steps: receiving satellite navigation signals and converting the satellite navigation signals into digital signals; generating k sampling signals based on the digital signal, wherein k is an integer greater than 0; acquiring a local code, segmenting the local code based on the fixed slice number, and calculating slice overflow values respectively corresponding to the k sampling signals based on code _ nco and nco control words; updating the number of used slices and code _ nco based on the slice overflow value; calculating k control signals respectively corresponding to the k sampling signals based on the fixed slice number, the used slice number, and the slice overflow value, and calculating a specific enable signal and a bit polarity signal based on any one of the k control signals; each partial correlator in the GNSS receiver receives the enabling signal and the bit polarity signal respectively, so that the corresponding sampling signals are processed in parallel to obtain a calculation result; selecting 1 channel from n channels each time and receiving the calculation result output by partial correlator in the channel; receiving the calculation results output by the channel selection module in each round of calculation in sequence, and accumulating to obtain a multi-path correlation value; and judging whether the multi-path correlation value reaches a peak value, if so, outputting the multi-path correlation value, and if not, performing loop adjustment on the chip control module and each of the plurality of channels until the multi-path correlation value reaches the peak value.

Optionally, the method comprises: and when the sampling signal stored in the tracking FIFO module of the GNSS receiver exceeds a first threshold value, outputting the sampling signal to the n channels from the tracking FIFO module.

Optionally, the method comprises: and when the time for generating the code _ nco reaches a second threshold value, stopping receiving the sampling signals by the n channels and starting calculating the multipath correlation values until the data volume reaches a third threshold value, and finishing one round of calculation.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects.

For example, each channel of the correlator circuit includes m partial correlators, and each partial correlator can process corresponding data in parallel based on the enable signal and the bit polarity signal to further obtain a calculation result, i.e., the correlation calculation resource of each channel is split, which can effectively avoid repeated calculation and greatly reduce the calculation time.

For another example, the enable and bit polarity generation module of the correlator circuit may associate the enable signal and the bit polarity signal with the k sampling signals, respectively, which may adaptively process a variable number of sampling points, so that the correlator circuit has versatility and high efficiency.

For another example, the multi-path correlation value calculation module may accumulate the calculation results of some correlators to obtain multi-path correlation values, that is, may combine the processing results of multiple channels, which may optimize resources, occupy lower hardware resources, and reduce power consumption.

Drawings

FIG. 1 is a block diagram of a correlator circuit for GNSS in accordance with an embodiment of the present invention;

FIG. 2 is a flowchart illustrating a method for receiving signals based on a GNSS receiver according to an embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

The embodiment of the invention discloses a correlator circuit for GNSS.

The GNSS comprises a space section, a ground measurement and control section and a user section. The space segment includes a satellite; the ground measurement and control section comprises a master control station, a monitoring station and the like; the user terminal comprises a GNSS receiver and the like. Wherein the GNSS receiver comprises a correlator circuit.

The correlator circuit may track the received GNSS signal, e.g., strip off the carrier and pseudo-random code, to obtain a data code and maintain absolute synchronization of the data code or tracked signal with the local signal.

The digital front end receives a satellite navigation signal sent by a satellite, converts the satellite navigation signal into a digital signal and samples the digital signal, so that k sampling signals can be generated in a plurality of sampling periods; wherein k is an integer greater than 0.

The sampling period corresponds to the sampling rate; the GNSS navigation systems (e.g., Global Positioning System (GPS), beidou system, Glonass system (Glonass) and Galileo system (Galileo) have different settings, as shown in table 1 below.

TABLE 1

Navigation system	Frequency band	Sampling rate (S/S)
			GPS	L1，L2	8M
GPS	L5	20M
			Glonass	G1，G2	16M
Galileo	E5A，E5B	20M
			Galileo	E1	8M
Beidou system	B1/B1C	8M
			Beidou system	B2/B2A，B3	20M

The output end of the digital front end is connected with the correlator circuit.

As shown in fig. 1, the correlator circuit 100 includes a tracking FIFO block 110, a chip control block 120, an enable and bit polarity generation block 130, a channel block 140 (which includes n channels, each of which includes m partial correlators, n and m being integers greater than 0), a channel selection block 150, a multi-path correlation value calculation block 160, and a loop adjustment block 170.

The tracking FIFO module 110 may receive the sampled signal from the digital front end output of the GNSS receiver. And may output k sampled signals obtained over several sampling periods to the channel module 140.

The chip control module 120 may acquire a local code, which may be generated by a pseudo-random code generator.

The chip control module 120 may divide the local code based on a fixed number of slices (code _ inv). The code _ nco may take the 0 th bit to the d-1 th bit based on the slice register, denoted as code _ nco [ d-1:0], where d is the fixed bit depth of the slice register, which is an integer greater than 1, e.g., 40.

The chip control module 120 may calculate slice overflow values (code _ inv _ ovf _ i) corresponding to the k sampling signals, respectively, based on code _ NCO and NCO control words (e.g., NCO frequency control words, the control steps of which may be expressed as code _ freq [ d-1:0]), wherein the NCO control words may be generated by a Numerically Controlled Oscillator (NCO), wherein i is an integer greater than 0 and less than or equal to k.

The chip control module 120 may also update the number of used slices and code _ nco based on the slice overflow value; the number of slices used in the slice register may be represented as prn _ cnt, which is an integer not less than 0, for example, 0 represents that 1 slice is used, and 15 represents that 16 slices are used.

In a specific implementation, the chip control module 120 may include an nco control word adjustment unit 121 and a code generation unit 122.

The nco control word adjusting unit 121 can receive the local code generated by the pseudo random code generator and divide the local code. When slicing, the local code may be segmented based on a fixed number of slices, one slice corresponding to 1bit of the local code. The fixed number of slices may be denoted code _ inv, which has a value of, for example, 2, 4, 8, 16, etc.

The smaller the number of fixed slices, the higher the granularity of the segmentation and the higher the accuracy of the subsequent correlation calculations. The fixed slice number may be kept constant in one or more rounds of the calculation of the multi-path correlation value calculation module 160, or may be changed in different rounds of the calculation. In one round of operation, different channels in a channel module may have the same or different fixed slice numbers.

The nco control word adjusting unit 121 can receive the adjusting signal output by the loop adjusting module 170, so as to adjust the nco control word.

The nco control word adjustment unit 121 may also calculate slice overflow values (code _ inv _ ovf _ i) corresponding to the k sampling signals, respectively, based on the code _ nco and the nco control word; this calculation may be performed based on the code _ nco and nco control words received within a unit clock tick.

At the current clock beat, a specific code _ nco (i.e., code _ nco _ i [ d + a-1:0]) can be obtained based on the following formula:

code_nco_i[d+a-1:0]＝

code_nco[d-1:0]+code_freq[d-1:0]*b (1)

wherein i is an integer greater than 0 and less than or equal to k, and i can range from 1 to k; a and b are integers which are more than 0 and less than or equal to k, a can be a positive integer from 1 to k or less than k, and b can be a positive integer from 1 to k or less than k; taking bits from 0 th bit to d + a-1 th bit in code _ nco [ d + a-1:0 ]; code _ freq [ d-1:0] is the step controlled by the nco control word.

At the next clock beat, code _ nco [ d-1:0] may be updated to code _ nco _ k [ d-1:0 ].

The slice overflow value includes an initial slice overflow value code _ inv _ ovf _0, which may be made equal to 0.

The slice overflow value code _ inv _ ovf _ i may be obtained based on the following formula:

code_inv_ovf_i＝code_nco_i[d+a-1:d] (2)

wherein i is an integer which is greater than 0 and less than or equal to k, i can be from 1 to k, and d bits to d + a-1 bits in code _ nco are taken from code _ nco [ d + a-1: d ].

When a is 1, code _ inv _ ovf _ i is code _ nco _ i [ d ].

The slice overflow value code _ inv _ ovf _ i corresponds to the ith sampling point.

In one embodiment, d is 40, k is 8, and at the current clock beat, the code _ nco _ i may be obtained based on the following formula:

code_nco_1[40:0]＝code_nco[39:0]+code_freq[39:0]，

code_nco_2[41:0]＝code_nco[39:0]+code_freq[39:0]*2，

code_nco_3[41:0]＝code_nco[39:0]+code_freq[39:0]*3，

code_nco_4[42:0]＝code_nco[39:0]+code_freq[39:0]*4，

code_nco_5[42:0]＝code_nco[39:0]+code_freq[39:0]*5，

code_nco_6[42:0]＝code_nco[39:0]+code_freq[39:0]*6，

code_nco_7[42:0]＝code_nco[39:0]+code_freq[39:0]*7，

code_nco_8[43:0]＝code_nco[39:0]+code_freq[39:0]*8。

at the next clock beat, code _ nco [39:0] may be updated to code _ nco _8[39:0 ].

In another embodiment, d is 40, k is 8, and at the current clock beat, the code _ nco _ i may be obtained based on the following formula:

code_nco_1[40:0]＝code_nco[39:0]+code_freq[39:0]，

code_nco_2[41:0]＝code_nco[39:0]+code_freq[39:0]*2，

code_nco_3[41:0]＝code_nco[39:0]+code_freq[39:0]*3，

code_nco_4[42:0]＝code_nco[39:0]+code_freq[39:0]*3，

code_nco_5[42:0]＝code_nco[39:0]+code_freq[39:0]*3，

code_nco_6[42:0]＝code_nco[39:0]+code_freq[39:0]*3，

code_nco_7[42:0]＝code_nco[39:0]+code_freq[39:0]*3，

code_nco_8[43:0]＝code_nco[39:0]+code_freq[39:0]*3。

The initial slice overflow value code _ inv _ ovf _0 is equal to 0.

The slice overflow value may be obtained based on the following equation:

code_inv_ovf_1＝code_nco_1[40]，

code_inv_ovf_2＝code_nco_2[41:40]，

code_inv_ovf_3＝code_nco_3[41:40]，

code_inv_ovf_4＝code_nco_4[42:40]，

code_inv_ovf_5＝code_nco_5[42:40]，

code_inv_ovf_6＝code_nco_6[42:40]，

code_inv_ovf_7＝code_nco_7[42:40]，

code_inv_ovf_8＝code_nco_8[43:40]。

the code generation unit 122 receives the slice overflow value output from the nco control word adjustment unit 121, which shifts (shifts left or right) the code _ nco held in the slice register, thereby updating the number of used slices (the initial value of which is 0) and the code _ nco held in the slice register; wherein an initial value of the number of used slices may be set to 0.

The slice register may be a shift feedback register, a read only memory, etc.

For example, k is 8, d is 40, and code _ inv is 8.

Before updating, the slice register stores 40-bit data "0000 _0000_1111_1111_0000_0000_1111_1111_1111_ 1111", prn _ cnt is 7, and code _ inv _ ovf _8 is 5.

When the code generation unit 122 receives the slice overflow value code _ inv _ ovf _8, the data held in the slice register is shifted to the left by 5 bits, and the 40-bit data is updated to "000 _1111_0000_0000_1111_1111_1111_ 1", and prn _ cnt is 4.

The enable and bit polarity generation block 130 may receive the fixed slice number, the used slice number, and the slice overflow value output by the chip control block 120, and calculate k control signals corresponding to the k sampling signals, respectively, based on the three.

In some embodiments, m is equal to 31.

Specifically, the enable and bit polarity generation module 130 may set the ith control signal prn _ acc _ i based on the following formula:

active_acc_max＝active_corr+code_inv-1 (3)

when prn _ acc _ i is greater than or equal to active _ acc _ max, then:

prn_acc_i＝0 (4)

active _ acc _ max is the maximum number of relevant paths, active _ corr is the number of relevant paths preset in the multi-path correlation value calculation module 160, and i is an integer greater than 0 and less than or equal to k.

The enable and bit polarity generation module 130 may obtain the y-th control signal prn _ acc _ i based on the following formula:

prn_acc_i＝prn_acc_0+code_inv*i (5)

prn_acc_0＝(prn_cnt_i+code_inv_ovf_i)mod code_inv (6)

where prn _ acc _0 is an initial control signal, code _ inv is a fixed number of slices, prn _ cnt _ i is a number of used slices corresponding to the ith sampling signal, code _ inv _ ovf _ i is a slice overflow value corresponding to the ith sampling signal, i is an integer greater than 0 and less than or equal to k, and mod represents a modulus value.

The ith control signal prn _ acc _ i corresponds to the ith sampling signal and is used for controlling the input of the ith sampling signal to a partial correlator in the channel module, for example, controlling the enabling and bit polarity of the partial correlator.

The enable and bit polarity generation module 130 may calculate an enable signal and a bit polarity signal applied to one partial correlator based on any one of the k control signals.

Each enable signal may or may not enable a respective partial correlator in the n channels to receive or not receive a respective sampled signal.

Each set of bit polarity signals may contribute to the polarity of the sampled signal output by a corresponding partial correlator in the n channels.

Specifically, the enable and bit polarity generation module 130 may obtain the enable signal prn _ acc _ j _ en _ sap _ i of the jth partial correlator in the m partial correlators with respect to the ith sampling signal based on the following formula:

prn_acc_j_en_sap_i＝prn_acc_en_group_i[j] (7)

prn_acc_en_group_k[m-1:0]

＝(1<<prn_acc_0)|(1<<prn_acc_1)|……|(1<<prn_acc_k) (8)

where j is an integer greater than 0 and less than or equal to m, prn _ acc _ en _ group _ k [ m-1:0] is obtained by shifting bits corresponding to the control signals to the left based on 1, respectively, and then performing bit-wise or operation in sequence (i.e., 1 is shifted to the left by bits corresponding to prn _ acc _0, prn _ acc _1, … …, prn _ acc _ i, … … prn _ acc _ k, respectively, and then performing bit-wise or operation in sequence to obtain, "|" indicates that bit-wise or operation is performed), and prn _ acc _ en _ group _ i [ j ] is an enable signal of the ith sampling signal at the jth partial correlator, and is obtained based on prn _ acc _ en _ group _ k [ m-1:0 ].

The jth partial correlator selects the ith sample signal (i.e., enables the ith sample signal) when the enable signal is one of 0 and 1 and does not select the ith sample signal (i.e., does not enable the ith sample signal) when the enable signal is the other of 0 and 1.

The enable and bit polarity generation module 130 may obtain prn _ i _ acc _ bit _ ij based on the following formula:

prn_i_acc_bit_ij＝prn_i_mask_i (9)

prn_i_mask_i＝

((1<<(prn_acc_i+code_inv_ovf_k-code_inv_ovf_i))&prn_reg) (10)

the method comprises the following steps that a prn _ i _ acc _ bit _ ij is an intermediate parameter of a jth partial correlator about an ith sampling signal, a prn _ i _ mask _ i is a mask of the ith sampling signal, a code _ inv _ ovf _ k is a slice overflow value corresponding to the kth sampling signal, and a prn _ reg is a code _ nco stored in a slice register; "1 < < (prn _ acc _ i + code _ inv _ ovf _ i-code _ inv _ ovf _ i)" means that 1 is moved to the left by (prn _ acc _ i + code _ inv _ ovf _ k-code _ inv _ ovf _ i) "bits and then bitwise and-operated with prn _ reg, and" & "means bitwise and-operated.

Prn _ i _ acc _ bit _0j, prn _ i _ acc _ bit _1j through prn _ i _ acc _ bit _ kj can be obtained based on equations (9) and (10), and these are or-ed to obtain a selection signal prn _ i _ mask _ bit _ sel _ j of the j-th partial correlator with respect to the i-th sample signal.

The enabling and bit polarity generating module 130 may obtain the bit polarity signal prn _ mask _ pair _ j _ sap _ i of the jth partial correlator with respect to the ith sampling signal (i.e., the polarity applied to the ith sampling signal at the jth partial correlator) based on the following formula:

prn_mask_pair_j_sap_i＝prn_i_mask_bit_sel_j (11)

channel module 140 includes n channels, each of which includes m partial correlators, e.g., channel 1 includes partial correlators 1(0), 1(1), … …, 1(m-1), channel 2 includes partial correlators 2(0), 2(1), … …, 2(m-1), and channel n includes partial correlators n (0), n (1), … …, n (m-1).

Each partial correlator in the n channels can receive k sampling signals, and k enabling signals and k bit polarity signals respectively corresponding to the k sampling signals, so as to process corresponding data in parallel to obtain a calculation result.

For example, the partial correlators 1(0), 1(1), … …, 1(m-1) in channel 1 may receive a first set of enable signals EN1(0), EN1(1), … …, EN1(m-1), respectively, the partial correlators 2(0), 2(1), … …, 2(m-1) in channel 2 may receive a second set of enable signals EN2(0), EN2(1), … …, EN2(m-1), respectively, and the partial correlators n (0), n (1), … …, n (m-1) in channel n may receive an nth set of enable signals EN (0), EN (1), … …, EN (m-1), respectively.

For another example, the partial correlators 1(0), 1(1), … …, and 1(m-1) in channel 1 may receive the first set of bit polarity signals PO1(0), PO1(1), … …, PO1(m-1), respectively, the partial correlators 2(0), 2(1), … …, and 2(m-1) in channel 2 may receive the second set of bit polarity signals PO2(0), PO2(1), … …, and PO2(m-1), respectively, and the partial correlators n (0), n (1), … …, and n (m-1) in channel n may receive the nth set of bit polarity signals POn (0), POn (1), … …, and POn (m-1), respectively.

Each partial correlator of the channel module 140 may operate based on the enable signal and the bit polarity signal of a certain sampling signal, and may process a plurality of sampling signals in parallel.

The j-th partial correlator of the m partial correlators may obtain a calculation result prn _ acc _ pair _ j based on the following formula:

where sample _ i is a sampling signal corresponding to the ith sampling signal.

Equation (12) is an iterative operation based on the calculation result prn _ acc _ pair _ j; when the sampling signal of the jth partial correlator is in an enabled state (i.e., the jth partial correlator can receive the sampling signal), the calculation result prn _ acc _ pair _ j can be updated at the turning edge of each clock beat.

In the embodiment of the present invention, i may sequentially take each integer from 1 to k, and j may sequentially take each integer from 1 to m, thereby obtaining each sampling signal, code _ nco, a slice overflow value, the number of used slices, a control signal, an enable signal, a bit polarity signal, a selection signal, a calculation result, and the like.

The channel selection module 150 selects 1 channel at a time from the n channels to receive the calculation result output from the partial correlator in the channel, and outputs the calculation result to the multi-path correlation value calculation module 160.

The multi-path correlation value calculating module 160 receives the calculation results output by the channel selection module in turn in each calculation, and accumulates the calculation results to obtain multi-path correlation values.

The counting module may count cyclically based on the period of code _ nco and transmit a counting signal, the n channels may count synchronously or independently, the counting module may be included in the channel module 140, may be included in the multi-channel correlation value calculating module 160, or may be an independent module.

The operation of the multi-way correlation value calculation module 160 may be triggered based on the count signal; the n channels may be stopped from receiving the sampled signal while the multi-path correlation value calculation module 160 is operating.

Specifically, the count value code _ count of code _ nco may be obtained based on the following formula:

code_count＝(code_count+code_inv_ovf_k)mod C (13)

where C is the period of code _ nco.

The multi-path correlation value calculation module 160 may trigger the initial calculation of one of the n channels when the following conditions are met:

code_count+code_inv_ovf_i>＝C (14)

wherein code _ count, code _ inv _ ovf _ i, and C are parameters associated with the channel, respectively.

And, the subsequent calculation of the channel may be triggered when the following two conditions are met:

code_count<active_corr-1 (15)

code_inv_ovf_k>0 (16)

wherein, active _ corr is the number of related paths preset in the multi-path correlation value calculation module 160, and code _ count and code _ inv _ ovf _ k are parameters related to the path respectively.

When the multi-path correlation value calculation module 160 performs the multi-path calculation, f may be the first value in a round of calculation, g may be the last value in the round of calculation, and dump _ num may be the number of multi-paths in the round of calculation.

The provisional count value code _ count _ tmp may be obtained based on the following equation:

code_count_tmp＝(code_count+code_inv_ovf8)mod C (17)

when the following two conditions are satisfied, let g be 0, h be active _ corr-1, and dump _ num be active _ corr:

code_count_tmp<code_inv_ovf_k (18)

code_count_tmp>＝active_corr-1 (19)

when the following two conditions are satisfied, let g be 0, h be code _ count _ tmp, dump _ num be code _ count _ tmp + 1:

code_count_tmp<code_inv_ovf_k (20)

code_count_tmp<active_corr-1 (21)

when the following two conditions are satisfied, let g ═ code _ count +1, h ═ active _ corr-1, dump _ num ═ active _ corr-1-code _ count:

code_count_tmp>＝code_inv_ovf_k (22)

code_count_tmp>＝active_corr-1 (23)

when the following two conditions are satisfied, let g be code _ count +1, h be code _ count _ tmp, dump _ num be code _ count _ tmp-1-code _ count:

code_count_tmp>＝code_inv_ovf_k (24)

code_count_tmp<active_corr-1 (25)

the values of g, h, and dump _ num can be determined by the conditions (18) to (25) as above.

When a channel is selected by the channel selection module 150 and outputs the calculation results of some correlators in the channel, the multi-path correlation value calculation module 160 receives the calculation results, obtains the values of g, h, and dump _ num of the channel at the clock beat, and accumulates the calculation results to obtain the multi-path correlation values.

The following algorithm illustrates the iterative computation of the correlation value for the g + h +1 way.

Wherein corr _ p is a multi-path correlation value, and prn _ acc _ pair (p + q) (which can also be expressed as prn _ acc _ pair _ p + q) is a calculation result; with regard to the "calculation result", see the above description about the formula (12).

The loop adjusting module 170 may receive the multi-path correlation value output by the multi-path correlation value calculating module 160, determine whether the multi-path correlation value reaches a peak value, if so, output the multi-path correlation value, and the correlator circuit 100 completes signal tracking; if not, the chip control module 120 and the m channels are respectively subjected to loop adjustment based on the multi-path correlation value until the multi-path correlation value reaches a peak value. When the multipath correlation value reaches the peak value, the sampling signal keeps absolute synchronization with the code _ nco.

For example, when the multi-path correlation value does not reach the peak value, the loop adjustment module 170 sends an adjustment signal to the chip control module 120 and the m channels, so that the chip control module 120, the enable and bit polarity generation module 130, the channel module 140, the channel selection module 150, and the multi-path correlation value calculation module 160 start a new round of calculation, and output the multi-path correlation value to the loop adjustment module 170 again for determination after the probabilistic calculation is completed.

In a specific implementation, a correlation value threshold may be set, and when the multi-path correlation value is greater than or equal to the correlation value threshold, it is determined that the multi-path correlation value reaches a peak value, otherwise it does not reach the peak value.

In some embodiments, each of the n channels includes a signal processing module, such as D1, … …, Dn shown in fig. 1, that receives the sampled signal and strips a carrier signal in the sampled signal based on a local carrier signal to obtain a baseband signal.

In a specific implementation, the loop adjustment module may adjust the nco control word at the chip control module based on the multi-path correlation value (see fig. 1), and adjust the frequency offsets of the local carrier signals corresponding to the m channels, respectively (not shown), so as to perform the loop adjustment.

In other embodiments, the correlator circuit includes a control module.

When the sampling signals stored in the tracking FIFO module exceed a first threshold value, the control module outputs the sampling signals to the n channels; the channel selection module can also output the calculation result of the partial correlator to the multipath correlation value calculation module.

For example, the first threshold is 2ms (i.e., tracking the amount of data stored by the FIFO module in 2 ms).

When the time for generating the code _ nco reaches a second threshold value, the control module enables the n channels to stop receiving the sampling signals and triggers the multipath correlation value calculation module to calculate the multipath correlation value, and one round of calculation is finished until the data volume reaches a third threshold value.

After finishing one round of calculation, the n channels re-receive the sampling signals, clear and re-time the time for generating code _ nco.

For example, the second threshold is 1ms, 4ms, 10ms, or 20 ms; the second threshold may also be an integer multiple of the code _ nco period.

For example, the third threshold is 1 ms.

The embodiment of the invention also discloses a GNSS receiver.

In particular implementations, the GNSS receiver may be a GNSS-based user navigation device or a user device incorporating GNSS navigation functionality.

The GNSS receiver may include a navigation front end and a correlator circuit.

The navigation front end is used for receiving satellite navigation signals sent by satellites and converting the satellite navigation signals into digital signals; the navigation front end may also sample the digital signal to obtain a sampled signal.

The correlator circuit can receive the sampling signal sent by the navigation front end and carry out processing and calculation; for the principle, structure, function, etc. of the correlator circuit, reference may be made to the above description, and details are not repeated here.

In some embodiments, the GNSS receiver further comprises a capture module that can obtain an initial frequency offset of the local carrier signal, and the correlator circuit can strip the carrier signal in the digital signal based on the local carrier signal with the initial frequency offset for the first time.

The embodiment of the invention also discloses a method for receiving the signal by the GNSS receiver.

As shown in FIG. 2, a method 200 for a GNSS receiver to receive signals includes the following steps.

In the execution of step 210, satellite navigation signals are received and converted to digital signals.

In the execution of step 220, k sampling signals are generated based on the digital signal, where k is an integer greater than 0.

In the execution of step 230, a local code is acquired, the local code is divided based on a fixed slice number, and slice overflow values respectively corresponding to the k sampling signals are calculated based on code _ nco and nco control words.

In the execution of step 240, the number of slices used and code _ nco are updated based on the slice overflow value.

In the execution of step 250, k control signals corresponding to the k sampling signals, respectively, are calculated based on the fixed slice number, the used slice number, and the slice overflow value, and a specific enable signal and a bit polarity signal are calculated based on any one of the k control signals.

In the execution of step 260, each partial correlator in the GNSS receiver receives the enable signal and the bit polarity signal, respectively, so as to process the corresponding data in parallel to obtain the calculation result.

In the execution of step 270, the calculation results output by the partial correlators in the n channels are received by selecting 1 channel from the n channels each time.

In step 280, the calculation results output by the channel selection module are received in turn in each round of calculation, and are accumulated to obtain a multi-path correlation value.

In the execution of step 290, it is determined whether the multi-path correlation value reaches a peak value, if so, the multi-path correlation value is output, and if not, the loop adjustment is performed on the chip control module and each of the plurality of channels until the multi-path correlation value reaches the peak value.

In a specific implementation, the method 200 further comprises: when the sampling signal stored in the tracking FIFO module of the GNSS receiver exceeds a first threshold value, the sampling signal is output to the n channels from the tracking FIFO module.

In a specific implementation, the method 200 further comprises: and when the time for generating the code _ nco reaches a second threshold value, stopping receiving the sampling signals by the n channels and starting calculating the multipath correlation values until the data volume reaches a third threshold value, and finishing one round of calculation.

For the steps involved in the method for receiving signals by the GNSS receiver, the principles thereof, and the like, reference may be made to the above description of the correlator circuit and the GNSS receiver, which is not repeated herein.

In an embodiment of the present invention, the Processor may be a Central Processing Unit (CPU), and the Processor may also be other general purpose processors, Digital Signal Processors (DSP), Application Specific Integrated Circuits (ASIC), Field Programmable Gate Arrays (FPGA), other Programmable logic devices, discrete Gate or transistor logic devices, or discrete hardware components. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

In embodiments of the invention, the memory may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash Memory. The volatile Memory may be a Random Access Memory (RAM) which serves as an external cache. By way of example but not limitation, many forms of RAM are available, such as Static random access memory (Static RAM, SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous dynamic random access memory (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct memory bus RAM (DR RAM).

In the embodiment of the present invention, the storage medium includes various media that can store program codes, such as a usb disk, a removable hard disk, a ROM, a RAM, a Non-volatile memory (Non-volatile), a Non-transitory memory (Non-transitory) memory, a magnetic disk, or an optical disk.

With regard to each module/unit included in each apparatus and product described in the above embodiments, it may be a software module/unit, or may also be a hardware module/unit, or may also be a part of a software module/unit and a part of a hardware module/unit. For example, for each apparatus and product applied to or integrated into a chip, each module/unit included in the apparatus and product may all be implemented by hardware such as a circuit, or at least a part of the modules/units may be implemented by a software program running on a processor integrated within the chip, and the remaining (if any) part of the modules/units may be implemented by hardware such as a circuit; for each device or product applied to or integrated with the chip module, each module/unit included in the device or product may be implemented by using hardware such as a circuit, and different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components of the chip module, or at least some of the modules/units may be implemented by using a software program running on a processor integrated within the chip module, and the rest (if any) of the modules/units may be implemented by using hardware such as a circuit; for each device and product applied to or integrated in the terminal, each module/unit included in the device and product may be implemented by hardware such as a circuit, different modules/units may be located in the same component (e.g., a chip, a circuit module, etc.) or different components in the terminal, or at least part of the modules/units may be implemented by a software program running on a processor integrated in the terminal, and the rest (if any) part of the modules/units may be implemented by hardware such as a circuit.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A correlator circuit for a GNSS comprising:

a tracking FIFO module adapted to generate k sampled signals obtained based on sampling digital signals related to satellite navigation signals, wherein k is an integer greater than 0;

a chip control module adapted to acquire a local code, divide the local code based on a fixed number of slices, calculate slice overflow values respectively corresponding to the k sampling signals based on code _ nco and nco control words, and update a used number of slices and the code _ nco based on the slice overflow values;

an enable and bit polarity generation module adapted to receive the fixed slice number, the used slice number, and the slice overflow value, calculate k control signals respectively corresponding to the k sampling signals based on the fixed slice number, the used slice number, and the slice overflow value, and calculate a specific enable signal and a bit polarity signal based on any one of the k control signals;

a channel module comprising n channels, each of the n channels comprising m partial correlators, each of the n channels being adapted to receive the enable signal and the bit polarity signal so as to process respective sampled signals in parallel to obtain a calculation result, wherein n and m are each integers greater than 0;

a channel selection module, which is suitable for selecting 1 channel from n channels at a time and receiving the calculation result output by partial correlator in the channel;

a multipath correlation value calculation module, which is suitable for receiving the calculation result output by the channel selection module in turn in each round of calculation and accumulating to obtain multipath correlation values;

and the loop adjusting module is suitable for receiving the multi-path correlation values and judging whether the multi-path correlation values reach peak values or not, if so, the multi-path correlation values are output, and if not, the loop adjusting module performs loop adjustment on the chip control module and each of the plurality of channels until the multi-path correlation values reach the peak values.

2. The correlator circuit of claim 1, comprising a control module adapted to output the sampled signal to the n channels when the sampled signal stored in the tracking FIFO module exceeds a first threshold, to cause the n channels to stop receiving the sampled signal and to trigger the multi-path correlation value calculation module to calculate the multi-path correlation values when a time to generate the code _ nco reaches a second threshold, and to end a round of calculation thereof until an amount of data reaches a third threshold.

3. The correlator circuit of claim 2 wherein the second threshold is an integer multiple of a code nco period.

4. The correlator circuit of claim 1, wherein the chip control module is adapted to calculate a slice overflow value corresponding to each of the k sampled signals based on:

code_nco_i[d+a-1:0]＝code_nco[d-1:0]+code_freq[d-1:0]*b，

updating code _ nco [ d-1:0] to code _ nco _ k [ d-1:0] in the next clock beat;

the slice overflow value, including an initial slice overflow value, is set to 0,

code_inv_ovf_i＝code_nco_i[d+a-1:d]，

the code _ nco _ i [ d + a-1:0] takes the bits from the 0 th bit to the d + a-1 th bit in the code _ nco, the code _ nco _ i [ d + a-1: d ] takes the bits from the d th bit to the d + a-1 th bit in the code _ nco, i is an integer which is more than 0 and less than or equal to k, a and b are integers which are more than 0 and less than or equal to k, d is a fixed bit depth which is an integer which is more than 1, and the code _ freq [ d-1:0] is the step controlled by the nco control word.

5. The correlator circuit of claim 4, wherein the enable and bit polarity generation module is adapted to set the ith control signal prn _ acc _ i based on the following equation:

active_acc_max＝active_corr+code_inv-1，

when prn _ acc _ i is greater than or equal to active _ acc _ max, making prn _ acc _ i equal to 0,

active _ acc _ max is the maximum number of relevant paths, active _ corr is the number of relevant paths preset in the multi-path relevant value calculation module, and code _ inv is the fixed slice number.

6. The correlator circuit of claim 5, wherein the enable and bit polarity generation module is adapted to obtain the ith control signal prn _ acc _ i based on the following equation:

prn_acc_i＝prn_acc_0+code_inv*i，

prn_acc_0＝(prn_cnt_i+code_inv_ovf_i)mod code_inv；

7. The correlator circuit of claim 6 wherein the enable and bit polarity generation module is adapted to obtain an enable signal prn _ acc _ j _ en _ sap _ i of a jth partial correlator of the m partial correlators with respect to the ith sample signal based on the following formula:

prn_acc_j_en_sap_i＝prn_acc_en_group_i[j]，

prn_acc_en_group_k[m-1:0]＝

(1<<prn_acc_0)|(1<<prn_acc_1)|……|(1<<prn_acc_k)，

wherein j is an integer greater than 0 and less than or equal to m, prn _ acc _ en _ group _ k [ m-1:0] is obtained by shifting bits corresponding to the control signals to the left based on 1 and then performing bit-wise OR operation in sequence, and prn _ acc _ en _ group _ i [ j ] is an enable signal of the ith sampling signal at the jth partial correlator and is obtained based on prn _ acc _ en _ group _ k [ m-1:0 ].

8. The correlator circuit of claim 7 wherein the enable and bit polarity generation module is adapted to obtain a bit polarity signal prn _ mask _ pair _ j _ sap _ i of a jth partial correlator of the m partial correlators with respect to the ith sample signal based on:

the prn _ i _ acc _ bit _ ij is obtained based on the following formula:

prn_i_acc_bit_ij＝prn_i_mask_i，

prn_i_mask_i＝((1<<(prn_acc_i+code_inv_ovf_k-code_inv_ovf_i))&prn_reg)，

the prn _ i _ acc _ bit _ ij is an intermediate parameter of the jth partial correlator about the ith sampling signal, prn _ i _ mask _ i is a mask of the ith sampling signal, code _ inv _ ovf _ k is a slice overflow value corresponding to the kth sampling signal, and prn _ reg is a code _ nco stored in a slice register;

performing an or operation on prn _ i _ acc _ bit _0j, prn _ i _ acc _ bit _1j, and prn _ i _ acc _ bit _ kj to obtain a selection signal prn _ i _ mask _ bit _ sel _ j of the jth partial correlator relative to the ith sampling signal;

prn_mask_pair_j_sap_i＝prn_i_mask_bit_sel_j。

9. the correlator circuit of claim 8, wherein the j-th partial correlator is adapted to obtain the calculation result prn _ acc _ pair _ j based on the following formula:

wherein sample _ i is a sampling signal corresponding to the ith sampling signal.

10. The correlator circuit of claim 9 wherein the multi-way correlation value computation module is adapted to trigger an initial computation of one of the n channels at code _ count + code _ inv _ ovf _ k > C, and to trigger subsequent computations for that channel at code _ count < active _ corr-1 and code _ inv _ ovf _ k >0, where code _ count is a count of the code _ nco and C is a period of the code _ nco.

11. The correlator circuit of claim 10 wherein each of the n channels includes a signal processing module adapted to receive the sampled signal and strip a carrier signal of the sampled signal based on a local carrier signal to obtain a baseband signal.

12. The correlator circuit of claim 11, wherein the loop adjustment module is adapted to adjust the nco control word at the chip control module and to adjust the frequency offsets of the local carrier signals corresponding to respective ones of the plurality of channels based on the multi-path correlation values.

13. A GNSS receiver comprising a correlator circuit according to any one of claims 1 to 12 and a navigation front end, wherein the navigation front end is adapted to convert satellite navigation signals it receives into digital signals and to sample the digital signals to obtain sampled signals.

14. The GNSS receiver of claim 13, characterized by comprising a capture module adapted to obtain an initial frequency offset of a local carrier signal, the correlator circuit being adapted to strip the carrier signal in the digital signal based on the local carrier signal with the initial frequency offset for the first time.

15. A method for receiving signals by a GNSS receiver according to claim 13, comprising:

receiving satellite navigation signals and converting the satellite navigation signals into digital signals;

generating k sampling signals based on the digital signal, wherein k is an integer greater than 0;

acquiring a local code, dividing the local code based on the number of fixed slices, and calculating slice overflow values respectively corresponding to the k sampling signals based on code _ nco and nco control words;

updating the used number of slices and the code _ nco based on the slice overflow value;

calculating k control signals corresponding to the k sampling signals, respectively, based on the fixed slice number, the used slice number, and the slice overflow value, and calculating a specific enable signal and a bit polarity signal based on any one of the k control signals;

each partial correlator in the GNSS receiver receives the enabling signal and the bit polarity signal respectively, so that corresponding sampling signals are processed in parallel to obtain a calculation result;

selecting 1 channel from n channels each time and receiving the calculation result output by partial correlator in the channel;

receiving the calculation results output by the channel selection module in each round of calculation in sequence, and accumulating to obtain a plurality of paths of correlation values;

and judging whether the multi-path correlation value reaches a peak value, if so, outputting the multi-path correlation value, and if not, performing loop adjustment on the chip control module and each of the plurality of channels until the multi-path correlation value reaches the peak value.

16. The method of claim 15, comprising: and when the sampling signal stored in a tracking FIFO module of the GNSS receiver exceeds a first threshold value, outputting the sampling signal to the n channels from the tracking FIFO module.

17. The method of claim 15, comprising: and when the time for generating the code _ nco reaches a second threshold value, stopping receiving the sampling signals by the n channels and starting calculating the multi-path correlation values until the data volume reaches a third threshold value, and finishing a round of calculation.