CN113451206B - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
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- CN113451206B CN113451206B CN202110620581.9A CN202110620581A CN113451206B CN 113451206 B CN113451206 B CN 113451206B CN 202110620581 A CN202110620581 A CN 202110620581A CN 113451206 B CN113451206 B CN 113451206B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/1042—Formation and after-treatment of dielectrics the dielectric comprising air gaps
Abstract
The embodiment of the invention discloses a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure comprises the following steps: providing a plurality of metal strips, wherein grooves are formed among the plurality of metal strips; the width of the groove is smaller than a preset value; forming a first dielectric layer filling the groove; forming a second dielectric layer covering the plurality of metal strips and the first dielectric layer; and heating the plurality of metal strips covered with the second dielectric layer and the first dielectric layer to remove the first dielectric layer, so that the grooves are filled with air.
Description
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to a semiconductor structure and a method of fabricating the same.
Background
As semiconductor device feature sizes (Critical Dimension, CD) become smaller, the distance between adjacent metal structures becomes smaller, resulting in larger parasitic capacitances between adjacent metal structures that affect not only the operating speed of the semiconductor device but also the reliability of the semiconductor device.
In the related art, low-k dielectric materials are used to replace high-k dielectric materials to reduce parasitic capacitance generated between adjacent metal structures, and porous materials with poor thermodynamic stability are often used as low-k dielectric materials, so that the reliability of semiconductor devices using the materials is poor.
Disclosure of Invention
In order to solve the above problems, embodiments of the present invention provide a semiconductor structure and a method for manufacturing the same.
The embodiment of the invention provides a manufacturing method of a semiconductor structure, which comprises the following steps:
providing a plurality of metal strips, wherein grooves are formed among the plurality of metal strips; the width of the groove is smaller than a preset value;
forming a first dielectric layer filling the groove;
forming a second dielectric layer covering the plurality of metal strips and the first dielectric layer;
and heating the plurality of metal strips covered with the second dielectric layer and the first dielectric layer to remove the first dielectric layer, so that the grooves are filled with air.
In the above scheme, the material of the second dielectric layer includes the material of the first dielectric layer; wherein the boiling point of the material of the first dielectric layer is smaller than the boiling point of the material of the second dielectric layer;
the heating the plurality of metal strips covered with the second dielectric layer and the first dielectric layer to remove the first dielectric layer includes:
heating the plurality of metal strips covered with the second dielectric layer and the first dielectric layer to evaporate the material of the first dielectric layer contained in the second dielectric layer to form a gap;
during heating, the material of the first dielectric layer is evaporated and leaves the trench through the void to effect removal of the first dielectric layer.
In the above scheme, the material of the first dielectric layer includes a glue-reducing coating RRC dielectric;
the forming a first dielectric layer filling the trench includes:
and forming a first dielectric layer filling the groove through an RRC process.
In the above aspect, the RRC medium includes at least one of propylene glycol methyl ether acetate or propylene glycol monomethyl ether.
In the above scheme, the material of the second dielectric layer includes an RRC dielectric and a spin-on SOD dielectric;
the forming a second dielectric layer covering the plurality of metal strips and the first dielectric layer includes:
and forming a second dielectric layer covering the plurality of metal strips and the first dielectric layer through an SOD process.
In the above scheme, the SOD medium comprises carbon doped silicon oxide.
In the above scheme, the method further comprises:
and after the plurality of metal strips covered with the second dielectric layer and the first dielectric layer are heated, flattening the second dielectric layer so as to thin the second dielectric layer.
In the above scheme, a covering layer is formed on the periphery of the metal strip.
In the above scheme, the semiconductor structure is used for forming the metal interconnection layer of the memory.
Another embodiment of the present invention provides a semiconductor structure comprising:
a plurality of metal strips; grooves are formed among the metal strips, the width of each groove is smaller than a preset value, and air is filled in each groove;
a second dielectric layer on the plurality of metal strips; the semiconductor structure is formed by the manufacturing method provided by the embodiment of the invention.
In the above scheme, the material of the second dielectric layer includes carbon doped silicon oxide.
The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof, wherein the manufacturing of the semiconductor structure comprises the following steps: providing a plurality of metal strips, wherein grooves are formed among the plurality of metal strips; the width of the groove is smaller than a preset value; forming a first dielectric layer filling the groove; forming a second dielectric layer covering the plurality of metal strips and the first dielectric layer; and heating the plurality of metal strips covered with the second dielectric layer and the first dielectric layer to remove the first dielectric layer, so that the grooves are filled with air. The manufacturing method of the semiconductor structure can effectively prepare the air gap, namely, the first dielectric layer filled in the groove between the plurality of metal strips is removed in a heating mode, so that the space originally occupied by the first dielectric layer is replaced by air. It will be appreciated that air has a dielectric constant close to 1, and thus, can greatly reduce the parasitic Capacitance between metals in a semiconductor structure, which has the effect of reducing Resistance-Capacitance (RC) delay. Meanwhile, the semiconductor structure with the air gap can effectively improve the leakage current problem, so that the device performance is improved.
Drawings
Fig. 1 is a schematic implementation flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention;
fig. 2a to 2e are schematic diagrams illustrating implementation procedures of a semiconductor structure manufacturing method according to an embodiment of the present invention.
Detailed Description
In order to make the technical scheme and advantages of the embodiments of the present invention more clear, the following describes the specific technical scheme of the present invention in further detail with reference to the accompanying drawings in the embodiments of the present invention. The following examples are illustrative of the invention and are not intended to limit the scope of the invention.
The invention is more particularly described by way of example in the following paragraphs with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
In order to mitigate the effect of parasitic capacitance caused by the decrease in the distance between metal structures in semiconductor structures, it is a related art practice to replace high-k dielectric materials such as silicon oxide with low-k dielectric materials to reduce the capacitance between adjacent metal layers/structures when forming inter-layer dielectric layers and/or inter-metal dielectric layers. However, as the feature size of the semiconductor device becomes smaller, the problem of parasitic capacitance becomes more serious, and the low-k dielectric layer in the related art mostly adopts a porous material to reduce the k value, but the thermodynamic stability of the porous material is poor, so that the parasitic capacitance cannot be effectively reduced, which is disadvantageous in reducing RC delay, for example, the reliability of the semiconductor device such as a three-dimensional NAND flash (3D NAND flash) adopting such a low-k dielectric structure is poor. In addition, as the minimum distance and k value of the metal wiring layer are reduced, problems such as leakage current are more serious.
Based on the above, the method for manufacturing a semiconductor structure provided in the embodiments of the present invention can effectively prepare the air gap, that is, remove the first dielectric layer filled in the trench between the plurality of metal strips by heating, so that the space originally occupied by the first dielectric layer is replaced by air. It is understood that air has a dielectric constant close to 1, and thus, parasitic capacitance between metals in the semiconductor structure can be greatly reduced, which has the effect of reducing RC delay. Meanwhile, the semiconductor structure with the air gap can effectively improve the leakage current problem, so that the device performance is improved.
An embodiment of the present invention provides a method for manufacturing a semiconductor structure, and fig. 1 is a schematic implementation flow chart of the method for manufacturing a semiconductor structure according to the embodiment of the present invention. As shown in fig. 1, the method comprises the steps of:
step 101: providing a plurality of metal strips, wherein grooves are formed among the plurality of metal strips; the width of the groove is smaller than a preset value;
step 102: forming a first dielectric layer filling the groove;
step 103: forming a second dielectric layer covering the plurality of metal strips and the first dielectric layer;
step 104: and heating the plurality of metal strips covered with the second dielectric layer and the first dielectric layer to remove the first dielectric layer, so that the grooves are filled with air.
Here, the semiconductor structure is at least a portion that will be used in subsequent processes to form the final device structure.
It should be noted that the method for manufacturing a semiconductor structure according to the embodiments of the present invention is particularly advantageous in manufacturing a semiconductor structure having air gaps. In practice, these semiconductor structures may be used to form metal interconnect layers for memories, where the memories may include, for example, NAND-type memories, dynamic random access memories (Dynamic Random Access Memory, DRAM), phase change memories (Phase Change Memory, PCM), and the like. The method for manufacturing the semiconductor structure provided by the embodiment of the invention is not limited to the application, and can be applied to non-storage semiconductors, such as processors, display semiconductors and the like.
Fig. 2a to 2e are schematic diagrams illustrating implementation procedures of a semiconductor structure manufacturing method according to an embodiment of the present invention. Hereinafter, each step in the method according to the embodiment of the present invention will be described in detail with reference to fig. 2a to 2 e.
It should be noted that the number of any components of the semiconductor structure of fig. 2a to 2e is merely exemplary, and is not intended to limit the specific structural features of the semiconductor structure in the embodiments of the present invention. For example, fig. 2 a-2 e exemplarily illustrate the number of metal strips and are not intended to limit the number of semiconductor structures in embodiments of the present invention.
In step 101, a plurality of metal strips 201 are provided, with trenches 210 formed therebetween; the width of the groove 210 is smaller than a predetermined value. In some embodiments, as shown in fig. 2a, the metal strip 201 may be located on the substrate 200.
In practical applications, the substrate is a semiconductor substrate, and may be, for example, a Si substrate, a Ge substrate, a SiGe substrate, a silicon-on-insulator (SOI, silicon On Insulator), or a germanium-on-insulator (GOI, germanium OnInsulator), or the like. In other embodiments, the semiconductor substrate may also be a substrate including other elemental or compound semiconductors, such as GaAs, inP, siC, or the like, a stacked structure, such as Si/SiGe, or the like, and other epitaxial structures, such as Silicon Germanium On Insulator (SGOI), or the like.
It should be noted that the substrate 200 according to the embodiment of the present invention may be a substrate in a broad sense, that is, the substrate may further have other functional layers formed thereon, for example, a multi-layer stack structure, a dielectric layer, etc. formed thereon. At this time, a plurality of metal strips are formed on the functional layer. Here, the material of the metal strip may include a conductive material. In practice, the conductive material may be copper, aluminum, tungsten or other suitable material.
Here, the metal strip 201 is a metal strip having a certain thickness (a dimension of the metal strip in a direction perpendicular to the substrate in fig. 2 a) and a certain width (a dimension of the metal strip in a direction parallel to the substrate in fig. 2 a), and a length of the metal strip (a dimension of the metal strip in another direction parallel to the substrate in fig. 2 a) is not limited.
In practice, the forming of the metal strip 201 may include: a metal layer is first formed on the substrate by chemical vapor deposition (Chemical Vapour Deposition, CVD), physical vapor deposition (Physical Vapour Deposition, PVD), plating, and/or other suitable process. Next, the trenches 210 are formed in the metal layer by a series of steps of masking, photolithography, etching, etc. In some embodiments, the periphery of the metal strip is formed with a cover layer 203. As shown in fig. 2a, a cover layer 203 is formed on the periphery of the plurality of metal strips 201, which functions to form isolation from other layers.
It should be noted that, other insulating layers or dielectric layers 202 may also be disposed on the metal strip 201 above the substrate 200, as shown in fig. 2 a. Other insulating or dielectric layers 202 may also be provided between the metal strip 201 and the substrate 200. In the embodiment of the present invention, other insulating or dielectric layers 202 are illustrated as being disposed over the metal strip 201.
In practical applications, in combination with fig. 2a, the material of the cover layer 203 may be a material that is easy to form a stable bond with metal, such as silicon nitride, or may be an oxide formed by oxidation of the metal itself, for example, the surface of the material of the plurality of metal strips may be oxidized by a high-temperature oxidation method, so as to form the cover layer 203.
In practical applications, in the case that the plurality of metal strips 201 are covered with the cover layer 203, the method for forming the cover layer 203 may further include masking, photolithography, etching, deposition, and the like.
Next, in step 102, a first dielectric layer 204 is formed filling the trench 210.
In practical applications, as shown in fig. 2b, the first dielectric layer 204 is filled in the trench 210 (the trench 210 is shown in fig. 2 a), and the material of the first dielectric layer 204 is typically a low viscosity volatile organic liquid. In practical applications, the material of the first dielectric layer includes an subtractive coating (Resist Reduced Coating, RRC) dielectric. In some specific applications, the RRC medium includes at least one of Propylene Glycol Methyl Ether Acetate (PGMEA) or Propylene Glycol Monomethyl Ether (PGME).
In practice, the material of the first dielectric layer 204 may include at least one of propylene glycol methyl ether acetate or propylene glycol monomethyl ether, and a solution of water. The components of the RRC medium may be formulated as desired by those skilled in the art. For example, the ratio of propylene glycol methyl ether acetate or propylene glycol monomethyl ether to water can be adjusted to form an RRC medium of suitable concentration. The RRC medium itself may be regarded as a solvent.
Accordingly, in some embodiments, the forming a first dielectric layer filling the trench includes:
and forming a first dielectric layer filling the groove through an RRC process.
Here, the RRC process generally refers to a pretreatment process of photoresist coating, which aims to allow the RRC medium to enter a narrow trench and then to perform photoresist coating, so that the photoresist dosage is reduced without causing gaps, and the photoresist can be rapidly and uniformly spread over the entire wafer. It should be noted that the method in the embodiment of the present invention uses the RRC process only to make the RRC medium enter the narrower trench, and does not involve the application of photoresist.
In practical applications, the RRC process may specifically include: by placing the substrate structure with the trenches in a spin-on device, the RRC medium is tiled over the structure and flows into the trenches 210. The RRC medium beyond the top portion of the trench 210 may then be removed by adjusting the spin-on speed. For example, by increasing the spin-coating speed above a preset value, the RRC medium located above the top portion of the trench 210 is forced away by centrifugal force.
It should be noted that, after the RRC process, the first dielectric layer substantially fills the trench 210, and the amount of the first dielectric layer 204 existing on the top surface of the metal strip 201 is very low, which is negligible.
Next, in step 103, a second dielectric layer 205 is formed to cover the plurality of metal strips and the first dielectric layer 204.
In practical application, as shown in fig. 2c, the second dielectric layer 205 is formed on the basis of the first dielectric layer 204. The second dielectric layer 205 covers the resulting structure of step 102. It will be appreciated that the second dielectric layer 205 covers both the first dielectric 204 filling the trench 205 and the top surface of the metal strip 201.
It will be appreciated that in the case where the capping layer 203 is present over the metal strip 201, the second dielectric layer 205 covers both the first dielectric 204 filling the trench 210 and the capping layer 203. In practical applications, the second dielectric layer 205 may be formed by spin coating or deposition. One skilled in the art can select an appropriate method according to the material of the second dielectric layer 205 to be added.
Next, step 104 is performed: the plurality of metal strips 201 covered with the second dielectric layer 205 and the first dielectric layer are heated to remove the first dielectric layer, so that the trenches are filled with air.
In this step, as shown in fig. 2d, in order to fill the air in the trench 210, the first dielectric layer 204 originally filled in the trench 210 needs to be removed, and no other material than air is introduced.
In some embodiments, the material of the second dielectric layer 205 includes the material of the first dielectric layer 204; wherein the boiling point of the material of the first dielectric layer 204 is smaller than the boiling point of the material of the second dielectric layer 205;
the heating the plurality of metal strips covered with the second dielectric layer 205 and the first dielectric layer to remove the first dielectric layer 204 includes:
heating the plurality of metal strips covered with the second dielectric layer 205 and the first dielectric layer 204, so that the material of the first dielectric layer 204 contained in the second dielectric layer 205 is evaporated to form a gap;
during heating, the material of the first dielectric layer 204 is evaporated and leaves the trench through the void to effect removal of the first dielectric layer 204.
In practical applications, the material of the first dielectric layer 204 is evaporated, and the material of the first dielectric layer 204 included in the second dielectric layer 205 has a boiling point higher than that of the material of the first dielectric layer 204, so that the first dielectric layer 204 is completely evaporated by heating, and the process is as follows: while the material of the first dielectric layer 204 included in the second dielectric layer 205 leaves the second dielectric layer as it is heated to evaporate, numerous fine voids are created through which the material of the first dielectric layer 204 is evaporated as the heating proceeds and leaves the trench 210. It is understood that the higher boiling point material in the second dielectric layer 205 is retained. In summary, the first dielectric layer 204 is removed by heating, while the second dielectric layer 205 is at least partially retained.
In this manner, the air fills the trench 210, thereby forming the air space 206.
In some embodiments, the material of the first Dielectric layer includes an RRC medium, the material of the second Dielectric layer includes an RRC medium and a Spin-On Dielectric (SOD) medium, and the RRC medium is evaporated by heating the plurality of metal strips covered with the second Dielectric layer and the first Dielectric layer.
Here, SOD dielectric is a coating substance used in a silicon thin film preparation process, and plays an insulating role between transistors of a semiconductor; and the SOD process is a process for preparing a silicon film by spin-coating an SOD medium for preventing electric leakage. The silicon film preparation process originally uses a CVD process, but with the miniaturization of patterns, the SOD spin coating process which is flat and has no gaps uses the SOD medium to replace the CVD process, and has the effects of improving the productivity and saving the investment cost of equipment.
In some embodiments, the SOD medium comprises carbon doped silicon oxide.
In practice, the carbon-doped silica may be, for example, dimethyl silsesquioxane.
Thus, in practical applications, the material of the second dielectric layer may include dimethyl silsesquioxane and Propylene Glycol Methyl Ether Acetate (PGMEA). In addition, the material of the second dielectric layer may further include dimethyl silsesquioxane and Propylene Glycol Monomethyl Ether (PGME), or the material of the second dielectric layer may further include dimethyl silsesquioxane, PGMEA and PGME. The contents of the components in the material of the second dielectric layer 205 can be determined by those skilled in the art according to the actual circumstances.
The method of forming the second dielectric layer 205 may be spin coating.
It will be appreciated that since the second dielectric layer comprises a SOD dielectric and an RRC dielectric, and the SOD dielectric comprises a carbon doped silicon oxide, the viscosity of the SOD dielectric is greater than the RRC dielectric, and thus the viscosity of the SOD dielectric and RRC dielectric combination is greater than the RRC dielectric alone. A second dielectric layer comprising SOD dielectric and RRC dielectric may overlie the plurality of metal strips and the first dielectric layer. As shown in fig. 2 d.
It should be noted that the heating process in step 104 may be performed in a heating device or in a semiconductor processing machine with a heating function, for example, typically performed in a baking tray. The temperature and time of heating depend on the specific composition of the RRC medium. In practical application, in the case where the RRC medium is PGMEA, the heating temperature is about 100 ℃ to 200 ℃ and the heating time is 10min to 30min.
Furthermore, it is understood that after the first dielectric layer is removed by heating, the RRC dielectric material in the material of the second dielectric layer will also evaporate, leaving only the SOD dielectric material.
Through a series of steps 101-104, a semiconductor structure with air gaps 206 is formed. It will be appreciated that by the steps of the method of an embodiment of the present invention, the first dielectric layer 204 filling the trenches 210 between the plurality of metal strips 201 is removed in a heated manner such that the space originally occupied by the first dielectric layer 204 is replaced by air, while the second dielectric layer 205 is at least partially preserved, thereby forming the air spaces 206. Since the dielectric constant of air is extremely low and is close to 1, parasitic capacitance between metal structures can be reduced compared with a semiconductor structure using a low-k dielectric material, and RC delay can be reduced. Meanwhile, the semiconductor structure with the air gap can effectively reduce the leakage current problem, so that the device performance is improved.
Another method of forming air gaps is provided by embodiments of the present invention, which includes first depositing a sacrificial layer in a trench between metal strips by a method such as CVD or PVD, and then planarizing the top surface of the sacrificial layer to be level with the top surfaces of the plurality of metal strips. Next, a barrier layer, which may be, for example, silicon carbonitride, is formed on top of the plurality of metal strips and the trench filled with the sacrificial layer. And forming an etching hole for removing the sacrificial layer. Finally, an acidic etching solution such as phosphoric acid is added to the etching holes to etch the sacrificial layer to remove the sacrificial layer, thereby forming an air gap at the space originally occupied by the sacrificial layer.
In the wet etching scheme, the silicon carbonitride with relatively poor filling performance is used as the blocking layer, so that unnecessary filling of the air gap after the sacrificial layer is removed can be avoided, and the air gap can be prepared.
It can be appreciated that, compared with the method of removing the sacrificial layer by wet etching to form the air gap, the method of removing the sacrificial layer by heating to form the air gap in the foregoing embodiment of the present invention adopts the RRC process, so that the RRC medium fills the trench instead of the deposition process of the dielectric material. Meanwhile, the first dielectric layer filled in the grooves among the metal strips is removed in a heating mode, the step of forming etching holes is reduced, the step of wet etching post-treatment is saved, and in addition, the problem of accessibility of wet etching solution to the sacrificial layer is avoided in a heating mode. That is, the method of forming the air gap by removing the sacrificial layer by heating can simplify the manufacturing process of the air gap and form a high quality air gap.
In the subsequent process, after step 104, the second dielectric layer may be thinned to meet the requirement of the subsequent process.
Specifically, in some embodiments, after the plurality of metal strips covered with the second dielectric layer 20 and the first dielectric layer are heated to form air gaps, the method further includes performing a planarization process on the second dielectric layer to thin the second dielectric layer.
It will be appreciated that in practical applications, in connection with fig. 2c to 2e, the topography of the second dielectric layer 205 may be affected, for example, by forming an uneven second dielectric layer 205, since the first dielectric layer 204 is separated through the second dielectric layer 205 and then subjected to a heating step to evaporate the first dielectric layer 204 through the second dielectric layer 205. In practice, in order to eliminate such adverse effects, and also in order to perform a subsequent process, a chemical mechanical planarization (Chemical Mechanical Planarization, CMP) step may be performed to thin the second dielectric layer 205 to a predetermined thickness, thereby obtaining the semiconductor structure 20.
Fig. 2e shows a schematic structural diagram of a CMP-processed semiconductor structure of the present invention. The method for manufacturing the semiconductor structure is particularly suitable for the situation that air gaps are adopted to replace low-k dielectric materials. And is more advantageously adapted to form air gaps in trenches of extremely small width. Therefore, the manufacturing method of the semiconductor structure of the invention is applicable to advanced processes of 14nm, 10nm, 7nm, 5nm and the like.
The manufacturing method of the semiconductor structure can effectively prepare the air gap, namely, the first dielectric layer filled in the groove between the metal strips is removed in a heating mode, so that the space originally occupied by the first dielectric layer is replaced by air, and meanwhile, the second dielectric layer is at least partially reserved. By this way of preparing the air space by heating, the filling step of the dielectric material can be reduced without adding additional photolithography, etching and deposition processes to form the air space with a closed volume. The air in the air gap has a dielectric constant close to 1, can greatly reduce the parasitic capacitance between metals in the semiconductor structure, and has the effect of reducing RC delay. Meanwhile, the semiconductor structure with the air gap can effectively reduce the leakage current problem, so that the device performance is improved.
Based on the above manufacturing method, the embodiment of the invention further provides a semiconductor structure, which includes:
a plurality of metal strips; grooves are formed among the metal strips, the width of each groove is smaller than a preset value, and air is filled in each groove;
a second dielectric layer on the plurality of metal strips; the semiconductor structure is formed by the manufacturing method provided by the embodiment of the invention.
In practical application, as shown in fig. 2e, the semiconductor structure 20 of the embodiment of the present invention includes a plurality of metal strips 201, wherein a trench 210 is formed between the plurality of metal strips 201, the width of the trench 210 is smaller than a predetermined value, and the method for forming the trench is described in detail above, which is not repeated herein.
As shown in fig. 2e, the semiconductor structure 20 according to the embodiment of the present invention further includes filling the trench with air to form the air space 206, and the method of filling air may be as described herein, but is not limited thereto, and any suitable method may be used to form the air space 206.
As shown in fig. 2e, the semiconductor structure 20 according to the embodiment of the present invention further includes a second dielectric layer 205 on the plurality of metal strips.
In an embodiment of the present invention, the material of the second dielectric layer includes SOD dielectric, specifically may include carbon doped silicon oxide, and more specifically may be dimethyl silsesquioxane. SOD mediators are described in detail above and are not described in detail herein.
In the semiconductor structure of the embodiment of the invention, the air interval is provided, and the dielectric constant of the air is close to the vacuum dielectric constant (about 1), so that the parasitic capacitance between metals can be greatly reduced, RC delay can be reduced, and meanwhile, the semiconductor structure with the air interval can effectively reduce the leakage current condition, thereby improving the device performance.
It should be noted that: in the description of the present invention, the terms "inner", "outer", "longitudinal", "transverse", "upper", "lower", "top", "bottom", "left", "right", "front", "rear", etc. refer to the orientation or positional relationship based on that shown in the drawings, merely for convenience of describing the present invention and do not require that the present invention must be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
In addition, the embodiments of the present invention may be arbitrarily combined without any collision. The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (9)
1. A method of fabricating a semiconductor structure, comprising:
providing a plurality of metal strips, wherein grooves are formed among the plurality of metal strips; the width of the groove is smaller than a preset value; a covering layer is formed on the periphery of the metal strip;
forming a first dielectric layer filling the groove;
forming a second dielectric layer covering the plurality of metal strips and the first dielectric layer; the material of the second dielectric layer comprises the material of the first dielectric layer; wherein the boiling point of the material of the first dielectric layer is smaller than the boiling point of the material of the second dielectric layer;
heating the plurality of metal strips covered with the second dielectric layer and the first dielectric layer to remove the first dielectric layer, so that the grooves are filled with air, and the method comprises the following steps:
heating the plurality of metal strips covered with the second dielectric layer and the first dielectric layer to evaporate the material of the first dielectric layer contained in the second dielectric layer to form a gap;
during heating, the material of the first dielectric layer is evaporated and leaves the trench through the void to effect removal of the first dielectric layer.
2. The method of claim 1, wherein the material of the first dielectric layer comprises an subtractive coating RRC medium;
the forming a first dielectric layer filling the trench includes:
and forming a first dielectric layer filling the groove through an RRC process.
3. The method of claim 2, wherein the RRC medium comprises at least one of propylene glycol methyl ether acetate or propylene glycol monomethyl ether.
4. The method of claim 1, wherein the material of the second dielectric layer comprises an RRC dielectric and a spin-on SOD dielectric;
the forming a second dielectric layer covering the plurality of metal strips and the first dielectric layer includes:
and forming a second dielectric layer covering the plurality of metal strips and the first dielectric layer through an SOD process.
5. The method of claim 4, wherein the SOD media comprises carbon doped silicon oxide.
6. The method according to claim 1, wherein the method further comprises:
and after the plurality of metal strips covered with the second dielectric layer and the first dielectric layer are heated, flattening the second dielectric layer so as to thin the second dielectric layer.
7. The method of claim 1, wherein the semiconductor structure is used to form a metal interconnect layer of a memory.
8. A semiconductor structure, comprising:
a plurality of metal strips; grooves are formed among the metal strips, the width of each groove is smaller than a preset value, and air is filled in each groove; a covering layer is formed on the periphery of the metal strip;
a second dielectric layer on the plurality of metal strips;
wherein the semiconductor structure is formed using the manufacturing method of any one of claims 1 to 7.
9. The semiconductor structure of claim 8, wherein the material of the second dielectric layer comprises carbon-doped silicon oxide.
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