CN113441379A

CN113441379A - PMUT-on-CMOS unit suitable for high-density integration, array chip and manufacturing method

Info

Publication number: CN113441379A
Application number: CN202110991565.0A
Authority: CN
Inventors: 李晖; 尹峰
Original assignee: Nanjing Shengxi Xinying Technology Co ltd
Current assignee: Nanjing Shengxi Xinying Technology Co ltd
Priority date: 2021-08-27
Filing date: 2021-08-27
Publication date: 2021-09-28
Anticipated expiration: 2041-08-27
Also published as: CN113441379B

Abstract

The invention discloses a PMUT-on-CMOS unit suitable for high-density integration, an array chip and a manufacturing method, wherein the PMUT-on-CMOS unit suitable for high-density integration realizes a three-dimensional PMUT-on-CMOS structure through a multi-channel metal connecting line structure in the vertical direction, extends to a packaging layer through TSV and does not need to be communicated with a CMOS through a pressure welding block on the periphery of an array, the bottleneck of the traditional PMUT-on-CMOS metal interconnection is relieved, the chip area occupied by the metal interconnection is greatly reduced, the length of metal wiring is reduced, and the adverse effect of electrical parasitic effect caused by the metal interconnection on the performance of the PMUT array is solved.

Description

PMUT-on-CMOS unit suitable for high-density integration, array chip and manufacturing method

Technical Field

The invention relates to the technical field of MEMS-on-CMOS high-density monolithic integrated semiconductor sensors, in particular to a novel structure and a processing technology for monolithic integration of a 3D (3 dimensional) three-dimensional PMUT (passive micro-electromechanical transducer) framework and a CMOS pulse and control circuit.

Background

Ultrasonic diagnostic apparatus, through its ultrasonic probe, to the human body transmission ultrasonic wave, and utilize its in the human organ, tissue propagation process, because of the sound reflection, refraction, diffraction various information, receive, enlarge and carry on the information processing, form the image or blood flow Doppler, finally display on the display. A medical color ultrasonic diagnostic apparatus mainly comprises a probe, a host, a control panel, a display and other accessories.

Medical ultrasound applications are rapidly developing as human society enters a major medical age. Ultrasound scans have been spread worldwide from medical imaging, such as fetal B-ultrasound, to liver, kidney scans. Compared with other imaging technologies, the ultrasonic imaging technology has the advantages of no wound, no pain, good real-time performance, safety, low price and the like for patients, has high utilization rate in disease prevention, diagnosis and treatment of patients, is widely applied to various clinical examinations such as gastroenterology, gynecology, obstetrics, urology, thoracic department, small organs, pediatrics, cardiology, emergency treatment and the like, is gradually combined with other clinical departments to develop examination applications such as gastroenterology (ultrasonic endoscope), cardiac surgery (intravascular ultrasound) and the like, and is an indispensable examination method at present.

Ultrasound technology and products are rapidly entering people's daily lives. One of the important applications is a smartphone. The fingerprint identification of the mobile phone is quick and convenient, and the safety of the user is greatly improved. Because the ultrasonic sensor has a wide field of view, even if the ultrasonic sensor is installed at the top or the bottom of the mobile phone, accurate distance measurement can be still realized, so that an optical proximity sensor in front of the mobile phone can be omitted in the design of the mobile phone, and the full-screen design of the mobile phone is convenient to realize.

After the ultrasonic distance measuring sensor is installed in the automobile, the safe distance between driving and backing can be kept, and the automobile is very convenient. Further, MEMS ultrasonic sensors have been used in applications such as unmanned aerial vehicles and robots. In such applications, the micro ultrasonic sensor can accurately track the target, form an array space radar, monitor human body movement, position and motion changes in real time, and be seamlessly connected with the VR/AR.

Ultrasonic sensors are also widely used in industrial control. For example, changes in the shape of the surface of an aircraft wing are detected to detect icing, thereby affecting flight safety. The ultrasonic sensor is arranged on an aircraft engine, can detect whether the engine has cracks or not in real time, finds problems in time, and carries out maintenance and replacement.

The traditional ultrasonic probe is realized by using a method of mechanical cutting, arrangement and metal interconnection wiring of piezoelectric ceramic crystals, and a piece of piezoelectric ceramic crystal is firstly fixed on a supporting substrate and mechanically cut along the X and Y directions. The processing mode has low yield, is easy to cause mechanical damage, is difficult to control the cost and is difficult to realize large-scale production. More importantly, the machining precision is low, the size of the smallest finished crystal is limited, and the requirement of high-resolution medical imaging on the increasingly reduced size of the PMUT cannot be met.

MEMS (micro electro mechanical systems) technology based on CMOS process is beginning to be regarded as a development direction of ultrasonic sensors. The semiconductor MEMS ultrasonic sensor benefits from the high precision and the high yield of a CMOS process, and is the most promising technology for realizing the high-resolution medical ultrasonic array sensor.

However, the normal operation of the PMUT requires a lot of circuit support. Fig. 1 is a block circuit diagram of a typical PMUT system. It is readily seen that PMUT operation requires a high voltage (typically 10-25 volts) pulse driver circuit. The high voltage source circuit generates and outputs direct current high voltage, the direct current high voltage is converted into a specific pulse driving signal by the pulse modulation circuit, and ultrasonic waves with specific frequency are generated through the PMUT array and emitted. This is the transmission process of ultrasound.

When the ultrasonic object to be scanned, such as different human organs, is reflected back, the PMUT receives the ultrasonic wave, converts the ultrasonic wave into an electrical signal through a piezoelectric effect, inputs the electrical signal into a low-noise signal amplifier, further enters a variable gain control circuit for signal amplification, further converts an analog signal into a digital signal through an analog/digital converter circuit, outputs the digital signal to a microprocessor, and forms an ultrasonic image through an ultrasonic imaging algorithm.

PMUTs require multiple CMOS analog and digital circuits to work with, whether in the ultrasonic transmit mode or the ultrasonic receive mode. If the various circuits in the block diagram of the PMUT system circuitry were to be completed by discrete IC package blocks, multiple ICs would be required to implement such a system, with the interconnections bonded to the printed circuit board, which would be quite bulky. For large ultrasound systems, such as a floor-mounted ultrasound scanner, this may not be a problem. However, miniaturization of the ultrasound scanner and even the increase in the volume of the portable ultrasound scanner are increasing today, and the ultrasound scanner must be reduced in size. Such a planar architecture has not been satisfactory.

The MEMS-on-CMOS is a semiconductor sensor technology which realizes high-density monolithic integration by making a MEMS (Micro-Electrical-Mechanical System) Micro-electromechanical System sensor above a CMOS chip. And (4) the output power of the PMUT: piezoelectric micro-machined Ultrasonic Transducers (piezoelectronic micro-machined Transducers) are also like other MEMS technologies, and the integration level is expected to be improved by means of technical paths of a PMUT-on-CMOS, so that a high-density PMUT array is provided for applications such as high-resolution Ultrasonic scanning and Ultrasonic fingerprint identification.

The PMUT-on-CMOS, as shown in fig. 2 (a), can vertically stack the two original chips by monolithic integration, thereby reducing the planar size, the number of packaged ICs, and the system volume.

However, this seems straightforward and logical solution has not been widely adopted so far, mainly because of the new technical challenges to implement PMUT-on-CMOS in the existing planar process architecture.

First, in the prior art, the PMUT array must be interconnected to the underlying CMOS circuitry via a peripheral bond pad (or mini-bond pad). As a result, metal wiring faces two major limitations. First, if it is desired to have an independent top level metal connection for each cell, as shown in fig. 2 (b), an additional number of metal routing lines must be added. As a result, the duty cycle of the PMUT cells (the ratio of the area in the cell in which ultrasound can be generated to the area of the entire cell) is reduced by the metal wiring, which simultaneously occupies a large proportion of the chip area outside the array, and the parasitic resistance, capacitance, and speed, power consumption, etc., caused by the additional metal wiring, are adversely affected. Second, in most of the designs of PMUT arrays today, in order to reduce the extra metal wiring, a common column metal connection (common-bulk connection) is shared by a plurality of cells in the same column, and as a result, cross-talk of the cells becomes serious, and the main performance parameters of the PMUT array, such as effective frequency bandwidth, signal-to-noise ratio, etc., are adversely affected.

In addition, building the PMUT above the CMOS, the choice of materials and the process are limited. For example, silicon material is a good mechanical substrate layer for PMUTs from material mechanical properties, repeatability, and uniformity considerations. However, above CMOS ICs, there is no way to form a single crystal silicon mechanical layer on a CMOS wafer due to the limitations of silicon material growth conditions, such as temperatures above 1000 degrees for silicon epitaxy.

The need for high-end development of ultrasound products is endless. Medical ultrasound imaging will require increasingly larger PMUT arrays to achieve higher resolution; more PMUT units will be required for fingerprinting imaging to achieve higher resolution. Unfortunately, the PMUT technology of today, in the direction of continued miniaturization, has encountered bottlenecks that require technological breakthroughs.

The most commonly used materials for PMUT thin film piezoelectric ultrasonic transducers are AlN (aluminum nitride) and PZT (lead zirconate titanate, pb (zrti) O3, abbreviated PZT). These materials and their process are also significantly different from standard CMOS processes. For example PZT materials, must have special, unlike CMOS processes, deposition equipment, etching and cleaning equipment, requiring a considerable investment. Meanwhile, the PZT material can cause metal contamination to the CMOS process, affecting the performance and reliability of the CMOS product. Thus, there are only a few PMUT process lines worldwide. The PMUT process is added on the basis of the CMOS process, and a device structure, a process flow, and a system design are continuously created and updated for manufacturing the ultrasonic transducer with high performance and low cost. AlN (aluminum nitride) piezoelectric material, like PZT, also requires special machinery and equipment, with additional investment requirements.

A typical PMUT piezoelectric ultrasound transducer arrangement 100 is shown in fig. 3 and includes:

the substrate material 160, which may be a silicon material or a silicon dioxide material, is typically deposited on the silicon substrate.

The cavity 120, which is typically a cavity etched into the substrate material, leaves room for the PMUT to mechanically vibrate up and down, emit, or receive ultrasound.

The mechanical layer 130, which serves as a mechanical support for the vibratable membrane of the PMUT, ensures the service life of the PMUT. The mechanical layer 130 material (thickness, specific gravity, Young's modulus, etc.) also affects the frequency of the PMUT vibrations.

The oxide layer 132 is typically a silicon dioxide layer that is created on the silicon surface during CMOS processing. In addition to protecting the silicon surface, the thickness of the oxide layer 132 also affects the PMUT vibration frequency.

The sandwich stack of piezoelectric layers comprises a layer 115 of piezoelectric material, associated electrode layers arranged below and above said piezoelectric layer 115, a lower electrode 112 and an upper electrode 114, respectively.

The most commonly used materials for the piezoelectric material layer 115 are PZT lead zirconate titanate ((pb (zrti) O3, abbreviated PZT) and aluminum nitride (AlN).

The lower electrode 112 and the upper electrode 114 are typically platinum-gold Pt material or a multilayer structure of platinum and titanium metal. The lower electrode 112 and the upper electrode 114 generate an electric field in the piezoelectric material, thereby generating expansion and compression of the material, and further generating mechanical vibration in a vertical direction, and transmitting ultrasonic waves. This is the well-known piezoelectric effect.

The frequency of the PMUT mechanical vibration is related to the materials of the layers in the sandwich, the mechanical layer 130, the oxide layer 132, the thickness of all materials, and the shape and size of the cavity 120. The mechanical stress of all materials also has an effect on the vibration frequency.

High resolution, high integration medical applications PMUT ultrasound probes require high frequencies of 10-50MHz megahertz. The requirements for the dimensions and the accuracy of different structures in the PMUT structure 100 are high, for example, the dimensions of the cavity 120 and the control of the variation range of the dimensions of the cavity 120 directly affect the working frequency, the working bandwidth and other key parameters of the ultrasonic probe. The currently common method of etching from the back side of the silicon wafer to form the cavity 120 structure may result in a variation of the size of the cavity 120 structure of 5-10 microns or even larger. The requirements of high frequency and high resolution cannot be met at all. Meanwhile, the method for forming the cavity 120 structure by etching from the back of the silicon wafer is difficult to form different cavity 120 structure sizes at the same time. This limits the possibilities of making a single-chip multi-frequency ultrasound probe, which is a great limitation in application.

Similar to the size of the cavity 120 dimensions, the control requirements for the range of variations in the cavity 120 dimensions, the film thickness and control thereof in the PMUT piezoelectric ultrasonic transducer structure 100 are also critical. For example, the piezoelectric material layer 115, the mechanical layer 130, the lower electrode 112, the upper electrode 114, etc., the film thickness and its control, the specific gravity of the material, the young's modulus, and even the mechanical stress inside the material directly affect the key parameters of the ultrasonic probe, such as the working frequency, the working bandwidth, the ultrasonic output power, the electromechanical coupling coefficient, etc.

In the prior PMUT array technology and product application, the electrical connection between the PMUT and peripheral circuits and a system is realized by using a crystal cutting method or a MEMS semiconductor IC method. Fig. 5 is a schematic top view of a typical PMUT array chip. The center of the chip is a two-dimensional array of PMUT 7X 12, and the periphery of the chip is provided with bonding pads for electrically connecting with pins of a circuit package. Since each PMUT cell in the array must be connected to a bond pad, the metal wiring to make the electrical connection has a lead width, a design rule for lead spacing requires, and as a result, a large portion of the chip area is actually used for metal wiring. The chip area occupied by metal wiring is much larger than that of PMUT array, which is very uneconomical. Meanwhile, the parasitic effect of resistance and capacitance is increased due to the longer metal wiring length, and the working frequency, the power consumption and the like of the PMUT array are adversely affected. The uniformity of the PMUT array operation is also directly affected by the uneven wiring length.

Disclosure of Invention

In order to overcome the defects of the conventional PMUT-on-CMOS, the invention provides a breakthrough 3D PMUT-on-CMOS device and a process architecture. The 3D device and the process manufacturing flow can realize the continuous miniaturization of the PMUT array; the 3D interconnection structure is introduced, vertical interconnection of a unit level is realized, the connection with a CMOS (complementary metal-oxide-semiconductor transistor) is not needed through a bonding pad on the periphery of the array, the bottleneck of the traditional metal interconnection of the PMUT-on-CMOS is eliminated, the length of metal wiring and the negative influence of the metal wiring on the performance of the PMUT array are obviously reduced, the chip area and the system volume are reduced, and the cost is reduced.

In the application level, the unit of the new generation of the PMUT-on-CMOS provided by the invention is continuously miniaturized, the chip area is continuously reduced due to more effective 3D interconnection, a brand new way is provided for manufacturing ultrasonic products with high integration and high resolution, and the invention contributes to accelerating the miniaturization and portable application of the PMUT ultrasonic transducer.

To achieve the above object, an embodiment of the present invention provides a PMUT-on-CMOS cell suitable for high density integration, comprising, from bottom to top: the CMOS unit comprises a silicon substrate, a substrate material, an oxide layer, a mechanical layer, a lower metal layer, a piezoelectric material layer and an upper metal layer, wherein the substrate material is provided with a cavity and two second metal wiring layers; the silicon substrate is also provided with two silicon front and back perforated TSVs for realizing the vertical interconnection of the metal interconnection layer and the back surface of the silicon substrate; the ultrasonic transducer is also provided with an upper-layer metal link hole ZTM for vertically interconnecting the upper-layer metal layer and one of the two second-layer metal wirings, and a lower-layer metal link hole ZBM for vertically interconnecting the lower-layer metal layer and the other of the two second-layer metal wirings.

Preferably, the mechanical layer is made of the same material as the silicon substrate.

Preferably, a silicon nitride layer is deposited at the bottom of the cavity.

The embodiment of the invention also provides an array chip which is characterized by comprising a plurality of the PMUT-on-CMOS units suitable for high-density integration, wherein the PMUT-on-CMOS units vertically connect the upper metal layer to one of the second metal wirings through the upper metal link hole ZTM, vertically connect the lower metal layer to the other second metal wiring through the lower metal link hole ZBM, then vertically connect the PMUT-on-CMOS units to corresponding metal interconnection layers through the two metal lead holes, and respectively lead the PMUT-on-CMOS units to the back of a silicon chip through the two silicon front and back through-hole TSVs to be connected to a printed circuit board.

The embodiment of the invention also provides a manufacturing method of the PMUT-on-CMOS unit, which is characterized by comprising the following steps:

step 1, preparing a first silicon wafer, growing silicon dioxide on the surface of the first silicon wafer, and manufacturing a CMOS circuit unit;

step 2, manufacturing a PMUT unit on the CMOS circuit unit, specifically including:

step 2-1, depositing a substrate material at a low temperature, and performing chemical mechanical polishing to form a flat substrate material surface;

step 2-2, photoetching, corroding and filling metal deposition to form a metal lead hole between the metal interconnection layer of the MOS circuit unit and the second layer of metal wiring;

step 2-3, depositing a metal layer, photoetching and corroding a second layer of metal wiring, removing photoresist and cleaning;

2-4, depositing a substrate material at a low temperature, and performing chemical mechanical polishing to form a flat substrate material surface;

step 2-5, photoetching and corroding a cavity, removing the photoresist and cleaning;

2-6, preparing a second silicon wafer, growing silicon dioxide on the surface, depositing a substrate material at a low temperature, and finishing bonding with the first silicon wafer;

2-7, grinding the back of the second silicon wafer, corroding with chemical liquid, and chemically and mechanically polishing to reduce the thickness;

2-8, depositing a lower metal layer by using metal;

2-9, depositing a piezoelectric material layer by using a piezoelectric material;

step 2-10, depositing top metal and photoetching to form an upper metal layer;

step 2-11, photoetching, corroding and depositing and filling metal to form a metal link hole;

step 2-12, performing metal photoetching corrosion to form required wiring;

and 3, photoetching, corroding and penetrating the front side and the back side of the silicon substrate, and depositing metal to form the TSV with through holes on the front side and the back side of the silicon.

Preferably, in the step 2-6, after the silicon dioxide surface is subjected to plasma treatment by using a silicon dioxide Fusion Bond technology, the wafer substrate materials are aligned face to face, and then are subjected to pressure heating and annealing to complete bonding.

Preferably, the lower metal layer is a multilayer structure of a lower titanium metal layer and an upper platinum material layer, the thicknesses of the titanium metal layer and the platinum material layer are respectively 20 nanometers and 100 nanometers, the titanium metal layer is formed by a sputtering method, and the platinum material layer is formed by evaporation of a high-current high-temperature electron gun in vacuum.

Preferably, the metal lead holes and the metal link holes are formed by metal titanium/titanium nitride sputtering and metal aluminum deposition on a hot substrate.

Preferably, in the step 2-5, a Cavity pattern is formed by photolithography, and then a substrate material is etched by plasma chemical vapor to form a Cavity, wherein the depth of the Cavity is 2 microns.

Preferably, the thickness of the second silicon wafer after thinning is 2-3 microns.

Has the advantages that:

in the existing 2D plane PMUT-on-CMOS array design and process, the chip area occupied by metal wiring is far larger than that occupied by the PMUT array, and the technology is not economical. Meanwhile, the long wiring length has adverse effects on the important indexes of the PMUT, such as working frequency, power consumption and heat dissipation, and the uniformity of the PMUT array operation can be directly influenced due to the uneven wiring length. The PMUT-on-CMOS unit provided by the invention realizes a PMUT-on-CMOS three-dimensional structure Through a multichannel metal connecting line structure in the vertical direction, extends to a packaging layer surface Through TSV (Through Silicon Via), and is not communicated with a CMOS Through a pressure welding block at the periphery of an array, so that the bottleneck of the traditional PMUT-on-CMOS metal interconnection is eliminated, the chip area occupied by the metal interconnection is greatly reduced, the length of metal wiring is reduced, and the adverse effect of electrical parasitic effect caused by the metal interconnection on the performance of the PMUT array is further reduced. The three-dimensional PMUT-on-CMOS structure design and the process flow provided by the invention can obviously reduce the size of a chip and the volume of a system, simultaneously reduce parasitic resistance caused by metal wiring and power consumption, delay and nonuniformity related to capacitance, have obvious benefits on improving the performance of a product, reducing the cost, improving the yield and the like, and can realize the miniaturization and high-density integration of the chip. The three-dimensional PMUT-on-CMOS structure design and the process flow provided by the invention have good compatibility with a semiconductor mainstream process, a semiconductor mainstream device and the existing chip packaging process. The invention can support high-resolution medical ultrasonic surface array, realizes multi-frequency scanning of one ultrasonic probe, and is also very suitable for high-integration-level and low-cost commercial application of mobile phone fingerprint identification. The special 3-dimensional PMUT-on-CMOS framework can obviously reduce the volume of a chip and a packaging system, and is suitable for the design of a small ultrasonic probe entering a human body.

Drawings

FIG. 1 is a circuit block diagram of a PMUT system;

FIG. 2 (a) is a prior art PMUT-on-CMOS architecture;

FIG. 2 (b) is a schematic diagram of a metal interconnection of a conventional PMUT-on-CMOS architecture;

FIG. 3 is a schematic diagram of a conventional 2D PMUT structure;

FIG. 4 is a schematic diagram of a first embodiment of a PMUT-on-CMOS structure;

FIG. 5 is a schematic diagram of a conventional PMUT array chip structure;

FIG. 6 is a schematic structural diagram of a PMUT array chip according to a third embodiment of the invention;

FIG. 7 is a first flow chart of the CMOS circuit unit fabrication;

FIG. 8 is a second flow chart of the CMOS circuit unit fabrication;

FIG. 9 is a third process flow diagram for fabricating a CMOS circuit unit;

FIG. 10 is a schematic view of a process corresponding to step 2-1 in the fourth embodiment of the present invention;

FIG. 11 is a schematic view of a process corresponding to step 2-2 of the fourth embodiment of the present invention;

FIG. 12 is a schematic diagram of a process corresponding to step 2-3 of the present invention;

FIG. 13 is a schematic diagram of a process corresponding to step 2-4 of the fourth embodiment of the present invention;

FIG. 14 is a schematic diagram of a process corresponding to step 2-5 of the present invention;

FIG. 15 is a schematic diagram of a fourth step 2-6 second silicon wafer according to an embodiment of the present invention;

FIG. 16 is a schematic diagram of a four-step 2-6 bonding process according to an embodiment of the present invention;

FIG. 17 is a schematic diagram of the completion of four step 2-6 bonding according to one embodiment of the present invention;

FIG. 18 is a schematic diagram of a process corresponding to step 2-7 of the fourth embodiment of the present invention;

FIG. 19 is a schematic diagram of a process corresponding to step 2-8 through step 2-10 according to an embodiment of the present invention;

FIG. 20 is a schematic diagram of a four step 2-10 process for forming an upper metal layer according to an embodiment of the present invention;

FIG. 21 is a schematic diagram of a four-step 2-11 PZT and bottom metal etching process in accordance with an embodiment of the present invention;

FIG. 22 is a schematic diagram of a four-step 2-11 vertical via etching process according to an embodiment of the present invention;

FIG. 23 is a schematic diagram of a four step 2-11 Ti/TiN/Al deposition process in accordance with an embodiment of the present invention.

Detailed Description

The technical solution of the present invention is further described in detail with reference to the specific examples below.

Example one

As shown in fig. 4, the present embodiment provides a PMUT-on-CMOS cell suitable for high density integration, comprising, from bottom to top, a silicon substrate 161, a substrate material 160, an oxide layer 132, a mechanical layer 130, a lower metal layer 112, a piezoelectric material layer 115, and an upper metal layer 114. The substrate material 160 is arranged with the cavity 120, two second-layer metal wirings 202. The silicon substrate 161 is arranged with a CMOS unit (161-CMOS in the figure), a P-type substrate of the CMOS unit is connected with the silicon substrate 161, and two ends of a metal interconnection layer 201 of the CMOS unit are vertically interconnected with two second-layer metal wirings 202 above the metal interconnection layer 201 through two metal lead holes 212 respectively. The silicon substrate 161 is provided with two through-hole TSVs 162 penetrating through the whole silicon substrate 161 from front to back, so that two ends of the metal interconnection layer 201 of the CMOS unit are respectively vertically interconnected with the back of the silicon substrate 161. The ultrasonic transducer is further arranged with an upper layer metal link hole ZTM 163-1 and a lower layer metal link hole ZBM 163-2, the two metal link holes penetrating through the piezoelectric material layer 115, the lower layer metal layer 112, the mechanical layer 130, the oxide layer 132 into the substrate material 160, the upper layer metal link hole ZTM 163-1 enabling the upper layer metal layer 114 to be vertically interconnected with one of the two second layer metal wirings 202, and the lower layer metal link hole ZBM 163-2 enabling the lower layer metal layer 112 to be vertically interconnected with the other of the two second layer metal wirings 202.

The upper and lower metal link holes are vertically connected through the PMUT top metal TM and the piezoelectric material PZT with different heights, and the cross section of the link holes is similar to a Z shape, so the link holes are called Z-shaped holes. The Z-shaped via may enable electrical connection of more than two junctions, for example, the upper metal link hole ZTM 163-1 may enable vertical interconnection of the upper metal layer 114 with the second metal routing 202 while other upper metals adjacent to the PMUT may be connected.

The PMUT-on-CMOS unit suitable for high-density integration of the embodiment utilizes the CMOS metal interconnection layer as the first layer of metal wiring, and forms a double-layer wiring design together with the second layer of metal wiring, thereby not only realizing the interconnection with the CMOS, but also providing the double-layer metal wiring density, remarkably increasing the interconnectivity of the PMUT array, realizing the parallel connection and the serial connection of a plurality of PMUT-on-CMOS units, providing a lot of flexibility for the PMUT array design, greatly reducing the length and the occupied area of the metal wiring, and remarkably reducing the chip area.

In the figure, the aluminum metal TSV Pad 162-2 is an aluminum structure which needs to be specially designed in the CMOS manufacturing process and forms a TSV etching stop layer to help the TSV etching stop at a specific position and simultaneously form electrical connection between the TSV and other CMOS circuits. The structure can be arranged as a whole with the metal interconnection layer of the CMOS circuit unit, or can be arranged separately and interconnected with the metal interconnection layer of the CMOS circuit unit.

The PMUT-on-CMOS unit suitable for high density integration of the present embodiment vertically interconnects the metal electrodes in the piezoelectric layer sandwich stack structure to the second layer metal wiring through the vertically oriented metal link holes, and then vertically interconnects to the first layer metal wiring (metal interconnect layer of the CMOS unit) through the vertically oriented metal lead holes, and then interconnects to the back surface of the silicon chip through the through-hole TSV on the front and back surfaces of the silicon. By adopting the vertical wiring design, most of the bonding blocks and metal leads in the conventional planar PMUT-on-COMS can be omitted and led to the back of the silicon wafer from the vertical direction, so that the transition of metal connecting wires from 2D (two-dimensional) planar wiring to 3D (three-dimensional) is realized, and the chip and the packaging volume can be obviously reduced.

Example two

The present embodiment provides a PMUT-on-CMOS cell suitable for high density integration, and similar to the architecture of the first embodiment, considering the overall design of PMUT-on-CMOS, when the resolution requirement is high and a large-scale array is required, the implementation of the interconnect may require multiple layers of wiring. For example, when artificial intelligence algorithms are also put into PMUT-on-CMOS ultrasonic designs, CMOS IC designs may require 5-6 layers of metal routing. In the process flow of the invention, the wiring architecture is considered particularly, and the process flow has great flexibility in the number of wiring layers. Therefore, in this embodiment, on the basis of the first embodiment, at least one layer of metal wirings is further disposed above the second layer of metal wirings, each layer of metal wirings of the at least one layer of metal wirings is vertically interconnected through a metal via, and a lowermost layer of metal wirings of the at least one layer of metal wirings is vertically interconnected with the second layer of metal wirings through metal vias. Each layer of the at least one layer of metal wiring is also divided into two metal wirings, and the two metal wirings on the same layer are vertically interconnected with the two metal wirings on the next layer through two metal lead holes respectively.

EXAMPLE III

The present embodiment provides an array chip, which includes a plurality of PMUT-on-CMOS units suitable for high density integration as described in the first embodiment or the second embodiment. The PMUT-on-CMOS unit vertically connects the upper metal layer 114 to the corresponding second metal wiring 202 through the upper metal link hole ZTM 163-1, vertically connects the lower metal layer 112 to the corresponding second metal wiring 202 through the lower metal link hole ZBM 163-2, vertically connects to the metal interconnection layer 201 of the CMOS unit through the two metal lead holes 212, and leads to the back of the silicon chip to be connected to the printed circuit board through the two silicon front and back through-hole TSVs 162, so that the serial and parallel connection of the plurality of piezoelectric micromachined ultrasonic transducers can be realized through reasonable wiring.

As shown in fig. 5 and 6, compared with the existing planar PMUT-on-CMOS interconnection architecture, the PMUT-on-CMOS unit adopting the 3D structure of the present invention does not need to be communicated with the CMOS through the bonding pads around the array, which greatly reduces the chip area and the wiring length occupied by the metal interconnection. Electrical simulations were performed with PMUT-on-CMOS chip layout wiring in a "7X 128 array", 7 rows with 128 bit PMUT cells per row, for a total of 896 PMUT working cells. For process uniformity considerations, 3 columns of dummy cells (dummy cells) are placed on each row side and participate in all process steps to reduce non-uniformity caused by edge effects during the process. However, these units are not electrically connected. Compared with the chip layout electrical simulation performance result obtained by the 2D PMUT-on-CMOS structure, the 3D PMUT-on-CMOS structure has the following main product parameters: the chip area is reduced by 240%, the power consumption is reduced by 50%, the array uniformity is improved by 25%, and the cost is reduced by 30%.

Example four

The present embodiment provides the method for manufacturing a PMUT-on-CMOS unit suitable for high density integration according to the first embodiment, wherein the process flow includes three parts, and the first part is a process flow of a CMOS circuit, such as a PMUT pulse generation and control circuit. The innovation of this embodiment is not in the CMOS circuit process itself, but in how the CMOS is fused as part of a 3D PMUT-on-CMOS. The main part of the CMOS can adopt the standard flow in the industry, but at the same time, the whole compatibility with the 3D PMUT process and the 3D TSV (Through Silicon Via) process needs to be considered. The second part is a process flow of the PMUT 3D array, the third part is a 3D TSV (Through Silicon Via ) process flow, and the key point is how the TSV is fused with the 3D framework to form a part of the whole process integration.

The method specifically comprises the following steps:

step 1, preparing a first silicon wafer, growing silicon dioxide of about 100 nanometers on the surface to form a silicon substrate, and manufacturing a CMOS circuit unit on the silicon substrate. The CMOS circuit process is shown in fig. 7-9 and implemented using standard processes in the industry. FIG. 7 includes the steps of (a) preparing a starting material of P-type silicon, (b) forming a silicon dioxide buffer layer, (c) photoresist coating, (d) N-type well etching, (e) etching the N-well silicon dioxide layer, (f), (g) diffusing or ion implanting to form N-wells, and (h) removing the silicon dioxide buffer layer. As shown in fig. 8, the method further comprises the following steps of (a) transistor gate oxidation and polysilicon deposition, (b) polysilicon gate photoetching and etching, (c) photoresist coating, (d) N + source/drain region and N-well connecting region photoetching, (e) source/drain region ion implantation, and (f) photoresist removal. Fig. 9 further includes the steps of (a) P + source/drain region, P-bottom connection region formation (via lithography, ion implantation, photoresist stripping, annealing process, etc.), (b) ILD electrical isolation layer formation including undoped silicon dioxide deposition, doped silicon dioxide deposition, reflow, Contact metal Contact hole lithography, etching, etc., and (c) metal interconnect layer formation including Contact metal sputtering, aluminum metal deposition, metal layer lithography, etching, photoresist stripping, etc.

The PMUT-on-CMOS global design may require multiple layers of wiring for interconnect implementation when resolution requirements are high, requiring larger arrays. For example, when artificial intelligence algorithms are also put into PMUT-on-CMOS ultrasonic designs, CMOS IC designs may require 5-6 layers of metal routing. In the process flow of the invention, the wiring architecture is considered particularly, and the process flow has great flexibility in the number of wiring layers.

Step 2, further manufacturing a PMUT unit on the CMOS circuit unit, as shown in fig. 10 to 23, specifically including:

step 2-1, as shown in fig. 10, depositing silicon dioxide (SiO 2) of about 800 nm on the metal interconnection layer of the cmos circuit unit, and then performing cmp (chemical Mechanical polish) to form a flat SiO2 surface, which is beneficial to subsequent processes such as photo-etching and glue coating;

step 2-2, as shown in fig. 11, forming metal lead holes Via between the metal wiring layers by photoetching, forming Via holes by plasma dry etching, removing photoresist, cleaning, then performing metal titanium/titanium nitride sputtering, and filling Via interconnection holes by thermal substrate metal aluminum deposition (if the Via holes are smaller, chemical vapor deposition of metal tungsten can be used to replace aluminum to form Via holes);

step 2-3, as shown in fig. 12, depositing a metal layer, photoetching and corroding a second layer of metal wiring, removing photoresist and cleaning;

2-4, as shown in fig. 13, depositing SiO2 substrate material at low temperature, and carrying out chemical mechanical polishing to form a flat substrate material surface;

the deposition temperature of the low-temperature silicon dioxide SiO2 (plasma enhanced chemical vapor deposition, PECVD) is 250-300 ℃, and the thickness of SiO2 is about 3 microns. Chemical mechanical polishing is then performed to form a flat SiO2 surface. In cooperation with the special process steps of the PMUT-on-CMOS, a silicon dioxide-silicon nitride-silicon dioxide sandwich structure is introduced into a dielectric layer (similar to a passivation layer in a CMOS process), a layer of silicon nitride is deposited on the silicon dioxide at the bottom of a cavity body at a part where the cavity body 120 needs to be formed, and the corrosion speed of the silicon dioxide is far higher than the corrosion speed of the silicon nitride, so that the cavity body is easily formed by adopting a silicon dioxide dry etching method, meanwhile, the depth of the cavity body can be accurately controlled, and the miniaturization of a device is favorably realized.

Step 2-5, as shown in fig. 14, the silicon dioxide cavity is etched by photolithography: coating photoresist, photoetching to form Cavity figure, plasma chemical gas phase etching SiO2 to form Cavity with depth of about 2 microns. And then removing the photoresist and cleaning.

And 2-6, as shown in figures 15-17, preparing a second silicon wafer, growing silicon dioxide with the diameter of about 100 nanometers on the surface, depositing a substrate material at a low temperature, and finishing bonding with the first silicon wafer. After the surface of SiO2 is treated by plasma by adopting the silicon dioxide Fusion Bond technology which is mature in the industry, the SiO2 of the wafer is aligned face to face, pressurized and heated, and then is annealed, thus completing bonding.

And 2-7, as shown in fig. 18, after bonding, grinding the back of the second silicon wafer to reduce the thickness to be less than 100 microns. Then chemical liquid corrosion is carried out to further thin the silicon slice to 5-6 microns, and finally chemical Mechanical polishing CMP (chemical Mechanical polishing) is carried out, and the thickness of the residual silicon slice is 2-3 microns.

In the mechanical layer 130 structure, a commonly used material is silicon oxide, silicon nitride, polysilicon, or a multi-layer thin film combination thereof. All these materials are not single crystal materials, in other words, due to the heterosequence form of the molecular structure, the mechanical property parameters of these materials, and the mechanical stress in the thin film are affected by the process conditions, and the controllability and the manufacturing repeatability are problematic. According to the method for bonding and thinning the silicon wafer, the silicon single crystal is introduced into the mechanical layer, and the mechanical layer is high in quality and strength, so that the repeatability of mechanical parameters of the mechanical layer is optimal, the internal mechanical stress is reduced to the minimum, the uniformity is high, and the manufacturing repeatability is good.

Step 2-8, as shown in FIG. 19, metal is deposited as the lower metal layer: the multilayer structure of Ti and Pt is adopted, and the thicknesses are respectively 20 nanometers and 100 nanometers. Titanium metal Ti increases the adhesion of the metal layer to silicon and silicon oxide, while platinum Pt is one of the best conductive layers to improve piezoelectric efficiency. Ti metal is formed by sputtering, while platinum Pt is formed by evaporation in vacuum using a high current, high temperature electron gun.

Step 2-9, as shown in fig. 19, depositing a piezoelectric material layer on the piezoelectric material;

the piezoelectric material may be PZT or other piezoelectric material such as AlN. Here we will describe the PZT as a representative. PZT deposition: PZT (lead zirconate titanate, pb (zrti) O3, abbreviated PZT), which is formed by a sputtering method, is a solid target material prepared by mixing in advance in a specific atomic ratio. Under high vacuum, the PZT target material is sputtered by the plasma generated by high voltage and is deposited on the surface of the silicon slice. And (3) applying a certain temperature to the silicon substrate to recrystallize the PZT during sputtering to form the required piezoelectric crystal. The thickness of the PZT deposit is around 1 micron. The AlN material is also formed by a sputtering method, the working temperature can be lower (less than 400 ℃ or even lower) during sputtering, and the influence of the temperature on the existing metal in the subsequent process integration is more favorably reduced.

Step 2-10, as shown in fig. 19-20, depositing a top metal layer, and performing photolithography corrosion to form an upper metal layer; the PZT top metal deposition also used platinum Pt, which was 0.1 micron at 100 nm. Platinum Pt is an inert metal and is relatively difficult to form by a liquid etching method, and in this embodiment, a top metal is etched by a plasma dry gas phase etching method.

Step 2-11, as shown in fig. 21-23, photoetching and etching, and metal deposition and filling to form a metal link hole;

as the metal link hole adopts a Z-shaped hole, PZT etching is firstly carried out, and only PZT is etched, as shown in a region 13 in figure 21, the PZT etching adopts an international advanced hydrogen chloride fluoride hydrogen chloride plasma dry-method gas-phase etching method, the method has good etching uniformity, the edge of the PZT material after etching is neat, and a certain slope is provided, thereby facilitating the subsequent process steps. The etching of the AlN material can be performed by phosphoric acid or corresponding plasma dry etching, and the process needs to be relatively adjusted. The PZT and underlying metal are then etched, as in region 14 of fig. 21, which simultaneously etches the PZT and underlying metal using a plasma dry vapor etch. Referring to fig. 22, a Z-via vertical via Zia is etched by photolithography, one of the key structures for 3D vertical electrical connections is the formation of a Z-via vertical via Zia, which serves to connect the upper and lower metal layers of PMUT to the second metal wiring 202 in the vertical direction, and to other parts of the circuit, or to the backside TSV pad, to external circuitry via metal wire vias 201. After Zia photoetching holes are formed, the mechanical layer and the silicon dioxide layer are etched continuously, the second layer of metal wiring 202 is stopped, and photoresist is removed and cleaning is carried out. FIG. 23 is followed by a Ti/TiN/Al deposition wherein the Ti/TiN is formed by sputtering and the aluminum is deposited by thermal liner deposition to enhance aluminum metal fill into Zia holes. Finally, metal is etched and corroded to form required wiring;

step 2-12, performing metal photoetching corrosion to form required wiring;

and 3, photoetching, corroding and penetrating the front side and the back side of the silicon substrate, and depositing metal to form the TSV with through holes on the front side and the back side of the silicon. The method specifically comprises the following steps:

(a) front protection of the PMUT wafer: forming a cavity, covering the glass protective layer

(b) Grinding and thinning of silicon substrate

(c) Pressing welding block, selective etching and thinning scribing groove

(d) Back metal layer

(e) Laser drilling to pressure welding block

(f) Sputtering (Ti/Cu), copper plating

(g) Etched back wiring

(h) Nickel-gold (Ni/Au) plating, etching ball bonding region

(i) Forming a backside ball bond array.

In the embodiment, the aluminum metal TSV Pad 162-2 is used as a TSV corrosion stop layer (etch stop plating Pad), and the direct welding of the PMUT-on-CMOS array to the printed circuit board is realized by utilizing the TSV solder ball array, so that the volume is small, the number of external leads is small, and the miniaturization of a system is facilitated.

Therefore, all manufacturing processes of the high-density integrated PMUT-on-CMOS unit are completed, the metal link holes are connected in the vertical direction, wiring efficiency is improved through twice metal wiring, metal interconnection is led to the back side from the front side of the wafer, the chip area occupied by the metal wiring is obviously reduced, and the chip size is greatly reduced.

The process flow of the PMUT-on-CMOS unit of the embodiment is compatible with the mainstream semiconductor process and equipment, the vertical direction connecting line is compatible with the conventional chip bga (ball Grid array) packaging process, and the PMUT-on-CMOS unit has wide adaptability.

Claims

1. A PMUT-on-CMOS cell suitable for high density integration, comprising from bottom to top: the piezoelectric device comprises a silicon substrate (161), a substrate material (160), an oxide layer (132), a mechanical layer (130), a lower metal layer (112), a piezoelectric material layer (115) and an upper metal layer (114), wherein the substrate material (160) is provided with at least one cavity (120) and two second-layer metal wirings (202), the silicon substrate (161) is provided with a CMOS unit, a P-type substrate of the CMOS unit is connected with the silicon substrate (161), and metal interconnection layers (201) of the CMOS unit are vertically interconnected with the two second-layer metal wirings (202) above the metal interconnection layers (201) through two metal lead holes (212); the silicon substrate (161) is also provided with two through-silicon-via TSVs (162) which vertically interconnect the metal interconnection layer (201) and the back surface of the silicon substrate (161); the PMUT-on-CMOS cell is further arranged with an upper-layer metal link hole ZTM (163-1) that vertically interconnects the upper-layer metal layer (114) and one (202) of the two second-layer metal wirings (202), and a lower-layer metal link hole ZBM (163-2) that vertically interconnects the lower-layer metal layer (112) and the other (202) of the two second-layer metal wirings (202).

2. PMUT-on-CMOS-cell suitable for high density integration according to claim 1, characterized in that the mechanical layer (130) is of the same material as the silicon substrate (161).

3. The PMUT-on-CMOS cell suitable for high density integration according to claim 1, wherein a silicon nitride layer is deposited at the bottom of the cavity (120).

4. The PMUT-on-CMOS cell suitable for high density integration according to claim 1, wherein the substrate material further comprises at least one layer of metal wiring above the second layer of metal wiring, each layer of metal wiring of the at least one layer of metal wiring being vertically interconnected by a metal via, a lowermost layer of metal wiring of the at least one layer of metal wiring being vertically interconnected with the second layer of metal wiring by a metal via.

5. An array chip comprising a plurality of PMUT-on-CMOS cells suitable for high density integration according to any one of claims 1 to 4, wherein the PMUT-on-CMOS cells vertically connect the upper metal layer (114) to one of the second-layer metal wirings (202) through the upper metal link hole ZTM (163-1), vertically connect the lower metal layer (112) to the other second-layer metal wiring (202) through the lower metal link hole ZBM (163-2), and vertically connect to the corresponding metal interconnection layer (201) through the two metal lead holes (212), respectively, and then lead to the back surface of the silicon chip through the two through-hole TSV on the front and back surfaces of the silicon chip to be connected to a printed circuit board.

6. A method of fabricating a PMUT-on-CMOS cell as claimed in any one of claims 1 to 4, comprising the steps of:

2-8, depositing a lower metal layer by using metal;

step 2-10, depositing top metal and photoetching to form an upper metal layer;

step 2-12, performing metal photoetching corrosion to form required wiring;

7. The method of claim 6, wherein in steps 2-6, after plasma treatment of the silicon dioxide surface by silicon dioxide Fusion Bond technique, the wafer substrate materials are aligned face to face, pressed, heated, and annealed to complete bonding.

8. The manufacturing method according to claim 6, wherein the lower metal layer is a multilayer structure of a lower titanium layer and an upper platinum layer, the thicknesses of the titanium layer and the platinum layer are 20 nm and 100 nm, respectively, the titanium layer is formed by a sputtering method, and the platinum layer is formed by evaporation in vacuum using a high-current high-temperature electron gun.

9. The method of claim 6 wherein the metal pin holes and metal link holes are formed by titanium/titanium nitride sputtering, thermal substrate aluminum metal deposition.

10. The method according to claim 6, wherein in the step 2-5, a Cavity pattern is formed by photolithography, and then the substrate material is etched by plasma chemical vapor to form a Cavity, wherein the Cavity has a depth of 2 μm.

11. The method of manufacturing according to claim 6 wherein the second silicon wafer has a reduced thickness of 2 to 3 microns.