CN113436670B - Memory detection method and memory detection system - Google Patents
Memory detection method and memory detection system Download PDFInfo
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- CN113436670B CN113436670B CN202010207558.2A CN202010207558A CN113436670B CN 113436670 B CN113436670 B CN 113436670B CN 202010207558 A CN202010207558 A CN 202010207558A CN 113436670 B CN113436670 B CN 113436670B
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- 238000001514 detection method Methods 0.000 title claims abstract description 21
- 230000014759 maintenance of location Effects 0.000 claims abstract description 140
- 238000012360 testing method Methods 0.000 claims abstract description 88
- 238000007619 statistical method Methods 0.000 claims abstract description 21
- 238000007689 inspection Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 8
- 238000012423 maintenance Methods 0.000 description 20
- 235000012431 wafers Nutrition 0.000 description 8
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50016—Marginal testing, e.g. race, voltage or current testing of retention
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56008—Error analysis, representation of errors
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Abstract
A memory detection method and a memory detection system. The memory inspection system includes a test machine and a computer system. The memory detection method comprises the following steps: performing a first data retention time test on the memory chips to obtain first qualified memory chips; performing a second data retention time test on the first qualified memory chip to obtain a second qualified memory chip; and performing a third data retention time test on the second qualified memory chip to obtain a third qualified memory chip. And performing a statistical analysis step on the third qualified memory chips according to the first data maintaining time, the second data maintaining time and the third data maintaining time of each third qualified memory chip to obtain final qualified memory chips. Thus, a memory chip having a variable retention time (Variable Retention Time; VRT) problem can be efficiently detected.
Description
Technical Field
The invention relates to a memory detection method and a memory detection system. And more particularly to a memory detection method and system suitable for variable retention time (Variable Retention Time; VRT) problems.
Background
Dynamic random access memory (Dynamic Random Access Memory, DRAM) stores charge (data) in a capacitor through a transistor. Over time, the data stored in the capacitor may disappear. The DRAM chip has the problem of variable retention time (Variable Retention Time; VRT). Conventionally, the problem of variable retention time of a dynamic random access memory chip is detected by writing data to the dynamic random access memory chip and performing a plurality of tests after a period of time to determine whether the data is lost.
However, even if the DRAM chip is judged to be a normal chip in the first test period, it is possible to judge the chip to have the VRT problem due to the data loss in the second test period. Therefore, it is difficult to efficiently detect a chip having the VRT problem.
Disclosure of Invention
The embodiment of the invention provides a memory detection method and a memory detection system, which can effectively detect a memory chip with VRT problem.
According to an embodiment of the present invention, in the memory inspection method, a first data retention time test is performed on a memory chip to obtain a first qualified memory chip. Then, a second data retention time test is performed on the first qualified memory chip to obtain a second qualified memory chip. And then, performing a third data maintenance time test on the second qualified memory chips to obtain third qualified memory chips, wherein each third qualified memory chip has a first data maintenance time, a second data maintenance time and a third data maintenance time, the first data maintenance time is obtained from the first data maintenance time test, the second data maintenance time is obtained from the second data maintenance time test, and the third data maintenance time is obtained from the third data maintenance time test. Then, a statistical analysis step is performed on each third qualified memory chip according to the first data retention time, the second data retention time and the third data retention time of the third qualified memory chip, so as to obtain at least one final qualified memory chip. In the foregoing statistical analysis step, the data retention time difference of each third qualified memory chip is calculated according to the first data retention time, the second data retention time and the third data retention time of each third qualified memory chip. Then, it is determined whether an absolute value of a data retention time difference value of one of the third qualified memory chips is greater than a preset threshold. And then, if the absolute value of the data maintaining time difference value is larger than a preset threshold value, judging that the third qualified memory chip is unqualified. If the absolute value of the data maintaining time difference value is smaller than or equal to the preset threshold value, the third qualified memory chip is judged to be the final qualified memory chip.
In some embodiments, a first time interval between the first data retention time test and the second data retention time test is greater than or equal to 6 hours, and a second time interval between the second data retention time test and the third data retention time test is greater than or equal to 6 hours.
According to an embodiment of the invention, the memory inspection system includes a test machine and a computer system. The test machine is used for: a first data retention time test is performed on the memory chips to obtain first qualified memory chips. Then, a second data retention time test is performed on the first qualified memory chip to obtain a second qualified memory chip. And then, performing a third data maintenance time test on the second qualified memory chips to obtain third qualified memory chips, wherein each third qualified memory chip has a first data maintenance time, a second data maintenance time and a third data maintenance time, the first data maintenance time is obtained from the first data maintenance time test, the second data maintenance time is obtained from the second data maintenance time test, and the third data maintenance time is obtained from the third data maintenance time test. The computer system is used for carrying out a statistical analysis step on each third qualified memory chip according to the first data maintaining time, the second data maintaining time and the third data maintaining time of each third qualified memory chip so as to obtain at least one final qualified memory chip. In the foregoing statistical analysis step, the data retention time difference of each third qualified memory chip is calculated according to the first data retention time, the second data retention time and the third data retention time of each third qualified memory chip. Then, it is determined whether an absolute value of a data retention time difference value of one of the third qualified memory chips is greater than a preset threshold. And then, if the absolute value of the data maintaining time difference value is larger than a preset threshold value, judging that the third qualified memory chip is unqualified. If the absolute value of the data maintaining time difference value is smaller than or equal to the preset threshold value, the third qualified memory chip is judged to be the final qualified memory chip.
In some embodiments, a first time interval between the first data retention time test and the second data retention time test is greater than or equal to 6 hours, and a second time interval between the second data retention time test and the third data retention time test is greater than or equal to 6 hours.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 illustrates a memory detection system according to an embodiment of the invention.
Fig. 2 is a flow chart of a memory detection method according to an embodiment of the invention.
FIG. 3 is a flow chart illustrating a statistical analysis step according to an embodiment of the present invention.
Fig. 4 shows a flow chart of a statistical analysis step according to an embodiment of the invention.
FIG. 5 shows a flow chart of a statistical analysis step according to an embodiment of the invention.
Fig. 6 is a flow chart of a memory detection method according to an embodiment of the invention.
Wherein reference numerals are as follows:
100: memory detection system
110: test machine
112: wafer with a plurality of wafers
114: probe apparatus
120: computer system
200: memory detection method
210-240: step (a)
342-344: step (a)
344a-344c: step (a)
442-444: step (a)
444a-444c: step (a)
542-548: step (a)
548a-548c: step (a)
600: memory detection method
640: step (a)
Detailed Description
Referring to FIG. 1, a memory inspection system 100 according to an embodiment of the invention is shown. The memory inspection system 100 includes a test station 110 and a computer system 120. The test station 110 is used for testing a plurality of memory chips on the wafer 112 to obtain test data of each memory chip. In an embodiment of the present invention, the memory chips on wafer 112 are dynamic random access memory (Dynamic Random Access Memory, DRAM) chips. The computer system 120 is electrically connected to the testing machine 110 to obtain and analyze the test data of the memory chip.
In the present embodiment, the test tool 110 includes a probe device 114 that applies electrical signals to the memory chips of the wafer 112 and obtains test data of the memory chips. The test data may include, but is not limited to, the location of the memory chip and the data retention time of the memory chip.
Referring to fig. 2, a flow chart of a memory detection method 200 according to an embodiment of the invention is shown. The memory inspection method 200 first proceeds to step 210 to perform a first data retention time test on the memory chips on the wafer 112 to obtain a plurality of first qualified memory chips. In step 210, the test machine 110 measures the data retention time of each memory chip, and then determines whether the memory chip passes the test according to the preset data retention time threshold value, so as to pick out the first qualified memory chip. However, embodiments of the present invention are not limited thereto, and other suitable data retention time testing methods may be applied in step 210.
Next, step 220 is performed to perform a second data retention time test on the first qualified memory chips on the wafer 112 to obtain a plurality of second qualified memory chips. Similarly, in step 220, the test station 110 measures the data retention time of each first qualified memory chip. And then judging whether the first memory chip passes the test according to a preset data maintaining time threshold value so as to select a second qualified memory chip from the first memory chip. However, embodiments of the present invention are not limited thereto, and other suitable data retention time testing methods may be applied in step 220.
Then, step 230 is performed to perform a third data retention time test on the second qualified memory chips on the wafer 112 to obtain a plurality of third qualified memory chips. Similarly, in step 230, the test station 110 measures the data retention time of each second qualified memory chip. And then judging whether the second memory chip passes the test according to a preset data maintaining time threshold value so as to select a third qualified memory chip from the second memory chip. However, embodiments of the present invention are not limited thereto, and other suitable data retention time testing methods may be applied in step 230.
In an embodiment of the present invention, the time interval between the first data retention time test and the second data retention time test is at least 6 hours, and the time interval between the second data retention time test and the third data retention time test is also at least 6 hours. For example, the second data retention time test may be performed after at least 6 hours have elapsed after the first data retention time test is completed. For another example, the third data retention time test may be performed after at least 6 hours have elapsed after the second data retention time test is completed. In this embodiment, the time interval between the first data retention time test and the second data retention time test is 24 hours, and the time interval between the second data retention time test and the third data retention time test is 24 hours.
Next, step 240 is performed to perform a statistical analysis on the third qualified memory chip by using the computer system 120 to obtain a final qualified memory chip. In an embodiment of the present invention, step 240 is a statistical analysis step of the third qualified memory chip according to the first data retention time, the second data retention time, and the third data retention time of the third qualified memory chip to obtain at least one final qualified memory chip therefrom.
Referring to fig. 3, a flow chart of step 240 according to an embodiment of the invention is shown. In this embodiment, step 240 uses the difference in data retention time to perform statistical analysis. As shown in fig. 3, step 342 is performed first to calculate a data retention time difference value of each third qualified memory chip according to the first data retention time, the second data retention time and the third data retention time of each third qualified memory chip. For example, calculating a difference between the first data retention time and the second data retention time; calculating a difference between the second data maintaining time and the third data maintaining time; and calculating a difference between the first data maintaining time and the third data maintaining time. Thus, step 342 may obtain three data retention time differences for each third qualified memory chip.
Next, step 344 is performed to determine whether the third qualified memory chip to be analyzed can be the final qualified memory chip. In step 344, first, step 344a is performed to determine whether the absolute value of the data retention time difference of the third qualified memory chip is greater than a preset threshold. In the present embodiment, the preset threshold is 30 milliseconds (ms), but the embodiment of the present invention is not limited thereto. If the data retention time difference of the third qualified memory chip is not greater than the predetermined threshold, step 344b is performed to determine the third qualified memory chip as the final qualified memory chip. If the data retention time difference of the third qualified memory chip is greater than the predetermined threshold, step 344c is performed to determine that the third qualified memory chip is a failed chip.
In the present embodiment, step 344a is to determine whether the three data retention time differences of the third qualified memory chip to be analyzed are all greater than a predetermined threshold. However, embodiments of the present invention are not limited thereto.
In another embodiment of the present invention, step 344a determines whether one of the three data retention time differences is greater than a preset threshold. If the determination result is no, step 344b is performed to determine that the third qualified memory chip is the final qualified memory chip. If the determination result is yes, go to step 344c to determine that the third acceptable memory chip is an unacceptable chip.
In yet another embodiment of the present invention, step 344a determines whether two of the three data retention time differences are greater than a predetermined threshold. If the determination result is no, step 344b is performed to determine that the third qualified memory chip is the final qualified memory chip. If the determination result is yes, go to step 344c to determine that the third acceptable memory chip is an unacceptable chip.
Referring to fig. 4, a flow chart of step 240 according to an embodiment of the invention is shown. In this embodiment, step 240 uses the root mean square value of the data retention time to perform the statistical analysis. As shown in fig. 4, step 442 is first performed to calculate a Root Mean Square (RMS) value of each third qualified memory chip according to the first data retention time, the second data retention time, and the third data retention time of each third qualified memory chip. The calculation formula of the square root value of the third qualified memory chip is as follows:
wherein R is the root of the square of a third qualified memory chip, and D 1 、D 2 、D 3 The three data retention time differences for this third pass memory chip, respectively.
Then, step 444 is performed to determine whether the third qualified memory chip to be analyzed can be the final qualified memory chip. In step 444, first, step 444a is performed to determine whether the root-mean-square value of the third qualified memory chip is greater than a predetermined threshold. In the present embodiment, the preset threshold is 45, but embodiments of the present invention are not limited thereto. If the root-mean-square value of the third qualified memory chip is not greater than the predetermined threshold, step 444b is performed to determine the third qualified memory chip as the final qualified memory chip. If the root-mean-square value of the third qualified memory chip is greater than the predetermined threshold, step 444c is performed to determine that the third qualified memory chip is a failed chip.
Referring to fig. 5, a flow chart of step 240 according to an embodiment of the invention is shown. In this embodiment, step 240 performs a statistical analysis using the AR value of the data retention time, wherein the AR value is a ratio of the average value to the root mean square value of the data retention time. As shown in fig. 5, step 542 is first performed to calculate a data retention time average value of each third qualified memory chip according to the first data retention time, the second data retention time and the third data retention time of each third qualified memory chip. Next, step 544 is performed to calculate the root-mean-square value of each third qualified memory chip according to the first data retention time, the second data retention time and the third data retention time of each third qualified memory chip. Step 544 is similar to step 442 described above and is not described herein.
Then, step 546 is performed to calculate A Ratio (AR) of the data retention time average value to the root mean square value of each third qualified memory chip, wherein the AR value is calculated as follows:
wherein T is 1 、T 2 、T 3 The third qualified memory chip is respectively tested for the data maintaining time in the first data maintaining time test, the second data maintaining time test and the third data maintaining time test.
Next, step 548 is performed to determine whether the third qualified memory chip to be analyzed can be the final qualified memory chip. In step 548, first, step 548a is performed to determine whether the AR value of the third qualified memory chip is greater than a predetermined threshold. In the present embodiment, the preset threshold is 3, but the embodiment of the invention is not limited thereto. If the AR value of the third qualified memory chip is not greater than the predetermined threshold, step 548b is performed to determine the third qualified memory chip as the final qualified memory chip. If the AR value of the third qualified memory chip is greater than the predetermined threshold, step 548c is performed to determine that the third qualified memory chip is a failed chip.
Referring to fig. 6, a flow chart of a memory detection method 600 according to an embodiment of the invention is shown. The memory inspection method 600 is similar to the memory inspection method 200 described above, except that the step 640 of the memory inspection method 600 integrates a plurality of statistical analysis steps to analyze the third qualified memory chip. For example, step 640 may integrate the embodiments of fig. 3 and 4 (e.g., steps 344 and 444) to analyze the third qualified memory chip. Specifically, if a third qualified memory chip is determined by one of steps 344 and 444, then the third qualified memory chip is determined to be the final qualified memory chip. For another example, step 640 may integrate the embodiments of fig. 3, 4, and 5 (e.g., steps 344, 444, and 548) to analyze the third qualified memory chip. Specifically, if a third qualified memory chip is determined by one of steps 344, 444 and 548, then the third qualified memory chip is determined to be the final qualified memory chip.
As can be seen from the above description, the memory inspection system and the memory inspection method according to the embodiments of the invention perform statistical analysis on the memory chips passing the data retention time test multiple times, so that the memory chips having the VRT problem can be efficiently inspected. In addition, although the statistical analysis step of the above embodiment uses the data retention time difference, root mean square and AR values for analysis, the embodiment of the present invention is not limited thereto. Other suitable statistical analysis methods may also be suitable for embodiments of the present invention.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather is capable of modification and variation without departing from the spirit and scope of the present invention.
Claims (4)
1. A memory detection method, comprising:
performing a first data retention time test on the plurality of memory chips to obtain a plurality of first qualified memory chips;
performing a second data retention time test on the first qualified memory chips to obtain a plurality of second qualified memory chips;
performing a third data retention time test on the second qualified memory chips to obtain a plurality of third qualified memory chips, wherein each third qualified memory chip has a first data retention time, a second data retention time and a third data retention time, the first data retention time is obtained from the first data retention time test, the second data retention time is obtained from the second data retention time test, and the third data retention time is obtained from the third data retention time test; and
performing a statistical analysis step on the third qualified memory chips according to the first data retention time, the second data retention time and the third data retention time of each third qualified memory chip to obtain at least one final qualified memory chip;
wherein the statistical analysis step comprises:
calculating a data retention time difference of each third qualified memory chip according to the first data retention time, the second data retention time and the third data retention time of each third qualified memory chip; and
judging whether the absolute value of the data maintaining time difference value of one of the third qualified memory chips is larger than a preset threshold value;
if the absolute value of the data maintaining time difference value is larger than the preset threshold value, judging that the third qualified memory chip is unqualified;
if the absolute value of the data retention time difference is less than or equal to the preset threshold, determining the one of the third qualified memory chips as the at least one final qualified memory chip.
2. The method of claim 1, wherein a first time interval between the first data retention time test and the second data retention time test is greater than or equal to 6 hours, and a second time interval between the second data retention time test and the third data retention time test is greater than or equal to 6 hours.
3. A memory inspection system, comprising:
a test machine for:
performing a first data retention time test on the plurality of memory chips to obtain a plurality of first qualified memory chips;
performing a second data retention time test on the first qualified memory chips to obtain a plurality of second qualified memory chips; and
performing a third data retention time test on the second qualified memory chips to obtain a plurality of third qualified memory chips, wherein each third qualified memory chip has a first data retention time, a second data retention time and a third data retention time, the first data retention time is obtained from the first data retention time test, the second data retention time is obtained from the second data retention time test, and the third data retention time is obtained from the third data retention time test; and
a computer system for performing a statistical analysis step on each of the third qualified memory chips according to the first data retention time, the second data retention time and the third data retention time to obtain at least one final qualified memory chip;
wherein the statistical analysis step comprises:
calculating a data retention time difference of each third qualified memory chip according to the first data retention time, the second data retention time and the third data retention time of each third qualified memory chip; and
judging whether the absolute value of the data maintaining time difference value of one of the third qualified memory chips is larger than a preset threshold value;
if the absolute value of the data maintaining time difference value is larger than the preset threshold value, judging that the third qualified memory chip is unqualified;
if the absolute value of the data retention time difference is less than or equal to the preset threshold, determining the one of the third qualified memory chips as the at least one final qualified memory chip.
4. The memory inspection system of claim 3, wherein a first time interval between the first data retention time test and the second data retention time test is greater than or equal to 6 hours and a second time interval between the second data retention time test and the third data retention time test is greater than or equal to 6 hours.
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