CN113436584A

CN113436584A - Scanning control circuit and driving method thereof, shift register and display device

Info

Publication number: CN113436584A
Application number: CN202110696140.7A
Authority: CN
Inventors: 张蒙蒙; 周星耀; 李玥; 杨帅
Original assignee: Shanghai Tianma AM OLED Co Ltd
Current assignee: Wuhan Tianma Microelectronics Co Ltd
Priority date: 2021-06-23
Filing date: 2021-06-23
Publication date: 2021-09-24
Anticipated expiration: 2041-06-23
Also published as: CN113436584B

Abstract

The embodiment of the invention provides a scanning control circuit, a driving method thereof, a shift register and a display device, relates to the technical field of display and improves the stability of the circuit. The scan control circuit includes: a first control module transferring a voltage to the first node and the fourth node in response to a voltage of the first clock signal and a voltage of the third clock signal, and transferring a voltage to the third node in response to the third clock signal; a pull-down module to transmit a voltage to the first node in response to a voltage of the third node and a voltage of the first node; a second control module transmitting a voltage to the third node in response to a voltage of the fourth node; a third control module transmitting a voltage to the second node in response to a voltage of the third node, a voltage of the second clock signal, and a voltage of the first node; and an output module outputting a scan signal to the gate line in response to the voltage of the first node and the voltage of the second node.

Description

Scanning control circuit and driving method thereof, shift register and display device

[ technical field ] A method for producing a semiconductor device

The invention relates to the technical field of display, in particular to a scanning control circuit, a driving method thereof, a shift register and a display device.

[ background of the invention ]

The display device is provided with a plurality of cascaded scanning control circuits, and the scanning control circuits are used for outputting scanning signals to the grid lines so as to drive the display panel to normally display pictures. It can be understood that the scan control circuit is composed of a plurality of transistors and a plurality of nodes, and during the operation of the scan control circuit, the potentials of the nodes will change, so that the voltage difference between the two ends of the transistors will change accordingly.

However, based on the specific structure of the existing scan control circuit, in the process of node potential change, the voltage difference between two ends of the transistor is too large, which may affect the stability of the transistor, and in a serious case, may also affect the working state of the whole scan control circuit, thereby causing the scan control circuit to fail to output correct scan signals.

[ summary of the invention ]

In view of this, embodiments of the present invention provide a scan control circuit, a driving method thereof, a shift register, and a display device, so as to improve the working stability of the scan control circuit.

In one aspect, an embodiment of the present invention provides a scan control circuit, including:

a first control module electrically connected to a shift control signal line, a first clock signal line, a third clock signal line, a first fixed potential signal line, a first node, a third node, and a fourth node, the first control module transmitting a node voltage to the first node and the fourth node, respectively, in response to a voltage of a first clock signal and a voltage of a third clock signal, and transmitting a node voltage to the third node in response to a voltage of a third clock signal;

a pull-down module electrically connected to a second fixed potential signal line, a second clock signal line, the third node, and the first node, the pull-down module transmitting a node voltage to the first node in response to a voltage of the third node and a voltage of the first node;

a second control module electrically connected to the third clock signal line, the third node, and the fourth node, the second control module transmitting a node voltage to the third node in response to a voltage of the fourth node;

a third control module electrically connected to the second clock signal line, the first node, the second node, and the third node, the third control module transmitting a node voltage to the second node in response to a voltage of the third node, a voltage of a second clock signal, and a voltage of the first node;

an output module electrically connected to the first clock signal line, the first fixed potential signal line, a gate line, the first node, and the second node, the output module outputting a scan signal to the gate line in response to a voltage of the first node and a voltage of the second node.

In another aspect, an embodiment of the present invention provides a driving method for a scan control circuit, where an operation process of the scan control circuit includes a first period, a second period, a third period, and a fourth period, and the driving method includes:

in the first period, the first control module transmits a high level provided by the shift control signal line to the first node and the fourth node in response to a low level provided by the first clock signal line and a low level provided by the third clock signal line, and transmits a low level provided by the first fixed potential signal line to the third node in response to a low level provided by the third clock signal line, the third control module transmits a low level provided by the second clock signal line to the second node in response to a low level of the third node and a low level provided by the second clock signal line, and the output module transmits a low level provided by the first clock signal line to the gate line in response to a low level of the second node;

in the second period, the third control module transmits the low level provided by the second clock signal line to the second node in response to the low level of the third node and the low level provided by the second clock signal line, and the output module transmits the high level provided by the first clock signal line to the gate line in response to the low level of the second node;

in the third period, the first control module transmits a low level provided by the shift control signal line to the first node and the fourth node in response to a low level provided by the first clock signal line and a low level provided by the third clock signal line, and transmits a low level provided by the first fixed potential signal line to a third node in response to a low level provided by the third clock signal line, the second control module transmits a low level provided by the third clock signal line to a third node in response to a low level of the fourth node, the third control module transmits a signal provided by the first signal line to the second node in response to a low level of the first node, the pull-down module pulls down a potential of the first node in response to a low level of the third node and a low level of the first node, the output module transmits a low level provided by the first fixed potential signal line to the gate line in response to a low level of the first node;

in the fourth period, the pull-down module continuously pulls down the potential of the first node in response to the low level of the third node and the low level of the first node, and the output module continuously transmits the low level to the gate line.

In another aspect, an embodiment of the present invention provides a shift register, which includes a plurality of cascaded scan control circuits.

In another aspect, an embodiment of the present invention provides a display device, including:

the display panel comprises a plurality of grid lines and a plurality of data lines, wherein the grid lines and the data lines are crossed to define a plurality of sub-pixels;

in the shift register, the scan control circuit in the shift register is electrically connected to the gate line.

One of the above technical solutions has the following beneficial effects:

in the related art, a second control module in the scan control circuit is electrically connected to the first node, and the second control module transmits a voltage to a third node in response to a voltage of the first node. In order to enable the output module to stably output the low level provided by the first fixed potential signal line in a specific time period during the working process of the scanning control circuit, the pull-down module pulls down the voltage of the first node in a partial time period, and the pulled-down potential is far lower than the fixed low level of the first fixed potential signal line, so that the ultra-low potential of the first node can influence the voltage difference between two ends of the transistor in the second control module. Particularly, when the circuit is subjected to high voltage application to reduce leakage current in the circuit, the voltage difference between two ends of the transistor in the second control module is larger, so that the voltage resistance of the transistor is poor, the stability of the transistor is influenced to a great extent, and further the working state of the transistor is wrong.

In the embodiment of the invention, the second control module in the scan control circuit is electrically connected to the fourth node, and the second control module transmits a voltage to the third node in response to the voltage of the fourth node. Because the fourth node is not electrically connected with the pull-down module, the voltage of the fourth node is not influenced by the pull-down module, the fourth node does not have the condition of ultra-low potential, so that the condition that the pressure difference between two ends of a transistor in the second control module is overlarge is avoided, the reliability of the working state of the transistor is improved, the reliability of the whole scanning control circuit is improved, the scanning control circuit can output accurate scanning signals to a grid line, and the display panel is ensured to normally emit light.

In addition, the voltage of the fourth node is derived from the signal provided by the shift control signal line, and the signal provided by the shift control signal line is at a high level in a certain period of time, and is at a low level in other periods of time, so that the potential of the fourth node is more stable compared with other nodes, and frequent jump cannot occur. Compared with the second control module electrically connected with other nodes, the second control module is electrically connected with the fourth node, so that the risk of overlarge differential pressure between two ends of the transistor can be reduced to a greater extent.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a scan control circuit according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the invention;

FIG. 3 is a timing diagram of a pixel circuit according to an embodiment of the present invention;

FIG. 4 is a timing diagram of a scan control circuit according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a scan control circuit according to an embodiment of the present invention;

fig. 6 is a schematic structural diagram of a scan control circuit according to another embodiment of the present invention;

FIG. 7 is a schematic diagram of another scan control circuit according to an embodiment of the present invention;

FIG. 8 is another timing diagram of the scan control circuit according to the embodiment of the present invention;

FIG. 9 is a schematic diagram of another structure of a scan control circuit according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of another scan control circuit according to an embodiment of the present invention;

FIG. 11 is a schematic diagram of another structure of a scan control circuit according to an embodiment of the present invention;

FIG. 12 is a diagram illustrating a shift register according to an embodiment of the present invention;

fig. 13 is a schematic structural diagram of a display device according to an embodiment of the present invention.

[ detailed description ] embodiments

For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.

It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.

It should be understood that although the terms first, second, third, etc. may be used to describe control modules in embodiments of the present invention, these control modules should not be limited to these terms. These terms are only used to distinguish the control modules from each other. For example, a first control module may also be referred to as a second control module, and similarly, a second control module may also be referred to as a first control module without departing from the scope of embodiments of the present invention.

An embodiment of the present invention provides a scan control circuit, as shown in fig. 1, fig. 1 is a schematic structural diagram of the scan control circuit provided in the embodiment of the present invention, and the scan control circuit includes a first control module 1, a pull-down module 2, a second control module 3, a third control module 4, and an output module 5.

The first control module 1 is electrically connected to the shift control signal line IN, the first clock signal line CK1, the third clock signal line CK3, the first fixed potential signal line VGL, the first node N1, the third node N3, and the fourth node N4, and the first control module 1 transmits a node voltage to the first node N1 and the fourth node N4, respectively, IN response to a voltage of the first clock signal and a voltage of the third clock signal, and transmits a node voltage to the third node N3 IN response to a voltage of the third clock signal.

The pull-down module 2 is electrically connected to the second fixed potential signal line VGH, the second clock signal line CK2, the third node N3 and the first node N1, and the pull-down module 2 transmits a node voltage to the first node N1 to pull down the voltage of the first node N1 in response to the voltage of the third node N3 and the voltage of the first node N1.

The second control module 3 is electrically connected to the third clock signal line CK3, the third node N3, and the fourth node N4, and the second control module 3 transmits a node voltage to the third node N3 in response to the voltage of the fourth node N4.

The third control module 4 is electrically connected to the second clock signal line CK2, the first signal line CL1, the first node N1, the second node N2, and the third node N3, and the third control module 4 transmits a node voltage to the second node N2 in response to the voltage of the third node N3, the voltage of the second clock signal, and the voltage of the first node N1.

The output block 5 is electrically connected to the first clock signal line CK1, the first fixed potential signal line VGL, the gate line Scan, the first node N1, and the second node N2, and the output block 5 outputs a Scan signal to the gate line Scan in response to the voltage of the first node N1 and the voltage of the second node N2.

It should be noted that the two structures electrically connected as defined in the embodiment of the present invention means that the two structures are directly connected, for example, that "the output module 5 is electrically connected to the first clock signal line CK1, the first fixed potential signal line VGL, the gate line Scan, the first node N1, and the second node N2" means that "the output module 5 is directly connected to the first clock signal line CK1, the first fixed potential signal line VGL, the gate line Scan, the first node N1, and the second node N2".

In the above-described configuration of the Scan control circuit, the output block 5 outputs the Scan signal to the gate line Scan in response to the voltage of the first node N1 and the voltage of the second node N2, that is, the voltages of the first node N1 and the second node N2 directly affect the signal output of the output block 5. The voltage at the first node N1 is mainly controlled by the first control module 1, and the voltage at the second node N2 is mainly controlled by the third control module 4. For the third control module 4, the voltage transmission process from the third control module 4 to the second node N2 is affected by the voltage of the third node N3, and the voltage of the third node N3 is affected by the second control module 3, so that the stability of the operating state of the second control module 3 directly affects the reliability of the voltage transmission from the third control module 4 to the second node N2, and further indirectly affects the reliability of the output module 5 outputting the scan signal.

In the embodiment of the invention, the second control module 3 in the scan control circuit is electrically connected to the fourth node N4, and the second control module 3 transmits a voltage to the third node N3 in response to the voltage at the fourth node N4. Because the fourth node N4 is not electrically connected to the pull-down module 2, the voltage at the fourth node N4 is not affected by the pull-down module 2, and the fourth node N4 does not have an ultra-low potential, so that an excessive voltage difference between two ends of a transistor in the second control module 3 is avoided, the reliability of the working state of the transistor is improved, the reliability of the whole scanning control circuit is improved, the scanning control circuit can output accurate scanning signals to the gate line Scan, and the display panel can be ensured to normally emit light.

IN addition, the voltage at the fourth node N4 is derived from the signal provided by the shift control signal line IN, and the signal provided by the shift control signal line IN is at a low level for the rest of the time period except for a high level for a certain time period, so that the potential at the fourth node N4 is more stable than that at other nodes, and frequent transitions do not occur. Therefore, compared with electrically connecting the second control module 3 to other nodes, the second control module 3 and the fourth node N4 are electrically connected according to the embodiment of the present invention, which can reduce the risk of an excessive voltage difference between two ends of the transistor.

It is understood that the display panel includes a plurality of sub-pixels including pixel circuits and organic light emitting diodes electrically connected. The pixel circuit is electrically connected with the gate line Scan, the scanning control line further transmits a scanning signal output by the gate line Scan to the pixel circuit, and the pixel circuit is driven to transmit a driving current to the organic light emitting diode, so that the organic light emitting diode emits light under the action of the driving current.

In order to make the display panel have both strong driving capability and Low power performance, so as to be suitable for both high frequency display and Low frequency display, the pixel circuit may be a Low Temperature Polysilicon (LTPO) circuit, and in this case, the pixel circuit includes two types of transistors, i.e., Low Temperature Polysilicon (LTPS) and Indium Gallium Zinc Oxide (IGZO). The scan control circuit in the embodiment of the invention is specifically configured to output a scan signal with a high active level, so as to be suitable for the pixel circuit.

Specifically, as shown in fig. 2, fig. 2 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, where the pixel circuit includes a capacitor C, a first switch transistor T1-a second switch transistor T7, where the fifth switch transistor T4 and the fourth switch transistor T4 are N-type transistors, and the first switch transistor T1, the second switch transistor T2, the third switch transistor T3, the sixth switch transistor T6, and the seventh switch transistor T7 are P-type transistors.

Based on the above-described structure, in conjunction with the timing chart shown in fig. 3, one driving cycle of the pixel circuit includes the initialization period t1 ', the data writing period t2 ', and the light emission control period t3 '.

In the initialization period T1', the first gate line Scan1 supplies a high level, the second gate line Scan2 supplies a low level, the third gate line Scan3 supplies a high level, the emission control signal line Emit supplies a high level, and the reset signal supplied from the reset signal line Vref resets the control electrode of the third switching transistor T3 via the turned-on fifth switching transistor T5.

In the Data writing period T2', the first gate line Scan1 supplies a low level, the second gate line Scan2 supplies a high level, the third gate line Scan3 supplies a low level, the emission control signal line Emit supplies a high level, and the Data signal supplied from the Data line Data is written to the control electrode of the third switching transistor T3 through the turned-on second switching transistor T2, third switching transistor T3, and fourth switching transistor T4; meanwhile, the reset signal provided by the reset signal line Vref is transmitted to the anode of the organic light emitting diode D through the turned-on seventh switching tube T7, and resets the anode of the organic light emitting diode D.

In the emission control period T3', the first gate line Scan1 supplies a low level, the second gate line Scan2 supplies a low level, the third gate line Scan3 supplies a high level, the emission control signal line Emit supplies a low level, the first switching transistor T1 and the sixth switching transistor T6 are turned on, and the light emitting diode D emits light by the driving current converted by the data signal and the power signal supplied from the power signal line PVDD.

Based on this, the Scan control circuit in the embodiment of the present invention is configured to output the Scan signal with the active level being the high level to the first gate line Scan1 and the second gate line Scan 2. Specifically, as shown in fig. 4, fig. 4 is a timing chart corresponding to the scan control circuit provided in the embodiment of the present invention, and the working process of the scan control circuit includes a first time period t1, a second time period t2, a third time period t3, and a fourth time period t 4.

IN the first period t1, the first control module 1 transmits the high level provided by the shift control signal line IN to the first node N1 and the fourth node N4 IN response to the low level provided by the first clock signal line CK1 and the low level provided by the third clock signal line CK3, and transmits the low level provided by the first fixed potential signal line VGL to the third node N3 IN response to the low level provided by the third clock signal line CK3, and then the third control module 4 transmits the low level provided by the second clock signal line CK2 to the second node N2 IN response to the low level of the third node N3 and the low level provided by the second clock signal line CK2, and the output module 5 transmits the low level provided by the first clock signal line CK1 to the Scan line IN response to the low level of the second node N2, at which the Scan control circuit outputs the inactive level (low level) to the Scan line.

In the second period t2, the third control module 4 transmits the low level supplied from the second clock signal line CK2 to the second node N2 in response to the low level of the third node N3 and the low level supplied from the second clock signal line CK2, and the output module 5 transmits the high level supplied from the first clock signal line CK1 to the gate line Scan in response to the low level of the second node N2, at which time the Scan control circuit continues to output the active level (high level) to the gate line Scan.

IN a third period t3, the first control module 1 transfers the low level provided by the shift control signal line IN to the first node N1 and the fourth node N4 IN response to the low level provided by the first clock signal line CK1 and the low level provided by the third clock signal line CK3, and transfers the low level provided by the first fixed potential signal line VGL to the third node N3 IN response to the low level provided by the third clock signal line CK3, the second control module 3 transfers the low level provided by the third clock signal line CK3 to the third node N3 IN response to the low level of the fourth node N4, the third control module 4 transfers the signal provided by the first signal line CL1 to the second node N2 IN response to the low level of the first node N1, the pull-down module 2 outputs the low level of the first node N1 IN response to the low level of the third node N3 and the low level of the first node N1, the low level supplied from the first fixed potential signal line VGL is transmitted to the gate line Scan, and at this time, the Scan control circuit outputs an inactive level (low level) to the gate line Scan.

In the fourth period t4, the pull-down module 2 continuously pulls down the potential of the first node N1 in response to the low level of the third node N3 and the low level of the first node N1, and the output module 5 continuously transmits the low level to the gate line Scan, at which time the Scan control circuit continuously outputs the inactive level (low level) to the gate line Scan.

In an implementation manner, as shown in fig. 5, fig. 5 is another schematic structural diagram of the scan control circuit provided in the embodiment of the invention, and the first control module 1 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4.

A control electrode of the first transistor M1 is electrically connected to the first clock signal line CK1, and a first electrode of the first transistor M1 is electrically connected to the shift control signal line IN; a control electrode of the second transistor M2 is electrically connected to the third clock signal line CK3, a first electrode of the second transistor M2 is electrically connected to a second electrode of the first transistor M1, and a second electrode of the second transistor M2 is electrically connected to the fourth node N4; a control electrode of the third transistor M3 is electrically connected to the third clock signal line CK3, a first electrode of the third transistor M3 is electrically connected to a second electrode of the first transistor M1, and a second electrode of the third transistor M3 is electrically connected to the first node N1; a control electrode of the fourth transistor M4 is electrically connected to the third clock signal line CK3, a first electrode of the fourth transistor M4 is electrically connected to the first fixed potential signal line VGL, and a second electrode of the fourth transistor M4 is electrically connected to the third node N3.

Based on the above-described structure, IN conjunction with fig. 4, at the first period t1, the first transistor M1 is turned on by the low level supplied from the first clock signal line CK1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are turned on by the low level supplied from the third clock signal line CK3, the high level supplied from the shift control signal line IN is transmitted to the fourth node N4 via the turned-on first transistor M1 and the turned-on third transistor M3, and to the first node N1 via the turned-on first transistor M1 and the turned-on third transistor M3, respectively, and the low level supplied from the first fixed potential signal line VGL is transmitted to the third node N3 via the turned-on fourth transistor M4.

IN the third period t3, the first transistor M1 is turned on by a low level supplied from the first clock signal line CK1, the second, third and fourth transistors M2, M3 and M4 are turned on by a low level supplied from the third clock signal line CK3, the low level supplied from the shift control signal line IN is transmitted to the fourth node N4 via the turned-on first and second transistors M1 and M2 and to the first node N1 via the turned-on first and third transistors M1 and M3, respectively, and the low level supplied from the first fixed potential signal line VGL is transmitted to the third node N3 via the turned-on fourth transistor M4.

In one embodiment, referring again to fig. 5, the pull-down module 2 includes a fifth transistor M5, a sixth transistor M6, and a first capacitor C1.

A control electrode of the fifth transistor M5 is electrically connected to the third node N3, a first electrode of the fifth transistor M5 is electrically connected to the second fixed-potential signal line VGH, and a second electrode of the fifth transistor M5 is electrically connected to the fifth node N5; a control electrode of the sixth transistor M6 is electrically connected to the first node N1, a first electrode of the sixth transistor M6 is electrically connected to the second clock signal line CK2, and a second electrode of the sixth transistor M6 is electrically connected to the fifth node N5; the first plate of the first capacitor C1 is electrically connected to the fifth node N5, and the second plate of the first capacitor C1 is electrically connected to the first node N1.

Based on the above structure, with reference to fig. 4, in the third period t3, the sixth transistor M6 is turned on by the low level of the first node N1, the second clock signal provided by the second clock signal line CK2 is transmitted to the fifth node N5 through the turned-on sixth transistor M6, when the second clock signal jumps from the high level to the level in the third period t3, the potential of the first plate (the fifth node N5) of the first capacitor C1 is pulled down, and based on the capacitance characteristic, the potential of the second plate (the first node N1) of the first capacitor C1 is also pulled down, so that the output module 5 outputs the low level provided by the first fixed potential signal line VGL to the gate line Scan more stably under the action of the lower potential of the first node N1, thereby improving the operation reliability of the Scan control circuit.

In one embodiment, referring to fig. 5 again, the second control module 3 includes a seventh transistor M7, a control electrode of the seventh transistor M7 is electrically connected to the fourth node N4, a first electrode of the seventh transistor M7 is electrically connected to the third clock signal line CK3, and a second electrode of the seventh transistor M7 is electrically connected to the third node N3.

Based on the above-described structure, in conjunction with fig. 4, in the third period t2, the seventh transistor M7 is turned on by the low level of the fourth node N4, transmitting the low level supplied from the third clock signal line CK3 to the third node N3.

It should be noted that, in the prior art, a control electrode of the transistor in the second control module is electrically connected to the first node N1, and in a third time period t3, in order to ensure that the transistor in the output module 5 controlled by the voltage of the first node N1 is completely turned on, so that the output module 5 continuously and stably outputs a low level (inactive level), in this time period, the pull-down module 2 is used to pull down the potential of the first node N1, and the pulled-down potential is much smaller than the low level provided by the first potential signal line VGL, which causes that, when the third node N3 is at a high level in this time period, the voltage difference between the third node N3 and the first node N1 having an ultra-low potential is very large, which further causes that the voltage difference between two ends of the transistor in the second control module is very large, and the operating state of the transistor is unstable.

In the embodiment of the present invention, the gate of the seventh transistor M7 in the second control module 3 is electrically connected to the fourth node N4, and the potential of the fourth node N4 is not pulled down by the pull-down module 2, so that the voltage difference between the third node N3 and the fourth node N4 is inevitably smaller than the voltage difference between the third node N3 and the first node N1 having the ultra-low potential in the prior art in the third time period t3, that is, compared with the prior art, the voltage difference between the gate and the second node of the seventh transistor M7 in the embodiment of the present invention is smaller, and the voltage withstanding property and stability of the seventh transistor M7 are better.

IN addition, it should be noted that, IN the embodiment of the present invention, two transistors, namely, the first transistor M1 and the second transistor M2, are connected IN series between the fourth node N4 and the shift control signal line IN, and the first transistor M1 and the second transistor M2 are respectively driven by the first clock signal line CK1 and the third clock signal line CK3, so that the signal provided by the shift control signal line IN can be transmitted to the fourth node N4 only when the first transistor M1 and the second transistor M2 are simultaneously turned on.

Specifically, referring to fig. 4, IN the period t01, the first clock signal line CK1 and the third clock signal line CK3 both provide a low level, at which time the first transistor M1 and the second transistor M2 are both turned on, and the high level provided by the shift control signal line IN is transmitted to the fourth node N4, and IN the later longer period t02, the first transistor M1 and the second transistor M2 are not turned on at the same time, and therefore, the signal of the shift control signal line IN is not transmitted to the fourth node N4 immediately after the signal is hopped low, but the low level after the hopping is transmitted to the fourth node N4 after the first transistor M1 and the second transistor M2 are turned on at the same time after the period t02 ends. Therefore, the fourth node N4 maintains a stable high level for the entire period t02, i.e., the gate of the seventh transistor M7 is continuously set high for the partial period. Since the first pole of the seventh transistor M7 is also kept high during the whole time period t02, the voltage difference between the control pole and the first pole of the seventh transistor M7 is small, further reducing the risk of a large voltage difference across the seventh transistor.

In an embodiment, referring to fig. 5 again, the scan control circuit further includes a second capacitor C2, a first plate of the second capacitor C2 is electrically connected to the second fixed-potential signal line VGH, and a second plate of the second capacitor C2 is electrically connected to the fourth node N4, so as to stabilize the potential of the fourth node N4 and further improve the stability of the operating state of the second control module 3.

In one embodiment, referring to fig. 5 again, the third control module 4 includes a third capacitor C3, an eighth transistor M8, a ninth transistor M9 and a tenth transistor M10.

The first plate of the third capacitor C3 is electrically connected with the third node N3; a control electrode of the eighth transistor M8 is electrically connected to the third node N3, a first electrode of the eighth transistor M8 is electrically connected to the second clock signal line CK2, and a second electrode of the eighth transistor M8 is electrically connected to the second plate of the third capacitor C3; a control electrode of the ninth transistor M9 is electrically connected to the second clock signal line CK2, a first electrode of the ninth transistor M9 is electrically connected to the second electrode of the third capacitor C3, and a second electrode of the ninth transistor M9 is electrically connected to the second node N2; a control electrode of the tenth transistor M10 is electrically connected to the first node N1, a first electrode of the tenth transistor M10 is electrically connected to the first signal line CL1, and a second electrode of the tenth transistor M10 is electrically connected to the second node N2.

Based on the above-described structure, in conjunction with fig. 4, during the first period t1, the eighth transistor M8 is turned on by the low level of the third node N3, the ninth transistor M9 is turned on by the low level supplied from the second clock signal line CK2, and the low level supplied from the second clock signal line CK2 is transmitted to the second node N2 via the turned-on eighth transistor M8 and the ninth transistor M9.

In the second period t2, the eighth transistor M8 is turned on by a low level of the third node N3, the ninth transistor M9 is turned on by a low level provided from the second clock signal line CK2, and the low level provided from the second clock signal line CK2 is transmitted to the second node N2 via the turned-on eighth transistor M8 and the ninth transistor M9.

In the third period t3, the tenth transistor M10 is turned on by the low level of the first node N1, and the signal provided from the first signal line CL1 is transmitted to the second node N2 via the turned-on tenth transistor M10.

In one embodiment, referring to fig. 5 again, the scan control circuit further includes a fourth capacitor C4, a first plate of the fourth capacitor C4 is electrically connected to the first clock signal line CK1, and a second plate of the fourth capacitor C4 is electrically connected to the second node N2. In the second time period t2, the signal provided by the first clock signal line CK1 jumps from the high level to the low level, the potential of the first plate of the fourth capacitor C4 is pulled low, and based on the capacitance characteristics, the potential of the second plate (the second node N2) of the fourth capacitor C4 is also pulled low, so as to increase the driving capability of the potential of the second node N2 to the output module 5, so that the level output by the output module 5 at that time jumps from the high level to the low level immediately, thereby ensuring that the output module 5 continuously and stably outputs the low level (the inactive level) after outputting the high level (the active level), so as to ensure the normal operation of the pixel circuit.

In one embodiment, the output module 5 includes an eleventh transistor M11 and a twelfth transistor M12. A control electrode of the eleventh transistor M11 is electrically connected to the second node N2, a first electrode of the eleventh transistor M11 is electrically connected to the first clock signal, and a second electrode of the eleventh transistor M11 is electrically connected to the gate line Scan; a control electrode of the twelfth transistor M12 is electrically connected to the first node N1, a first electrode of the twelfth transistor M12 is electrically connected to the first fixed potential signal line VGL, and a second electrode of the twelfth transistor M12 is electrically connected to the gate line Scan.

Based on the above structure, in conjunction with fig. 4, during the first period t1, the eleventh transistor M11 is turned on by the low level of the second node N2 to transmit the low level supplied from the first clock signal line CK1 to the gate line Scan; in the second period t2, the eleventh transistor M11 is turned on by the low level of the second node N2, transmitting the high level supplied from the first clock signal line CK1 to the gate line Scan; in the third period t3, the twelfth transistor M12 is turned on by the low level of the first node N1, and transmits the low level supplied from the first fixed potential signal line VGL to the gate line Scan.

In one implementation, referring to fig. 4 and fig. 6, as shown in fig. 6, fig. 6 is a schematic diagram of another structure of the scan control circuit according to the embodiment of the present invention, and the first signal line CL1 is a second fixed-potential signal line VGH.

In the third period t3, the tenth transistor M10 is turned on by the low level of the first node N1, and the fixed high level provided by the second fixed potential signal line VGH is transmitted to the second node N2 via the turned-on tenth transistor M10, which ensures that the eleventh transistor M11 is turned off, thereby ensuring that the output block 5 outputs a stable low level in the third period t 3.

Alternatively, in another embodiment, as shown in fig. 7 and 8, fig. 7 is a schematic diagram of another structure of the scan control circuit provided in the embodiment of the present invention, fig. 8 is another timing diagram corresponding to the scan control circuit provided in the embodiment of the present invention, and the first signal line CL1 is the first clock signal line CK 1.

In the third and fourth periods t3 and t4, the first node N1 continues to be low level and the tenth transistor M10 continues to be turned on. When the first clock signal line CK1 provides a low level, the low level provided by the first clock signal line CK1 is transmitted to the second node N2 via the tenth transistor M10 which is turned on, the eleventh transistor M11 is controlled to be turned on, and the low level provided by the first clock signal line CK1 is transmitted to the gate line Scan via the eleventh transistor M11 which is turned on. At this time, the output block 5 simultaneously transmits the low level to the gate line Scan via two paths of the eleventh transistor M11 and the twelfth transistor M12, which improves the reliability of the Scan control circuit outputting the low level in this period. When the first clock signal line CK1 provides a high level, the high level provided by the first clock signal line CK1 is transmitted to the second node N2 via the tenth transistor M10 being turned on, and the eleventh transistor M11 is turned off, and thus, the high level provided by the first clock signal line CK1 cannot be output via the eleventh transistor M11, and the output block 5 outputs a low level only through the twelfth transistor M12 during this period.

In an implementation manner, as shown in fig. 9 to 11, fig. 9 is a schematic structural diagram of a scan control circuit provided in an embodiment of the present invention, fig. 10 is a schematic structural diagram of a scan control circuit provided in an embodiment of the present invention, and fig. 11 is a schematic structural diagram of a scan control circuit provided in an embodiment of the present invention; the scan control circuit further includes a thirteenth transistor M13, the thirteenth transistor M13 being connected in series between the third transistor M3 and the first node N1.

Referring to fig. 9 again, the control electrode of the thirteenth transistor M13 is electrically connected to the third node N3, and in combination with fig. 4, in the third time period t3, when the pull-down module 2 pulls down the potential of the first node N1, the thirteenth transistor M13 is turned off under the action of the high level of the third node N3, so as to prevent the transition of the potential of the first node N1 from being transmitted to the third transistor M3, and weaken the influence of the potential transition of the first node N1 on the third transistor M3.

Or, referring to fig. 10 again, the control electrode of the thirteenth transistor M13 is electrically connected to the first fixed potential signal line VGL, at this time, the thirteenth transistor M13 is in a normally open state, and in combination with fig. 4, when the potential of the first node N1 jumps low, the jump signal can still be weakened to a certain extent in the process of being transmitted to the third transistor M3 via the turned-on thirteenth transistor M13, compared with the case where the third transistor M3 is directly connected to the first node N1, the influence of the potential jump of the first node N1 on the third transistor M3 can be weakened.

Alternatively, referring to fig. 11 again, the gate of the thirteenth transistor M13 is electrically connected to the first clock signal line CK 1. Referring to fig. 4, at the time when the potential of the first node N1 is pulled low, the first clock signal is at a low level, the thirteenth transistor M13 is turned on, and the low-jump signal is attenuated during the transmission to the third transistor M3 via the turned-on thirteenth transistor M13, so that the influence of the potential jump of the first node N1 on the third transistor M3 is reduced.

Based on the same inventive concept, an embodiment of the present invention further provides a driving method of a scan control circuit, the driving method of the scan control circuit is applied to the scan control circuit, and with reference to fig. 1, fig. 4 and fig. 5, an operation process of the scan control circuit includes a first time period t1, a second time period t2, a third time period t3 and a fourth time period t4, the driving method includes:

IN the first period t1, the first control module 1 transmits the high level provided by the shift control signal line IN to the first node N1 and the fourth node N4 IN response to the low level provided by the first clock signal line CK1 and the low level provided by the third clock signal line CK3, and transmits the low level provided by the first fixed potential signal line VGL to the third node N3 IN response to the low level provided by the third clock signal line CK3, the third control module 4 transmits the low level provided by the second clock signal line CK2 to the second node N2 IN response to the low level of the third node N3 and the low level provided by the second clock signal line CK2, and the output module 5 transmits the low level provided by the first clock signal line CK1 to the gate line Scan IN response to the low level of the second node N2.

In the second period t2, the third control module 4 transmits the low level supplied from the second clock signal line CK2 to the second node N2 in response to the low level of the third node N3 and the low level supplied from the second clock signal line CK2, and the output module 5 transmits the high level supplied from the first clock signal line CK1 to the gate line Scan in response to the low level of the second node N2.

IN a third period t3, the first control module 1 transfers the low level provided by the shift control signal line IN to the first node N1 and the fourth node N4 IN response to the low level provided by the first clock signal line CK1 and the low level provided by the third clock signal line CK3, and transfers the low level provided by the first fixed potential signal line VGL to the third node N3 IN response to the low level provided by the third clock signal line CK3, the second control module 3 transfers the low level provided by the third clock signal line CK3 to the third node N3 IN response to the low level of the fourth node N4, the third control module 4 transfers the signal provided by the first signal line CL1 to the second node N2 IN response to the low level of the first node N1, the pull-down module 2 outputs the low level of the first node N1 IN response to the low level of the third node N3 and the low level of the first node N1, the low level supplied from the first fixed potential signal line VGL is transmitted to the gate line Scan.

In the fourth period t4, the pull-down module 2 continuously pulls down the potential of the first node N1 in response to the low level of the third node N3 and the low level of the first node N1, and the output module 5 continuously transmits the low level to the gate line Scan.

Please refer to fig. 4 again, after the fourth time period t4, the scan control circuit also executes the third time period t3 and the fourth time period t4 in a loop, so as to ensure that the scan control circuit continuously and stably outputs the low level in the subsequent time period, thereby ensuring the normal operation of the pixel circuit.

In an embodiment of the present invention, the second control module 3 transmits a voltage to the third node N3 in response to the voltage of the fourth node N4. Because the fourth node N4 is not electrically connected to the pull-down module 2, the voltage at the fourth node N4 is not affected by the pull-down module 2, and the fourth node N4 does not have an ultra-low potential, so that an excessive voltage difference between two ends of a transistor in the second control module 3 is avoided, the reliability of the working state of the transistor is improved, the reliability of the whole scanning control circuit is improved, the scanning control circuit can output accurate scanning signals to the gate line Scan, and the display panel can be ensured to normally emit light.

Based on the same inventive concept, an embodiment of the present invention further provides a shift register, as shown in fig. 12, fig. 12 is a schematic structural diagram of the shift register provided in the embodiment of the present invention, and the shift register 100 includes a plurality of scan control circuits 200. The specific circuit structure and driving method of the scan control circuit 200 have been described in detail in the above embodiments, and are not described herein again.

Based on the same inventive concept, an embodiment of the present invention further provides a display device, as shown in fig. 13, fig. 13 is a schematic structural diagram of the display device provided in the embodiment of the present invention, the display device includes a display panel 300 and a shift register 100, the display panel 300 includes a plurality of gate lines Scan and a plurality of Data lines Data, the plurality of gate lines Scan and the plurality of Data lines Data intersect to define a plurality of sub-pixels 400, and as described above, the sub-pixels 400 include pixel circuits and organic light emitting diodes which are electrically connected; the Scan control circuit 200 in the shift register 100 is electrically connected to the gate line Scan. Of course, the display device shown in fig. 13 is only a schematic illustration, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, or a television.

The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A scan control circuit, comprising:

2. The scan control circuit of claim 1, wherein the first control module comprises:

a first transistor, a control electrode of which is electrically connected to the first clock signal line, and a first electrode of which is electrically connected to the shift control signal line;

a second transistor having a control electrode electrically connected to the third clock signal line, a first electrode electrically connected to the second electrode of the first transistor, and a second electrode electrically connected to the fourth node;

a third transistor having a control electrode electrically connected to the third clock signal line, a first electrode electrically connected to the second electrode of the first transistor, and a second electrode electrically connected to the first node;

a fourth transistor, a control electrode of which is electrically connected to the third clock signal line, a first electrode of which is electrically connected to the first fixed potential signal line, and a second electrode of which is electrically connected to the third node.

3. The scan control circuit of claim 1, wherein the pull-down module comprises:

a fifth transistor, a control electrode of which is electrically connected to the third node, a first electrode of which is electrically connected to the second fixed potential signal line, and a second electrode of which is electrically connected to the fifth node;

a sixth transistor having a control electrode electrically connected to the first node, a first electrode electrically connected to the second clock signal line, and a second electrode electrically connected to the fifth node;

and a first plate of the first capacitor is electrically connected with the fifth node, and a second plate of the first capacitor is electrically connected with the first node.

4. The scan control circuit of claim 1, wherein the second control module comprises:

a seventh transistor, a control electrode of which is electrically connected to the fourth node, a first electrode of which is electrically connected to the third clock signal line, and a second electrode of which is electrically connected to the third node.

5. The scan control circuit of claim 1, further comprising:

and a first polar plate of the second capacitor is electrically connected with the second fixed potential signal line, and a second polar plate of the second capacitor is electrically connected with the fourth node.

6. The scan control circuit of claim 1, wherein the third control module comprises:

a third capacitor, wherein a first polar plate of the third capacitor is electrically connected with the third node;

an eighth transistor, a control electrode of which is electrically connected to the third node, a first electrode of which is electrically connected to the second clock signal line, and a second electrode of which is electrically connected to the second plate of the third capacitor;

a ninth transistor, a control electrode of which is electrically connected to the second clock signal line, a first electrode of which is electrically connected to the second plate of the third capacitor, and a second electrode of which is electrically connected to the second node;

a tenth transistor having a control electrode electrically connected to the first node, a first electrode electrically connected to the first signal line, and a second electrode electrically connected to the second node.

7. The scan control circuit of claim 1, further comprising:

and a first polar plate of the fourth capacitor is electrically connected with the first clock signal line, and a second polar plate of the fourth capacitor is electrically connected with the second node.

8. The scan control circuit of claim 1, wherein the output module comprises:

an eleventh transistor having a control electrode electrically connected to the second node, a first electrode electrically connected to the first clock signal, and a second electrode electrically connected to the gate line;

and a twelfth transistor, a control electrode of which is electrically connected to the first node, a first electrode of which is electrically connected to the first fixed potential signal line, and a second electrode of which is electrically connected to the gate line.

9. The scan control circuit of claim 1,

the first signal line is the second fixed potential signal line.

10. The scan control circuit of claim 1,

the first signal line is the first clock signal line.

11. The scan control circuit of claim 2, further comprising:

a thirteenth transistor connected in series between the third transistor and the first node;

a control electrode of the thirteenth transistor is electrically connected to the third node, or the control electrode of the thirteenth transistor is electrically connected to the first fixed-potential signal line, or the control electrode of the thirteenth transistor is electrically connected to the first clock signal line.

12. A driving method of a scan control circuit is characterized in that,

the working process of the scanning control circuit comprises a first period, a second period, a third period and a fourth period, and the driving method comprises the following steps:

in the third period, the first control module transmits a low level provided by the shift control signal line to the first node and the fourth node in response to a low level provided by the first clock signal line and a low level provided by the third clock signal line, and transmits a low level provided by the first fixed potential signal line to the third node in response to a low level provided by the third clock signal line, the second control module transmits a low level provided by the third clock signal line to the third node in response to a low level of the fourth node, the third control module transmits a signal provided by the first signal line to the second node in response to a low level of the first node, the pull-down module pulls down a potential of the first node in response to a low level of the third node and a low level of the first node, the output module transmits a low level provided by the first fixed potential signal line to the gate line in response to a low level of the first node;

13. A shift register comprising a plurality of cascaded scan control circuits according to any one of claims 1 to 11.

14. A display device, comprising:

the shift register of claim 13, wherein the scan control circuit is electrically connected to the gate lines.