CN113434441B - DMA transmission method, device, controller and readable storage medium - Google Patents

DMA transmission method, device, controller and readable storage medium Download PDF

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CN113434441B
CN113434441B CN202110707703.8A CN202110707703A CN113434441B CN 113434441 B CN113434441 B CN 113434441B CN 202110707703 A CN202110707703 A CN 202110707703A CN 113434441 B CN113434441 B CN 113434441B
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dma
request
request source
dma transmission
channel
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CN113434441A (en
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刘吉平
刘俊伟
王翔
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Shenzhen Hangshun Chip Technology R&D Co Ltd
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Shenzhen Hangshun Chip Technology R&D Co Ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

The application discloses a DMA transmission method, a device, a controller and a readable storage medium, wherein the DMA transmission method comprises the following steps: numbering a plurality of request sources; selecting a target request source corresponding to one or more DMA transmission channels from a plurality of request sources according to the number; acquiring target data according to a DMA transmission request signal of a target request source; and transmitting the target data through the corresponding DMA transmission channel. The DMA transmission method of the application codes a plurality of request sources, and the DMA transmission channel selects a target request source from the request sources according to the codes and transmits the data requested by the selected target request source. In the method, each DMA transmission channel can be selected from all request sources, so that the problem that each channel can only process fixed request sources in the original DMA design is solved, a developer does not need to query the request sources which can be processed by each channel when using DMA, and the development efficiency of the developer is improved.

Description

DMA transmission method, device, controller and readable storage medium
Technical Field
The present application relates to the field of communications technologies, and in particular, to a DMA transmission method, a DMA transmission device, a DMA controller, and a DMA readable storage medium.
Background
DMA (Direct Memory Access ) transfers allow hardware devices of different speeds to communicate without relying on the massive interrupt load of the CPU, thus allowing higher speeds to be achieved. DMA transfer does not save site, resume site, or the like during data transfer. Because the CPU does not participate in the transmission operation at all, the operations of CPU such as instruction fetching, sending and the like are omitted. Memory address modification, counting of the number of transferred words, etc., are not implemented by software, but directly by hardware lines. Therefore, the DMA mode can meet the requirement of high-speed I/O equipment and is also beneficial to the exertion of CPU efficiency.
In existing DMA designs, packets are typically made according to the number of DMA transfer requests, with each channel of the DMA handling a different packet. When using DMA, a developer needs to query the request source packet corresponding to each channel and select one of the request sources. In large-scale design, a large number of request sources may exist, so that the inquiry of the DMA channel corresponding to each request source is quite complicated and easy to make mistakes during use, and the development efficiency is reduced.
Disclosure of Invention
In view of the above, the present application provides a DMA transmission method, apparatus, controller and readable storage medium, so as to solve the problems of complex process and error-prone problem of the existing DMA transmission that a developer needs to query a request source packet corresponding to each channel when using DMA.
The DMA transmission method provided by the application comprises the following steps:
Numbering a plurality of request sources;
Selecting a target request source corresponding to one or more DMA transmission channels from the plurality of request sources according to the number;
Acquiring target data according to a DMA transmission request signal of the target request source;
and transmitting the target data through a corresponding DMA transmission channel.
Optionally, after the selecting a target request source of the corresponding DMA transfer channel from the plurality of request sources according to the number, the method further includes:
if a new request source is added, numbering the new request source;
And distributing the new request source to the corresponding DMA transmission channel according to the number of the new request source.
Optionally, after the target transmission data is transmitted through the corresponding DMA transmission channel, the method further includes:
acquiring the times of the DMA transmission channel for transmitting the target data;
And if the number of times is smaller than a preset transmission number threshold value, acquiring and processing a new DMA transmission request signal.
Optionally, the method further comprises:
And if the times are greater than or equal to the preset transmission times threshold, ending the DMA transmission.
The application also provides a DMA transmission device, which comprises:
The request source numbering module is used for numbering a plurality of request sources;
A request source selection module, configured to select a target request source corresponding to one or more DMA transmission channels from the plurality of request sources according to the number;
And the request processing module is used for acquiring target data according to the DMA transmission request signal of the target request source and transmitting the target data through a corresponding DMA transmission channel.
Optionally, the request source numbering module is further configured to code a new request source if the new request source is added;
The request source selection module is further configured to allocate the new request source to a corresponding DMA transmission channel according to the number of the new request source.
Optionally, the DMA transfer device further includes:
The counting module is used for acquiring the times of the DMA transmission channel for transmitting the target data;
And the request processing module is further used for acquiring and processing a new DMA transmission request signal if the number of times is smaller than a preset transmission number threshold value.
Optionally, the request processing module is further configured to end DMA transmission if the number of times is greater than or equal to the preset transmission number threshold.
The present application also provides a DMA controller comprising: the system comprises a memory and a processor, wherein the memory stores a DMA transmission method program, and the DMA transmission method program realizes the steps of the DMA transmission method in the above embodiments when being executed by the processor.
The present application also provides a computer storage medium storing a computer program which, when executed by a processor, implements the steps of the DMA transfer method in the above embodiments.
As described above, in the DMA transfer method according to the embodiment of the present application, a plurality of request sources are numbered, and the DMA transfer channel selects a target request source from the request sources according to the numbers and transfers data requested by the selected target request source. In the method, each DMA transmission channel can be selected from all request sources, so that the problem that each channel can only process fixed request sources in the original DMA design is solved, a developer does not need to query the request sources which can be processed by each channel when using DMA, and the development efficiency of the developer is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a prior art DMA transfer method;
FIG. 2 is a flowchart of a DMA transfer method according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a DMA transfer method according to an embodiment of the present application;
FIG. 4 is a flowchart of another DMA transfer method according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a DMA transfer apparatus according to an embodiment of the present application;
Fig. 6 is a schematic diagram of a DMA controller according to an embodiment of the present application.
Detailed Description
The technical solutions of the present application will be clearly and completely described by means of examples, and it is obvious that the described examples are only some of the examples of the present application, but not all of the examples. The various embodiments described below and their technical features can be combined with each other without conflict.
In the existing DMA transfer method, packets are performed according to the number of request sources for DMA transfer, and each channel of the DMA processes a different packet. The following 17 request sources are taken as an example for illustration.
ADC_QUE1, analog-to-digital converter request 1;
ADC_QUE2, analog-to-digital converter request 2;
ADC_QUE3, analog-to-digital converter request 3;
ADC_QUE4, analog-to-digital converter request 4;
ADC_QUE5, analog-to-digital converter request 5;
SPI_QUE1, serial peripheral interface request 1;
SPI_QUE2, serial peripheral interface request 2;
tim1_que1, timer 1 request 1;
Tim1_qu2, timer 1 request 2;
tim1_que3, timer 1 request 3;
tim1_qu4, timer 1 request 4;
tim2_que1, timer 2 request 1;
tim2_qu2, timer 2 request 2;
UART1_QUE1, UART1 request 1;
UART1_QUE2, UART1 request 2;
UART2_QUE1, UART2 request 1;
Uart2_qu2, universal asynchronous receiver transmitter 2 requests 2.
As shown in FIG. 1, the existing DMA transmission method is that 17 request sources are divided into five groups, wherein the total of 4 request sources of ADC_QUE1, SPI_QUE1, TIM1_QUE1 and TIM2_QUE1 are the first group, and the first group is connected with a channel 1 of a DMA controller; the total of 4 request sources of ADC_QUE2, SPI_QUE2, TIM1_QUE2 and TIM2_QUE2 are a second group, which is connected with the channel 2 of the DMA controller; the total of 3 request sources of ADC_QUE3, TIM1_QUE3 and UART1_QUE1 are a third group, and are connected with the channel 3 of the DMA controller; the total of 3 request sources of ADC_QUE4, TIM1_QUE4 and UART1_QUE2 is a fourth group, which is connected with the channel 4 of the DMA controller; the total of 3 request sources ADC_QUE4, UART2_QUE1 and UART2_QUE2 is the fifth group, connected to channel 5 of the DMA controller. In use, it is cumbersome and error-prone to query the DMA channel corresponding to each request source, and each channel can only handle the requests of the request sources of the present group, when the number of request sources changes, for example, a dac_que6 (analog-to-digital converter request 6) is newly added, the original design cannot be used any more.
The embodiment of the application provides a DMA transmission method, a flow diagram is shown in figure 2, and the DMA transmission method comprises the following steps:
101, numbering a plurality of request sources.
The request sources for DMA transfer generally include a plurality of request sources, and all the request sources are numbered in advance. For example, for 17 request sources in FIG. 3, they may be sequentially numbered 0-16 by the request source numbering module. In one embodiment, the DMA controller numbers 17 request sources as follows: ADC_QUE1 number 0, ADC_QUE2 number 1, ADC_QUE3 number 2, ADC_QUE4 number 3, ADC_QUE5 number 4, SPI_QUE1 number 5, SPI_QUE2 number 6, TIM1_QUE1 number 7, TIM1_QUE2 number 8, TIM1_QUE3 number 9, TIM1_QUE4 number 10, TIM2_QUE1 number 11, TIM2_QUE2 number 12, UART1_QUE1 number 13, UART1_QUE2 number 14, UART2_QUE1 number 15, UART2_QUE2 number 16.
102, Selecting a target request source corresponding to one or more DMA transmission channels from a plurality of request sources according to the number.
After numbering all the request sources, each request source corresponds to one number, and when the method is used, the DMA transmission channel can select the corresponding request source through the number only by inquiring the number of the corresponding channel. When there is only one DMA transfer channel, then all numbers are selected to that DMA transfer channel. When there are multiple DMA transfer channels, such as5 DMA transfer channels in the previous embodiment, 17 request sources are selected. If the request source selection module of the DMA transmission channel 1 needs to use the ADC_QUE1, selecting the number 0, wherein the ADC_QUE1 is the target request source of the DMA transmission channel 1; if the request source selection module of the DMA transmission channel 2 needs to use TIM1_QUE2, selecting the number 8, wherein TIM1_QUE2 is the target request source of the DMA transmission channel 2; the DMA transfer channel 3 to the DMA transfer channel 5 and so on, the corresponding target request source can be selected according to the number.
It will be appreciated that in this embodiment, each DMA transfer channel is connected to all request sources, and can process requests from all request sources, so that each DMA transfer channel can select a target request source from all numbers. When each DMA transmission channel finishes selecting the target request source, each DMA transmission channel only receives the DMA transmission request of the target request source selected by itself.
103, Acquiring target data according to the DMA transmission request signal of the target request source.
When a target request source sends a DMA transfer request signal, a corresponding DMA transfer channel receives the DMA transfer request signal. For example, when the DMA transfer channel 1 selects the number 0, and when the adc_quit1 (number 0) transmits the DMA transfer request signal, the DMA transfer channel 1 receives the DMA transfer request signal. The request processing module of the DMA controller acquires target data from the source address according to the DMA transmission request signal.
It should be noted that, in some embodiments, each DMA transfer channel may include a plurality of target request sources, and when at least 2 target request sources send transfer request signals at the same time, the request processing module may process DMA transfer requests sequentially according to the priority of the request sources.
104, Transmitting the target data through the corresponding DMA transmission channel.
After the request processing module of the DMA controller acquires the target data, the target data is sent to the target address through the corresponding DMA transmission channel. It will be appreciated that each DMA transfer channel, upon selection of a target request source, processes only the request from the selected target request source and transfers the data requested by the target request source.
In the above embodiment of the present application, a plurality of request sources are numbered, and the DMA transfer channel selects a target request source from the request sources according to the numbers and transfers data requested by the selected target request source. In the method, each DMA transmission channel can be selected from all request sources, so that the problem that each channel can only process fixed request sources in the original DMA design is solved, a developer does not need to query the request sources which can be processed by each channel when using DMA, and the development efficiency of the developer is improved.
The embodiment of the application provides another DMA transmission method, a flow diagram is shown in fig. 4, and the DMA transmission method comprises the following steps:
201, numbering a plurality of request sources.
In this step, reference may be made to step 101, which is not described in detail in this embodiment.
Alternatively, new request sources may be numbered when the DMA design needs to be changed, such as when new request sources need to be added. For example, a new request source tim2_que3 (timer 2 request 3) is added to the 17 request sources, and a new number 17 can be compiled.
202, Selecting a target request source corresponding to one or more DMA transmission channels from a plurality of request sources according to the number.
In this step, reference may be made to step 102, which is not described in detail in this embodiment.
Alternatively, in a new DMA design, for a new request source to be added, the new request source may be allocated to the corresponding DMA transfer channel. For example, one of the DMA transfer channels may be used to select a new request source based on the number of the new request source, which serves as a new target request source for the DMA transfer channel. For example, in the embodiment of step 201, the DMA transfer channel 3 may be selected with the number 17, and the request source tim2_qu3 becomes a new target request source for the DMA transfer channel 3.
203, Acquiring target data according to the DMA transmission request signal of the target request source.
In this step, reference may be made to step 103, which is not described in detail in this embodiment.
204, Transmitting the target data through the corresponding DMA transmission channel.
In this step, reference may be made to step 104, which is not described in detail in this embodiment.
205, Obtaining the number of times of the DMA transfer channel transferring the target data.
The number of DMA transfers is increased by 1 per DMA transfer request processed. In one embodiment, a counter may be used to record the number of times the DMA transfer channel transfers the target data. The number of times may be a sum of the number of times that all DMA transfer channels transfer the target data.
206, If the number of times is smaller than the preset transmission number threshold, acquiring and processing a new DMA transmission request signal.
A threshold value of the transfer number of times of transferring the target data with respect to the DMA transfer channel may be designed in advance, and when the number of DMA transfers is smaller than the threshold value of the transfer number, the request source may be waited for initiating a new DMA transfer request. The DMA controller may continuously receive and process a new DMA transfer request signal, i.e. may return to step 203 when the number of DMA transfers is less than the transfer number threshold.
Optionally, the foregoing embodiment may further include:
207, if the number of times is greater than or equal to the preset transmission number threshold, ending the DMA transmission.
After multiple DMA transmissions, when the number of times of the DMA transmissions is larger than a preset transmission number threshold, ending the DMA transmissions, and then the DMA controller returns the bus control right to the CPU.
In the above embodiment of the present application, a plurality of request sources are numbered, and the DMA transfer channel selects a target request source from the request sources according to the numbers and transfers data requested by the selected target request source. In the method, each DMA transmission channel can be selected from all request sources, so that the problem that each channel can only process fixed request sources in the original DMA design is solved, a developer does not need to query the request sources which can be processed by each channel when using DMA, and the development efficiency of the developer is improved. In addition, when the request source changes, the new request source can adapt to the change of the new design only by numbering the new request source, and the request source which can be processed by each DMA channel needs to be redistributed in the traditional method, so that the development cost is increased. The embodiment of the application does not need to redesign DMA like the traditional method, thereby reducing the cost of new design. The execution and end of DMA transfer can also be controlled by setting a transfer number threshold for the number of DMA transfer target data.
The embodiment of the present application further provides a DMA transfer device, as shown in fig. 5, the DMA transfer device 300 may include a request source numbering module 301, a request source selecting module 302, and a request processing module 303.
A request source numbering module 301, configured to code a plurality of request sources;
a request source selecting module 302, configured to select a target request source corresponding to one or more DMA transfer channels from the plurality of request sources according to the number;
The request processing module 303 is configured to obtain target data according to a DMA transmission request signal of the target request source, and transmit the target data through a corresponding DMA transmission channel.
In one embodiment, the request source numbering module 301 is further configured to code a new request source if the new request source is added;
the request source selection module 302 is further configured to allocate the new request source to a corresponding DMA transmission channel according to the number of the new request source.
In one embodiment, the DMA transfer apparatus 300 further comprises:
a counting module 304, configured to obtain the number of times the DMA transfer channel transfers the target data;
The request processing module 303 is further configured to acquire and process a new DMA transfer request signal if the number of times is less than a preset transfer number threshold.
In one embodiment, the request processing module 303 is further configured to end DMA transfer if the number of times is greater than or equal to the preset transfer number threshold.
The embodiment of the present application further provides a DMA controller, as shown in fig. 6, a DMA controller 400 may include: a memory 401 and a processor 402, wherein the memory 401 stores a computer program, and the computer program when executed by the processor 402 implements a flow in the DMA transfer method as provided in the present embodiment.
An embodiment of the present application provides a computer-readable storage medium having stored thereon a computer program which, when executed on a computer, causes the computer to execute the flow in the DMA transfer method as provided in the present embodiment.
That is, the foregoing embodiments of the present application are merely examples, and are not intended to limit the scope of the present application, and all equivalent structures or equivalent processes using the descriptions of the present application and the accompanying drawings, such as the combination of technical features of the embodiments, or direct or indirect application in other related technical fields, are included in the scope of the present application.

Claims (8)

1. A DMA transfer method, comprising:
Numbering a plurality of request sources;
Selecting a target request source corresponding to one or more DMA transmission channels from the plurality of request sources according to the number;
if a new request source is added, numbering the new request source;
distributing the new request source to a corresponding DMA transmission channel according to the number of the new request source;
Acquiring target data according to a DMA transmission request signal of the target request source;
and transmitting the target data through a corresponding DMA transmission channel.
2. The DMA transfer method according to claim 1, wherein after said transferring the target data through the corresponding DMA transfer channel, the method further comprises:
acquiring the times of the DMA transmission channel for transmitting the target data;
And if the number of times is smaller than a preset transmission number threshold value, acquiring and processing a new DMA transmission request signal.
3. The DMA transfer method according to claim 2, characterized in that the method further comprises:
And if the times are greater than or equal to the preset transmission times threshold, ending the DMA transmission.
4. A DMA transfer apparatus, comprising:
The request source numbering module is used for numbering a plurality of request sources;
A request source selection module, configured to select a target request source corresponding to one or more DMA transmission channels from the plurality of request sources according to the number;
the request processing module is used for acquiring target data according to the DMA transmission request signal of the target request source and transmitting the target data through a corresponding DMA transmission channel;
the request source numbering module is further configured to code a new request source if the new request source is added;
The request source selection module is further configured to allocate the new request source to a corresponding DMA transmission channel according to the number of the new request source.
5. The DMA transfer apparatus according to claim 4, wherein the DMA transfer apparatus further comprises:
The counting module is used for acquiring the times of the DMA transmission channel for transmitting the target data;
And the request processing module is further used for acquiring and processing a new DMA transmission request signal if the number of times is smaller than a preset transmission number threshold value.
6. The DMA transfer apparatus according to claim 5, wherein the request processing module is further configured to end the DMA transfer if the number of times is greater than or equal to the preset transfer number threshold.
7. A DMA controller, the DMA controller comprising: a memory and a processor, wherein the memory has stored thereon a computer program which, when executed by the processor, implements the steps of the DMA transfer method according to any of claims 1 to 3.
8. A readable storage medium, characterized in that it has stored thereon a computer program which, when executed by a processor, implements the steps of the DMA transfer method according to any of claims 1 to 3.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5555433A (en) * 1994-06-13 1996-09-10 Xerox Corporation Circuit for interfacing data busses
JP2002024157A (en) * 2000-07-07 2002-01-25 Matsushita Electric Ind Co Ltd Method and device for processing dma

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61131153A (en) * 1984-11-30 1986-06-18 Toshiba Corp Dma transfer control system
JP4174213B2 (en) * 2002-01-11 2008-10-29 キヤノン株式会社 Control circuit
CN100481045C (en) * 2007-04-24 2009-04-22 北京中星微电子有限公司 DMA controller and transmit method for implementing software/hardware reusing
CN104750639A (en) * 2015-04-09 2015-07-01 东南大学 Enhanced DMA controller based on AMBA bus
US9935870B2 (en) * 2016-01-14 2018-04-03 Xilinx, Inc. Channel selection in multi-channel switching network
CN112199309B (en) * 2020-10-10 2022-03-15 北京泽石科技有限公司 Data reading method and device based on DMA engine and data transmission system
CN112765059A (en) * 2021-01-20 2021-05-07 苏州浪潮智能科技有限公司 DMA (direct memory access) equipment based on FPGA (field programmable Gate array) and DMA data transfer method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5555433A (en) * 1994-06-13 1996-09-10 Xerox Corporation Circuit for interfacing data busses
JP2002024157A (en) * 2000-07-07 2002-01-25 Matsushita Electric Ind Co Ltd Method and device for processing dma

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