CN113424262A

CN113424262A - Storage verification method and device

Info

Publication number: CN113424262A
Application number: CN201980091806.7A
Authority: CN
Inventors: 孙亚萍; 王岩松; 李挺
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-03-21
Filing date: 2019-03-21
Publication date: 2021-09-21
Anticipated expiration: 2039-03-21
Also published as: WO2020186524A1; CN113424262B

Abstract

A storage checking method and a device are used for storing and checking user data with smaller granularity. The method comprises the following steps: carrying out error check and correction ECC check on user data to obtain ECC check data, wherein the user data comprises m pieces of sliced data, and m is an integer greater than 2; performing Redundant Array of Independent Disks (RAID) check or Erasure Codes (EC) check on user data and ECC check data to obtain parity check data; storing the m sliced data, the ECC check data and the parity check data on a plurality of chips; each of m chips in the plurality of chips bears one piece of sliced data, the sliced data borne by different chips are different, n first chips except the m chips in the plurality of chips bear the ECC check data, and p second chips except the m chips in the plurality of chips are used for bearing the parity check data.

Description

Storage verification method and device

Technical Field

The present application relates to the field of storage, and in particular, to a storage verification method and apparatus.

Background

With the rapid development of computer technology, more and more user data are available, and a single hard disk carried by a computer cannot meet the storage requirement of the user data, so that an independent storage system is required to be used for storing the user data. In the process of storing and transmitting user data in the storage system, the user data may be damaged due to hardware failure, software failure, hard disk error or the like of the storage system. In the prior art, some data protection techniques are generally adopted to improve the security and reliability of data storage. Such as parity (parity), Redundant Array of Independent Disks (RAID), Erasure Coding (EC), or Error Checking and Correcting (ECC). In some storage systems, a combination of data protection techniques is used. Such as a technique that employs a combination of ECC and EC, or a technique that employs a combination of ECC and RAID. ECC is used to correct bit errors and RAID/EC is used to recover fragmented data.

Intel and millitron have introduced a new mainstream memory chip technology 3D XPoint. Compared to NAND flash, 3D XPoint has 10 times low latency, 3 times write endurance, 4 times write per second, 3 times read performance improvement and 30% power consumption. 3D XPoint helps computers acquire and process large amounts of data generated by networked devices at a faster rate. The 3D XPoint memory includes a plurality of chips (die), each die including a plurality of partitions (partitions), each partition including a plurality of pages of data (pages) that are the smallest write-read granularity. FIG. 1 shows a die memory structure in 3D XPoint memory chip technology. As shown in fig. 1, a die comprises 16 partitions, denoted by P0, P1, … …, P15. One line of a die is a stripe, the storage space of a stripe is composed of a plurality of pages (pages), and a minimum rectangular box represents one page. User data and corresponding ECC check data are carried on one stripe in one die, and the ECC check data on the same die is used for checking the user data. For example, the user data size is 4kB, the storage space of one stripe of one die is 256 bytes (byte), and the storage space of each data page is 16 bytes. 4kB of user data may be spread over 17 die, e.g., die 0-die 16 carry 4KB of user data. The 16 data pages of one stripe in each die of die 0-die 16 are used to carry a portion of user data and corresponding ECC check data, for example, the portion of user data occupies 240 bytes, and the ECC check data occupies 16 bytes. Parity data for RAID/EC is carried on die 17.

The storage and verification method is suitable for user data with larger granularity, such as 4kB or 2 kB. How to store and check user data with smaller granularity (such as 256 bytes) is a technical problem to be solved.

Disclosure of Invention

The application provides a storage checking method and device, which are used for storing and checking user data with smaller granularity.

In one aspect, a storage verification method is provided, and the method is implemented by the following steps: carrying out error check and correction ECC (error correction code) check on user data to obtain ECC check data, wherein the user data comprises m sliced data, and m is an integer greater than 2; performing Redundant Array of Independent Disks (RAID) check or Erasure Codes (EC) check on the user data and the ECC check data to obtain parity check data; storing the m sliced data, the ECC check data, and the parity check data onto a plurality of chips; each of m chips in the plurality of chips bears one piece of sliced data, the sliced data borne by different chips are different, n first chips except the m chips in the plurality of chips bear the ECC check data, p second chips except the m chips in the plurality of chips are used for bearing the parity check data, and n and p are positive integers. By adopting the method, the partitioned data are dispersed on the m die, and the ECC check data are stored on the n die different from the m die, and the ECC check data can check the plurality of partitioned data, so that the storage check of the user data with small granularity can be realized. By storing parity data over p die different from the m and n die, data reliability is further ensured. If the existing storage checking method is adopted, the user data on the same die is checked by the ECC checking data on the same die, and when the user data with smaller granularity is stored, the user data and the ECC checking data may occupy a plurality of stripes, thereby causing reading delay. By the method of the embodiment of the application, the ECC check data can check the partitioned data on the multiple die, so that the reading delay can be avoided. By generating parity data independently from user data and ECC check data made up of a set of sliced data, no additional write amplification is introduced. In the existing method, if a group of parity data is generated by a plurality of groups of data, when the group of data changes, the parity data needs to be regenerated, so that the write quantity of the check is large. In the embodiment of the application, the user data and the ECC check data formed by the plurality of sliced data can be equivalent to a group of data, and the parity check data is independently generated by the user data and the ECC check data formed by the group of sliced data, so that extra write amplification is not introduced.

In one possible design, any one of the plurality of chips includes a plurality of partitions; one or more partitions on any one of the m chips bear one piece of fragment data; one or more partitions on the first chip carry the ECC check data; one or more partitions on the second chip carry the parity data.

In one possible design, the plurality of partitions are on a stripe. Where a stripe is a row of multiple die.

In one possible design, any one of the plurality of chips includes a plurality of partitions, and a partition on any one of the plurality of chips includes a plurality of data pages; one or more data pages on any one of the m chips bear one piece of fragmented data; one or more pages of data on the first chip carry the ECC check data; one or more data pages on the second chip carry the parity data.

In one possible design, the plurality of data pages are on a stripe. Where a stripe is a row of multiple die.

In a second aspect, a storage verification method is provided, which may be implemented by: reading a plurality of chips; the plurality of chips are used for storing user data, ECC check data and parity check data, the user data comprises a plurality of sliced data, each of m chips in the plurality of chips bears one sliced data, the sliced data borne by different chips are different, n first chips except the m chips in the plurality of chips bear the ECC check data, p second chips except the m chips in the plurality of chips are used for bearing the parity check data, and n and p are positive integers; if the data stored on p third chips in the plurality of chips is lost, then: performing Redundant Array of Independent Disks (RAID) verification or Erasure Codes (EC) verification on the p third chips to obtain recovery data on the p third chips; and performing ECC (error correction code) check on the data of the m chips by adopting the ECC check data to obtain the user data, wherein if the p third chips comprise the chips in the m chips, the data of the m chips comprise the recovery data. By adopting the method, the user data with smaller granularity is fragmented, the fragmented data is dispersed on the m die, and the ECC check data is stored on the n die different from the m die, so that the ECC check data can check the plurality of fragmented data, and the storage check of the user data with small granularity can be realized. By storing parity data over p die different from the m and n die, data reliability is further ensured. If the existing storage checking method is adopted, the user data on the same die is checked by the ECC checking data on the same die, and when the user data with smaller granularity is stored, the user data and the ECC checking data may occupy a plurality of stripes, thereby causing reading delay. By the method of the embodiment of the application, the ECC check data can check the partitioned data on the multiple die, so that the reading delay can be avoided. By generating parity data independently from user data and ECC check data made up of a set of sliced data, no additional write amplification is introduced. In the existing method, if a group of parity data is generated by a plurality of groups of data, when the group of data changes, the parity data needs to be regenerated, so that the write quantity of the check is large. In the embodiment of the application, the user data and the ECC check data composed of the plurality of sliced data can be equivalent to a group of data, and the parity check data is independently generated by the user data and the ECC check data composed of the group of sliced data, so that extra write amplification is not introduced

In one possible design, the maximum number of bits that the ECC check data can correct errors is not less than the number of bits of data existing in the m chips. This ensures reliability in the event of die data loss.

In a third aspect, a storage verification apparatus is provided, which has a function of implementing the first aspect, the second aspect, any one of the possible designs of the first aspect, or any one of the possible designs of the second aspect. The functions can be realized by hardware, and the functions can also be realized by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the above-described functions.

In a fourth aspect, a memory system is provided, the memory system comprising a processing device and a memory device, the memory device being operable to perform the functions of the first aspect, the second aspect, any of the possible designs of the first aspect or any of the possible designs of the second aspect.

In a fifth aspect, a computer storage medium is provided that stores a computer program comprising instructions for performing the aspects described above and any possible method in design of aspects.

In a sixth aspect, there is provided a computer program product containing instructions which, when run on a computer, cause the computer to perform the method as described in the aspects and any possible design of aspects.

Drawings

FIG. 1 is a schematic diagram of a 3D XPoint memory chip in the prior art;

FIG. 2 is a schematic diagram of a memory system architecture according to an embodiment of the present application;

FIG. 3 is a schematic flow chart illustrating a storage verification method according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a memory structure in an embodiment of the present application;

FIG. 5 is a schematic diagram of a verification method in an embodiment of the present application;

FIG. 6 is a schematic structural diagram of a storage verification apparatus according to an embodiment of the present application;

FIG. 7 is a second schematic structural diagram of a memory verification apparatus according to an embodiment of the present application;

fig. 8 is a third schematic structural diagram of a storage verification apparatus in the embodiment of the present application.

Detailed Description

The embodiment of the application provides a storage checking method and device, which are used for storing and checking user data with smaller granularity. The method and the device are based on the same conception, and because the principle of solving the problems of the method and the device is similar, the implementation of the device and the method can be mutually referred, and repeated parts are not repeated. In the description of the embodiment of the present application, "and/or" describes an association relationship of associated objects, which means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. At least one referred to in this application means one or more; the plural referred to means two or more. In addition, it is to be understood that the terms first, second, etc. in the description of the present application are used for distinguishing between the descriptions and not necessarily for describing a sequential or chronological order.

Fig. 2 illustrates an architecture of a possible storage system to which the storage verification method provided in the embodiment of the present application is applied. As shown in fig. 2, the storage system 200 includes a processing device 201 and a storage device 202. The processing device 201 may be, for example, a computer host. The storage device 202 may include devices such as a storage server and an interface server, and the storage device 202 has its own interface and protocol, and is connected to the processing device 201 by means of a coaxial cable, a network cable, an optical fiber, and the like, and serves as a storage center for data to provide storage services for the processing device 201. The storage device 202 is mainly used for storing user data and verification data in the present application. When the above memory system 200 is used, one I/O operation is divided into two aspects of writing and reading. For the write aspect, the processing device 201 initiates a write request over a network such as a SAN, and the storage device 202 receives the write request from the processing device 201 requesting that user data be written to the storage device 202. For the read aspect, the storage device 202 receives a read request from the processing device 201, the storage device 202 reads the user data and the check data, and when the user data matches the check data, the storage device 202 returns the user data to the processing device 201.

The method provided by the embodiment of the application can be applied to any application scenarios using ECC and RAID/EC verification methods, and the 3D XPoint storage medium is taken as an example in the application, but the method is not limited to the 3D XPoint storage medium, and can also be applied to other storage media. The method provided by the embodiment of the application can store and verify the user data with smaller granularity. The user data with smaller granularity, for example, the size of the user data is 256 bytes, 128 bytes, 512 bytes, and the like. According to the embodiment of the application, for user data with a smaller granularity, according to a storage structure of a die, if the storage size of one row (namely, one stripe) of the die is not enough to store the user data and the ECC check data, the method provided by the embodiment of the application is adopted to perform storage check. For example, the user data size is 256 bytes. As shown in fig. 1, a die may include 16 partitions, one data page in one partition having a size of 16 bytes, and one stripe of one die having a storage size of 256 bytes. Therefore, if one stripe in one die stores the user data with the size of 256 bytes by using the related art method, the ECC check data of the user data can be stored only on another stripe in the die, which increases the read delay. The method provided by the embodiment of the application can help to solve the problem of reading delay.

As shown in fig. 3, the storage verification method of the present application will be described in detail below.

S301, carrying out ECC check on the user data to obtain ECC check data.

Wherein the user data comprises a plurality of sliced data. For example, the user data may be sliced first to obtain a plurality of sliced data. To reduce read latency, a slice of data may occupy some or all of the data pages in a stripe of a die. And determining the number of the fragments according to the size of the user data and the storage space of the data page. For example, if the user data size is 256 bytes and the storage space of one data page is 16 bytes, the data page may be fragmented into 16 pieces of fragmented data, and one piece of fragmented data occupies exactly one data page. Of course, according to the size of the user data, the user data may be fragmented so that the fragmented data occupies two or more data pages.

S302, RAID check or EC check is carried out on the user data and the ECC check data to obtain parity (parity) data.

It should be noted that, in the embodiment of the present application, specific methods of ECC checking, RAID checking, and EC checking may be referred to in the prior art, and are not described herein again.

And S303, storing the obtained plurality of slicing data, the ECC check data and the parity check data on a plurality of chips.

If the user data is divided into m pieces of sliced data, the plurality of chips may include m chips, n chips, and p chips. The m chips, the n chips and the p chips are different chips in the m chips, wherein the m chips bear m piece data, the n chips bear ECC check data, and the p chips bear odd-even check data. m is an integer greater than 1, and n and p are both positive integers. In general, the value of p is related to the number of die recovered. In the embodiments of the present application, n is 1 and p is 1. It is understood that the application of this exemplary method to scenarios where n and p are integers greater than 1 is also within the scope of the present application.

Dividing the user data into m sliced data, the user data and the check data can be stored on (m +2) die, wherein the check data includes ECC check data and parity check data. Each die of m dice in the (m +2) dice carries one piece of sliced data, and different dice carry different pieces of sliced data. Optionally, the m pieces of fragmented data into which the user data is divided are numbered according to the sequence numbers, and the m pieces of fragmented data may be sequentially placed on die with corresponding sequence numbers. ECC check data and parity data are carried on two die other than m die, respectively, for example, ECC check data is carried on a first chip other than m die, and parity data is carried on a second chip other than m die. Assuming that (m +2) dice are represented by dice 0, dice 1, … …, and dice (m +1), m different pieces of sliced data may be carried on dice 0, dice 1, … …, and dice (m-1), respectively, ECC check data is carried on dice m, and parity data is carried on dice (m + 1).

Any one die of the (m +2) dice includes a plurality of partitions (partition). Wherein, one or more partitions on any die in the m dice bear one piece of fragment data. The number of partitions for bearing the fragment data is determined according to the size of the user data and the storage space of the data page. Similarly, one or more partitions on the first chip carry ECC check data. The first one or more partitions on the second chip carry parity data. The number of the partitions for bearing the ECC check data is determined according to the size of the ECC check data and the storage space of the data page. The number of partitions carrying parity data is determined according to the size of the parity data and the storage space of the data page. Generally, the size of the ECC check data is determined by the size of the user data, and the size of the parity data is determined by the sizes of the user data and the ECC check data. Further, when multiple partitions carry one fragmented data, the multiple partitions may be on one stripe, and similarly, when multiple partitions carry ECC check data, the multiple partitions may be on one stripe; when multiple partitions carry parity data, the multiple partitions may be on a stripe, which can reduce read latency.

Any one of the (m +2) dice includes a plurality of partitions (partition), and one partition includes a plurality of data pages, one data page being a minimum read-write unit. Then, one or more data pages on any one die of the m dice carry one piece of sliced data. The number of partitions for bearing the fragment data is determined according to the size of the user data and the storage space of the data page. Similarly, one or more pages of data on the first chip carry ECC check data. One or more data pages on the second chip carry parity data. The number of the partitions for bearing the ECC check data is determined according to the size of the ECC check data and the storage space of the data page. The number of data pages carrying parity data is determined according to the size of the parity data and the storage space of the data pages. Generally, the size of the ECC check data is determined by the size of the user data, and the size of the parity data is determined by the sizes of the user data and the ECC check data. Further, when multiple data pages carry one fragmented data, the multiple data pages may be on one stripe, and similarly, when multiple data pages carry ECC check data, the multiple data pages may be on one stripe; when multiple data pages carry parity data, the multiple data pages may be on a stripe, which can reduce read latency.

For example, assuming that the user data is 256 bytes and the storage size of one data page in die is 16 bytes, the user data may be divided into 16 pieces of sliced data, and the size of one piece of sliced data is 16 bytes. The entire user data occupies 16 die. The user data and the check data are integrated to occupy 18 die. As shown in fig. 4, it is assumed that 18 die are represented by die0, die1, … …, and die 17. Different shard data in the 16 shard data can be stored on die 0-die 15, respectively, and the shard data is indicated by letter d. ECC check data is stored on die17 and parity data is stored on die 18. The storage location is merely an example, and other storage manners may be used in the embodiments of the present application, for example, two or more data pages occupying one stripe on one die are used to store fragmented data.

If a plurality of sets of data are used to generate a set of parity data, when a set of data changes, the parity data needs to be regenerated, resulting in a large write amount of checks. In the embodiment of the application, the user data and the ECC check data formed by the plurality of sliced data can be equivalent to a group of data, and the parity check data is independently generated by the user data and the ECC check data formed by the group of sliced data, so that extra write amplification is not introduced.

S304, reading a plurality of chips.

By fragmenting the user data with smaller granularity, the user data and the check data are dispersed on a plurality of die, and the user data or the check data borne on each die does not exceed one stripe, so that concurrent access can be realized during reading, and the reading time delay can be reduced during reading.

If the data stored on p chips of the plurality of chips is lost, S305 to S306 are executed. The p chips may be any p chips in the plurality of chips, for example, data loss on a chip storing fragmented data, data loss on a second chip storing ECC check data, or data loss on a third chip storing parity check data. The p chips that lose data are referred to as p third chips.

S305, performing RAID check or EC check by adopting the parity check data to obtain recovery data on the p third chips.

And if the chip losing the data is a chip storing the fragment data and ECC check data, performing RAID check by adopting parity check data stored on the second chip. And if the parity data on the second chip is lost, calculating the parity data by adopting the fragment data and the ECC check data, and then recovering the data.

If RAID check is performed on the user data and the ECC check data in S302, RAID check is performed using the parity data stored on the first chip to obtain recovery data on the third chip.

If EC check is performed on the user data and the ECC check data in S302, EC check is performed using the parity check data stored on the first chip to obtain recovery data on the third chip.

S306, ECC check is carried out on the data on the m chips by adopting the ECC check data stored on the first chip, if data loss exists on the m chips, the slicing data stored on the lost chip is obtained, and the whole user data is further obtained. Wherein the data on the m chips includes the recovered data obtained in S305.

In the present application, ECC check is performed on a plurality of sliced data, and the sliced data is stored on a die, for example, a first chip; and performing RAID/EC check on the plurality of sliced data and ECC check data to obtain parity data, and storing the parity data on another die, for example, a second chip. When data is read, if the fragmented data on the third chip is lost, data recovery is performed according to a method of firstly adopting RAID/EC check and then ECC check. Namely, the data on the third chip is restored by adopting a RAID/EC verification method to obtain the restored data. And jointly checking the recovery data on the third chip and the fragmented data on other chips for storing the fragmented data by using an ECC checking method so as to obtain correct user data. The number of check bits of the recovered data obtained by the RAID/EC check method is the sum of the number of error bits of the partitioned data on other chips, so that when ECC check is used, the maximum number of error bits of the ECC check data is not less than the sum of the number of error bits of the data on m chips, and the data on m chips comprise recovered data of a third chip.

The following describes the data recovery process in detail by way of example.

As shown in fig. 5, still taking the above example as an example, the user data is 256 bytes, the storage size of one data page in the die is 16 bytes, the user data is sliced to obtain 16 sliced data, the 16 sliced data may be stored on die0 to die15, the user data composed of the 16 sliced data is ECC checked to obtain ECC check data, and the ECC check data is stored on die 16. And performing RAID/EC check on the user data and the ECC check data to obtain parity data, and storing the parity data on die 17.

In data storage, there must be an error bit. It is assumed that both user data and check data have erroneous bits. Assuming that die2 is lost during reading, RAID/EC check is performed on the fragmentation data on die1, die3, die4 … and the ECC check data on die16 by parity check data to obtain recovery data on die 2. Because of the presence of error bits in user data storage, the recovered data of die2 obtained through RAID/EC checks will also have error bits. Assuming that there are x error bits in the sliced data on die other than die2, there will be x error bits in the recovered data of die2 at most. Then there are 2x error bits for the entire user data. Then, the ECC check data on die16 is used to check the fragmentation data on die0, die1, and die 3-die 15 and the obtained recovery data on die2, so as to obtain the fragmentation data lost on die 2. If the error bit of the user data is 2 times xbit, when the error correction capability of the ECC is greater than or equal to 2 times x bits, the data on die2 can be correctly read, so that the entire user data can be correctly read. The error correction capability of an ECC is greater than or equal to 2 times x bits, that is, the number of error bits that the ECC can correct can be greater than or equal to 2 times x bits. This ensures reliability in the event of die data loss.

Assuming that data loss occurs in p dice during reading, y error bits coexist on dice other than the p dice, and the recovered data of the p dice stores p times of x error bits at most. Then there are (p +1) times x error bits for the entire user data. Similarly, the error correction capability of an ECC is greater than or equal to ((p +1) times x bits, i.e., the number of error bits that the ECC can correct can be greater than or equal to (p +1) times x bits.

Based on the same concept of the above method embodiment, as shown in fig. 6, an embodiment of the present application further provides a storage verification apparatus 600, where the storage verification apparatus 600 is configured to perform a corresponding operation in writing in the storage verification method. The storage verification apparatus 600 includes a verification unit 601 and a storage unit 602. Wherein:

a checking unit 601, configured to perform error checking and ECC correction checking on user data to obtain ECC check data, where the user data includes m pieces of sliced data; and the data processing device is used for carrying out RAID (redundant array of independent disks) check or EC (erasure code) check on the user data and the ECC check data to obtain parity check data, wherein m is an integer greater than 2; (ii) a

A storage unit 602, configured to store the m sliced data, the ECC check data, and the parity data onto (m +2) chips; each of m chips in the (m +2) chips bears one piece of sliced data, the sliced data borne by different chips are different, n first chips except the m chips in the (m +2) chips bear the ECC check data, p second chips except the m chips in the (m +2) chips are used for bearing the parity check data, and n and p are positive integers.

Optionally, any one of the (m +2) chips includes a plurality of partitions;

one or more partitions on any one of the m chips bear one piece of fragment data;

one or more partitions on the first chip carry the ECC check data;

one or more partitions on the second chip carry the parity data.

Optionally, the plurality of partitions are on a strip.

Optionally, any one of the (m +2) chips includes a plurality of partitions, and one partition on any one of the (m +2) chips includes a plurality of data pages;

one or more data pages on any one of the m chips bear one piece of fragmented data;

one or more pages of data on the first chip carry the ECC check data;

one or more data pages on the second chip carry the parity data.

Optionally, the plurality of data pages are on a stripe.

Based on the same concept of the above method embodiment, as shown in fig. 7, an embodiment of the present application further provides a storage verification apparatus 700, where the storage verification apparatus 700 is configured to perform a corresponding operation in a reading aspect in the above storage verification method. The storage verification apparatus 700 includes a reading unit 701 and a verification unit 702. Wherein:

a reading unit 701 that reads (m +2) chips; the (m +2) chips are used for storing user data, ECC check data and parity data, the user data comprises a plurality of sliced data, each of m chips in the (m +2) chips carries one sliced data, the sliced data carried by different chips are different, a first chip except the m chips in the (m +2) chips carries the ECC check data, and a second chip except the m chips in the (m +2) chips is used for carrying the parity data;

a checking unit 702, configured to perform RAID checking or erasure code EC checking on a redundant array of independent disks by using the parity data when the fragmented data stored on a third chip of the m chips is lost, to obtain recovered data on the third chip; and performing ECC (error correction code) check on the data of the m chips by adopting the ECC check data to obtain the user data, wherein the data of the m chips comprises the recovery data.

Optionally, the maximum number of bits for error correction of the ECC check data is not less than the number of bits of data existing in the m chips.

Based on the same concept of the above method embodiment, as shown in fig. 8, an embodiment of the present application further provides a storage verification apparatus 800, where the storage verification apparatus 800 is configured to execute the above storage verification method. The memory verification device 800 includes a processor 801 and a memory 802. Wherein:

the processor 801 is configured to receive a write request for writing user data into the chip, a read request for reading the chip, and operations of the verification aspect described in the above method embodiments, and the like, and the memory 802 may be equivalent to the chip in the above method embodiments, and is configured to store the user data and the verification data. The processor 801 in the storage verification apparatus 800 may also be configured to perform other operations in the above method embodiments, which are not described herein again.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.

Claims

A storage verification method, comprising:

carrying out error check and correction ECC (error correction code) check on user data to obtain ECC check data, wherein the user data comprises m sliced data, and m is an integer greater than 2;

performing Redundant Array of Independent Disks (RAID) check or Erasure Codes (EC) check on the user data and the ECC check data to obtain parity check data;

storing the m sliced data, the ECC check data, and the parity check data onto a plurality of chips; each of m chips in the plurality of chips bears one piece of sliced data, the sliced data borne by different chips are different, n first chips except the m chips in the plurality of chips bear the ECC check data, p second chips except the m chips in the plurality of chips are used for bearing the parity check data, and n and p are positive integers.
The method of claim 1, wherein any one of the plurality of chips comprises a plurality of partitions;

one or more partitions on any one of the m chips bear one piece of fragment data;

one or more partitions on the first chip carry the ECC check data;

one or more partitions on the second chip carry the parity data.
The method of claim 2, wherein the plurality of partitions are on a stripe.
The method of claim 1, wherein any one of the plurality of chips comprises a plurality of partitions, one partition on any one of the plurality of chips comprising a plurality of data pages;

one or more data pages on any one of the m chips bear one piece of fragmented data;

one or more pages of data on the first chip carry the ECC check data;

one or more data pages on the second chip carry the parity data.
The method of claim 4, wherein the plurality of pages of data are on a stripe.
A storage verification method, comprising:

reading a plurality of chips; the plurality of chips are used for storing user data, ECC check data and parity check data, the user data comprises a plurality of sliced data, each of m chips in the plurality of chips bears one sliced data, the sliced data borne by different chips are different, n first chips except the m chips in the plurality of chips bear the ECC check data, p second chips except the m chips in the plurality of chips are used for bearing the parity check data, and n and p are positive integers;

if the data stored on p third chips in the plurality of chips is lost, then:

performing Redundant Array of Independent Disks (RAID) verification or Erasure Codes (EC) verification on the p third chips to obtain recovery data on the p third chips;

and performing ECC (error correction code) check on the data of the m chips by adopting the ECC check data to obtain the user data.
The method of claim 6, wherein a maximum number of bits by which the ECC check data can be corrected is not less than a number of bits by which data of the m chips exists.
A storage verification apparatus, comprising:

the device comprises a checking unit, a data processing unit and a data processing unit, wherein the checking unit is used for carrying out error check and correction ECC check on user data to obtain ECC check data, the user data comprises m sliced data, and m is an integer greater than 2; and the data processing unit is used for carrying out RAID (redundant array of independent disks) check or EC (erasure code) check on the user data and the ECC check data to obtain parity check data;

a storage unit, configured to store the m sliced data, the ECC check data, and the parity check data on a plurality of chips; each of m chips in the plurality of chips bears one piece of sliced data, the sliced data borne by different chips are different, n first chips except the m chips in the plurality of chips bear the ECC check data, p second chips except the m chips in the plurality of chips are used for bearing the parity check data, and n and p are positive integers.
The apparatus of claim 8, wherein any one of the plurality of chips comprises a plurality of partitions;

one or more partitions on any one of the m chips bear one piece of fragment data;

one or more partitions on the first chip carry the ECC check data;

one or more partitions on the second chip carry the parity data.
The apparatus of claim 9, wherein the plurality of partitions are on a strip.
The apparatus of claim 9, wherein any one of the plurality of chips comprises a plurality of partitions, one partition on any one of the plurality of chips comprising a plurality of pages of data;

one or more data pages on any one of the m chips bear one piece of fragmented data;

one or more pages of data on the first chip carry the ECC check data;

one or more data pages on the second chip carry the parity data.
The apparatus of claim 11, wherein the plurality of pages of data are on a stripe.
A storage verification apparatus, comprising:

a reading unit that reads the plurality of chips; the plurality of chips are used for storing user data, ECC check data and parity check data, the user data comprises a plurality of sliced data, each of m chips in the plurality of chips bears one sliced data, the sliced data borne by different chips are different, n first chips except the m chips in the plurality of chips bear the ECC check data, p second chips except the m chips in the plurality of chips are used for bearing the parity check data, and n and p are positive integers;

the verification unit is used for performing Redundant Array of Independent Disks (RAID) verification or Erasure Code (EC) verification on p third chips in the plurality of chips when data stored on the p third chips are lost, so as to obtain recovery data on the p third chips; and performing ECC (error correction code) check on the data of the m chips by adopting the ECC check data to obtain the user data.
The apparatus of claim 13, wherein a maximum number of bits by which the ECC check data can be error-corrected is not less than a number of bits by which data of the m chips exists.