CN113422603B - SET detection circuit, method and chip - Google Patents
SET detection circuit, method and chip Download PDFInfo
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Abstract
The invention discloses a SET detection circuit, a SET detection method and a SET detection chip.A locking detection module input end is respectively connected with clk0 and clk360, and a locking detection module output end is connected with lock_l0; the input ends of the inverter and the transmission gate of the differential clock judgment circuit are respectively connected with two differential signals, the two differential signals are a pair of complementary differential signals, the output ends of the inverter and the transmission gate are connected with the input end of the exclusive-OR gate, and the output end of the exclusive-OR gate is connected with the d port of the trigger; the ck port of the trigger is connected with clk0; the rstb port of the trigger is connected with the output end of the locking detection module; the q port of the trigger is connected with the first input end of the NAND gate, the second input end of the NAND gate is connected with tie_high, and the output end of the NAND gate is connected with lock_l1. The lock detection function in the normal circuit is reserved, and two special SET responses in the voltage-controlled delay line can be detected.
Description
Technical Field
The invention belongs to the field of anti-radiation reinforcement, and relates to a SET detection circuit, a SET detection method and a SET detection chip.
Background
Delay locked loops (Delay locked loop, DLLs) are one type of phase locked loop (Phase locked loop, PLL) that is widely used in microprocessors, memory interfaces, clock distribution networks on communication chips. DLLs are specially designed for applications of clock distribution and data synchronization, in which frequency multiplication and clock synthesis are not required, and thus DLLs are favored over PLLs due to better stability and lower jitter. The phase detector is mainly composed of a phase detector, a charge pump, a low-pass filter and a voltage-controlled delay line, wherein the phase detector generates continuously-adjusted switching signals by comparing the phase difference of a feedback clock generated by an input reference clock and the voltage-controlled delay line, so as to control charge and discharge of the charge pump, adjust output control voltage, and form stable control signals after the voltage is filtered by the low-pass filter, so that the delay of the voltage-controlled delay line is adjusted, and finally, the phase detector reaches a locking state.
A single event transient (Single event transient, SET) refers to a disturbance of the node voltage caused by the drift and diffusion of a large number of free carriers generated when energetic particles are incident on a sensitive node in an integrated circuit. With the continuous decrease of the processing size of integrated circuits, the continuous increase of the operating frequency of circuits, the influence of SET on integrated circuits for aerospace applications is becoming more and more interesting. Particularly in analog integrated circuits such as DLLs, the SET-induced response will be more complex. Although the current radiation-resistant reinforcement technology has been developed from the device to the system level, the occurrence of the SET is inevitably caused after the energy of the incident particles reaches a certain value. If the SET is present in the DLL module in the memory interface but not detected, an error in the data transmission must be caused.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a SET detection circuit, a SET detection method and a SET detection chip, which not only keep the locking detection function in a normal circuit, but also can detect two special SET responses in a voltage-controlled delay line.
In order to achieve the purpose, the invention is realized by adopting the following technical scheme:
a SET detection circuit comprises a lock detection module and a differential clock judgment circuit;
the input end of the locking detection module is connected with clk0 and clk360 respectively, and the output end of the locking detection module is connected with lock_l0;
the differential clock judgment circuit comprises a first inverter, a transmission gate, an exclusive-OR gate, a first trigger and a first NAND gate, wherein the input ends of the first inverter and the transmission gate are respectively connected with two differential signals, the two differential signals are a pair of complementary differential signals, the output ends of the inverter and the transmission gate are connected with the input end of the exclusive-OR gate, and the output end of the exclusive-OR gate is connected with the d port of the first trigger; the ck port of the first trigger is connected with clk0; the rstb port of the first trigger is connected with the output end of the locking detection module; the q port of the first trigger is connected with the first input end of the first NAND gate, the second input end of the first NAND gate is connected with tie_high, and the output end of the first NAND gate is connected with lock_l1.
Preferably, the lock detection module includes a second buffer, a third buffer, a second flip-flop, a third flip-flop, a second nand gate, a second inverter, and a third nand gate;
clk0 is divided into two paths, one path is connected with a d port of the third trigger, and the other path is connected with a ck port of the second trigger through the second buffer; clk360 is divided into two paths, one path is connected with the d port of the second trigger, and the other path is connected with the ck port of the third trigger through a third buffer; the q ports of the second trigger and the third trigger are respectively connected with two input ends of a second NAND gate; the output end of the second NAND gate is connected with the input end of the second inverter, the output end of the second inverter is connected with one of the input ends of the third NAND gate, the other input end of the third NAND gate is connected with lock_en, and the output end of the third NAND gate is connected with lock_l0.
Preferably, a first buffer is connected between the output end of the exclusive-or gate and the d port of the first trigger.
Preferably, the differential clock decision circuits are multiple groups, and differential signals complementary in pairs among each group are staggered.
The SET detection method based on any one of the circuits, wherein the lock_l0 output is high and the lock_l1 output state is invalid before the circuit is locked, when the circuit enters the locked state at the time t1, the lock_l0 output is 0, meanwhile, no single event transient appears on the voltage-controlled delay line, the output result of the lock_l1 is 1, and no single event transient appears at the moment; when a single event transient occurs in the circuit at time t2, the priority of the detection result of lock_l0 is the highest, and as long as lock_l0 jumps to be high, it is indicated that a SET phenomenon occurs in the circuit.
A SET detection method based on any one of the above circuits, when the circuit is locked, one of the complementary differential signals generates a duty cycle error pulse, the output of lock_l0 is always kept at a low potential, when the other differential signal is inverted, the output of lock_l0 is xored with the differential signal generating the duty cycle error pulse, a high pulse is generated at time t1, the pulse encounters the rising edge of clko at the next period at time t2, the pulse is captured by clko, so that the output of the first trigger is SET to be high, and the result is then nand-operated with tie_high, so that lock_l1 generates a downward pulse, at this time, the duty cycle error is displayed until lock_l1 is restored to a high level state after one clock period.
A SET detection method based on any one of the above circuits, when the circuit is locked, a pair of complementary differential signals have a missing pulse of one period, lock_l0 is always kept at a low level, one of the pair of complementary differential signals passes through an inverter, and then performs an exclusive-or operation with the other differential signal, so that a period of high pulse is generated, the pulse is captured by the rising edge of clk0, so that the output of the first flip-flop is SET to be high, and the result is then nand-operated with tie_high, so that lock_l1 has a downward pulse, at this time, the missing pulse error is detected, and lock_l1 is pulled down by one clock period.
A chip on which the SET detection circuit of any one of the above is printed.
Compared with the prior art, the invention has the following beneficial effects:
according to the circuit, a locking detection circuit of clk0 and clk360 is still reserved in the circuit, after locking, the result of a transmission gate with the same delay, through which one differential signal is inverted, of the pair of complementary differential signals and the other differential signal are identical signals, the result of exclusive OR is used as input data of a first trigger, the output result of the first trigger is respectively subjected to NAND operation at tie_high, and finally, duty ratio error pulses and lost pulses can be captured, so that the locking detection function in a normal circuit is reserved, and two special SET responses in a voltage-controlled delay line can be detected.
Further, the addition of the first buffer can ensure that the result output by the exclusive-or gate can be collected by the first trigger.
Drawings
FIG. 1 is a schematic diagram of a SET detection circuit according to the present invention;
FIG. 2 is a schematic diagram of a lock detection module according to the present invention;
FIG. 3 is a waveform diagram of a first embodiment of the present invention;
FIG. 4 is a waveform diagram of a second embodiment of the present invention;
fig. 5 is a waveform diagram of a third embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the attached drawing figures:
as shown in fig. 1, the SET detection circuit according to the present invention includes a lock detection module and a differential clock decision circuit.
The input end of the locking detection module is connected with clk0 and clk360 respectively, and the output end of the locking detection module is connected with lock_l0.
The differential clock judgment circuit comprises a first inverter, a transmission gate, an exclusive-OR gate, a first buffer, a first trigger and a first NAND gate, wherein the input end of the first inverter is connected with a first differential signal, the input end of the transmission gate is connected with a second differential signal, the first differential signal and the second differential signal are a pair of complementary differential signals, the output ends of the inverter and the transmission gate are connected with the input end of the exclusive-OR gate, and the output end of the exclusive-OR gate is connected with the d port of the first trigger through the first buffer; the ck port of the first trigger is connected with clk0; the rstb port of the first trigger is connected with the output end of the locking detection module; the q port of the first trigger is connected with the first input end of the first NAND gate, the second input end of the first NAND gate is connected with tie_high, and the output end of the first NAND gate is connected with lock_l1.
As shown in fig. 2, the lock detection module includes a second buffer, a third buffer, a second flip-flop, a third flip-flop, a second nand gate, a second inverter, and a third nand gate.
clk0 is divided into two paths, one path is connected with a d port of the third trigger, and the other path is connected with a ck port of the second trigger through the second buffer; clk360 is divided into two paths, one path is connected with the d port of the second trigger, and the other path is connected with the ck port of the third trigger through a third buffer; the q ports of the second trigger and the third trigger are respectively connected with two input ends of a second NAND gate; the output end of the second NAND gate is connected with the input end of the second inverter, the output end of the second inverter is connected with one of the input ends of the third NAND gate, the other input end of the third NAND gate is connected with lock_en, and the output end of the third NAND gate is connected with lock_l0.
The differential clock decision circuits are multiple groups, and differential signals complementary in pairs among the groups are staggered. In the embodiment described below, the differential clock decision circuits are in two sets, one set of complementary differential signals clk360 and clk180 and the other set of complementary differential signals clk90 and clk270.
The lock detection circuits for clk0 and clk360 remain in the circuit of the present application. After power-up, the delay phase-locked loop starts to work and gradually enters a locking state, and the output signal lock_lo of the lock_det module jumps to 0 after locking, and simultaneously resets the two first triggers dff1 and dff 2.
After locking, clk0 and clk180, clk90 and clk270 are just two pairs of fully complementary differential signals, so the signal after clk0 inversion and clk180 result from passing through the same delayed pass gates are fully identical signals, the result of which is taken as the input data of the first flip-flop dff 1; the result of clk90 inverting and clk270 passing through the same delayed pass gate is the exact same signal, the result of which is exclusive or' ed as the input data to the first flip-flop dff 2. In order to ensure that the trigger can detect and obtain the result of the error pulse, a buffer unit buf is added before the result of the exclusive OR is input into the trigger, and the function of the buffer unit buf is to ensure that the result output by the exclusive OR gate can be acquired by the trigger.
The output results of the two first flip-flops dff1 and dff2 are respectively nand-operated at tie_high, which is a stable level that is always high, corresponding to the digital signal "1".
As shown in fig. 3, a waveform diagram of a first embodiment of the present invention is shown. The lock detection function in the normal circuit still remains, and the lock_l0 output is high and the lock_l1 and lock_l2 output values are invalid before the circuit is locked; when the circuit enters a locking state at time t1, the lock_l0 output is 0, and if no single event transient appears on the voltage-controlled delay line, the output results of lock_l1 and lock_l2 are both 1. However, at time t2, a SET phenomenon is generated in the circuit, and it can be seen from the figure that, in all output clock signals of the circuit, except clk0, the following continuous three-phase clock is interfered, however, the SET effect is obviously serious, and the generated waveform distortion maintains longer, so that the waveform distortion is acquired at the rising edge of the next clk0, and the normal lock detection circuit can still meet the requirement. In this case, the detection result priority of lock_l0 is highest, and as long as lock_l0 transitions high, the SET phenomenon is generated in the circuit, and the output states of lock_l1 and lock_l2 are invalid regardless of whether lock_l1 and lock_l2 are detected.
As shown in fig. 4, which shows waveforms of the second embodiment of the present invention, the clk270 generates a duty cycle error pulse at time t1 after the circuit is locked, and since other clock signals are not disturbed, the lock detection circuit in the normal circuit cannot detect such an error at this time, so that the output of lock_l0 is always kept at a low level. However, in the proposed differential decision circuit, clk90 is taken to be the opposite, and is exclusive-ored with ck270, so that a high pulse is generated, the rising edge of clko in the next period is just encountered at time t2 after the pulse is delayed by Δt through the buffer buf, the pulse is captured by clko, so that the output of the first flip-flop is set high, and the result is then nand-operated with tie_high, so that a downward pulse appears in lock_l2, and at this time, the duty cycle error is displayed until lock_l2 is restored to the high state after one clock period.
Fig. 5 shows waveforms of the third embodiment of the present invention. After the circuit is locked, ck180 and ck360 have a one-cycle missing pulse, but the normal circuit fails to show such an error, so lock_l0 remains low all the time. However in the proposed differential decision circuit. clk180 first passes through an inverter and then performs an exclusive-or operation with clk360 to generate a period of high pulse, the pulse is captured by the rising edge of clko after being delayed by a buffer, so that the output of the flip-flop is set high, and the result is then subjected to a nand operation with tie_high, so that lock_l1 generates a downward pulse, at this time, the missing pulse error is detected, and lock_l1 is pulled down by one clock period.
The invention also discloses a chip, and the SET detection circuit is printed on the chip.
The above is only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited by this, and any modification made on the basis of the technical scheme according to the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (8)
1. The single event transient SET detection circuit is characterized by comprising a locking detection module and a differential clock judgment circuit;
the input end of the locking detection module is connected with clk0 and clk360 respectively, and the output end of the locking detection module is connected with lock_l0;
the differential clock judgment circuit comprises a first inverter, a transmission gate, an exclusive-OR gate, a first trigger and a first NAND gate, wherein the input ends of the first inverter and the transmission gate are respectively connected with two differential signals, the two differential signals are a pair of complementary differential signals, the output ends of the inverter and the transmission gate are connected with the input end of the exclusive-OR gate, and the output end of the exclusive-OR gate is connected with the d port of the first trigger; the ck port of the first trigger is connected with clk0; the rstb port of the first trigger is connected with the output end of the locking detection module; the q port of the first trigger is connected with the first input end of the first NAND gate, the second input end of the first NAND gate is connected with tie_high, tie_high is a stable level which is always high, and the output end of the first NAND gate is connected with lock_l1.
2. The single event transient SET detection circuit of claim 1, wherein the lock detection module comprises a second buffer, a third buffer, a second flip-flop, a third flip-flop, a second nand gate, a second inverter, and a third nand gate;
clk0 is divided into two paths, one path is connected with a d port of the third trigger, and the other path is connected with a ck port of the second trigger through the second buffer; clk360 is divided into two paths, one path is connected with the d port of the second trigger, and the other path is connected with the ck port of the third trigger through a third buffer; the q ports of the second trigger and the third trigger are respectively connected with two input ends of a second NAND gate; the output end of the second NAND gate is connected with the input end of the second inverter, the output end of the second inverter is connected with one of the input ends of the third NAND gate, the other input end of the third NAND gate is connected with lock_en, and the output end of the third NAND gate is connected with lock_l0.
3. The single event transient SET detection circuit of claim 1, wherein a first buffer is connected between the exclusive or gate output and the d-port of the first flip-flop.
4. The single event transient SET detection circuit of claim 1, wherein the differential clock decision circuits are multiple SETs, and wherein complementary pairs of differential signals between each SET are staggered.
5. A SET detection method based on a circuit according to any one of claims 1-4, characterized in that, before the circuit is locked, the lock_l0 output is high, the lock_l1 output state is invalid, when the circuit enters the locked state at time t1, the lock_l0 output is 0, meanwhile, no single event transient occurs on the voltage-controlled delay line, the output result of the lock_l1 is 1, and no single event transient occurs at this time; when a single event transient occurs in the circuit at time t2, the priority of the detection result of lock_l0 is the highest, and as long as lock_l0 jumps to be high, it is indicated that a SET phenomenon occurs in the circuit.
6. A SET detection method based on a circuit according to any one of claims 1-4, characterized in that when the circuit is locked, one of the complementary pairs of differential signals generates a duty cycle error pulse, the output of lock_l0 is always kept at a low potential, and when the other differential signal is inverted, the output is xored with the differential signal generating the duty cycle error pulse, a high pulse is generated at time t1, the pulse encounters the rising edge of clk0 at the next period at time t2, the pulse is captured by clk0, so that the output of the first flip-flop is SET high, the result is nand-operated with tie_high, so that a downward pulse appears in lock_l1, the duty cycle error is displayed at this time, and lock_l1 is restored to a high level state again until after one clock period.
7. A SET detection method based on a circuit according to any one of claims 1-4, characterized in that when the circuit is locked, the complementary differential signals in pairs have a missing pulse of one period, lock_l0 is always kept low, one of the complementary differential signals in pairs is first passed through an inverter and then xored with the other differential signal, a high pulse of one period is generated, which pulse is captured by the rising edge of clk0, so that the output of the first flip-flop is SET high, and as a result is nand-operated with tie_high, so that lock_l1 has a downward pulse, and this missing pulse error is detected, lock_l1 is pulled down by one clock period.
8. A chip, wherein the single event transient SET detection circuit of any one of claims 1-4 is printed on the chip.
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