CN113421886B

CN113421886B - Display panel and preparation method thereof

Info

Publication number: CN113421886B
Application number: CN202110615417.9A
Authority: CN
Inventors: 黄旭
Original assignee: TCL Huaxing Photoelectric Technology Co Ltd
Current assignee: TCL Huaxing Photoelectric Technology Co Ltd
Priority date: 2021-06-02
Filing date: 2021-06-02
Publication date: 2022-12-06
Anticipated expiration: 2041-06-02
Also published as: CN113421886A

Abstract

The application discloses a display panel and a preparation method thereof. The display panel is provided with a first display area and a second display area, the second display area is arranged around the first display area, and the first display area corresponds to a photosensitive device. The display panel comprises a substrate base plate, a transparent ultraviolet light barrier layer, a buffer layer and a metal oxide semiconductor layer which are sequentially arranged. Wherein the transparent ultraviolet blocking layer includes a first blocking member, the first blocking member being located at the first display region. The metal oxide semiconductor layer comprises a first semiconductor, and the first semiconductor is located in the first display area and corresponds to the first barrier. This application is through setting up transparent ultraviolet light barrier layer as the light shield layer, can shield the ultraviolet ray wave band that comes from substrate base plate one side, when guaranteeing the working property of first semiconductor, has improved the light transmissivity in first display area effectively.

Description

Display panel and preparation method thereof

Technical Field

The application relates to the technical field of display, in particular to a display panel and a preparation method thereof.

Background

To meet the demands of customers, a full screen gradually becomes a main trend of mobile terminal development. And an under-screen photosensitive device, such as an under-screen camera, is an important technology for realizing a full screen. The camera technology under the screen is based on a flexible Active matrix Organic Light-Emitting Diode (AMOLED) display screen, the camera is placed below the display screen, and the display screen can also ensure that the photographing effect is normal when displaying.

Metal Oxide Thin Film Transistors (OTFTs) are a new focus of the industry to gradually replace conventional amorphous Silicon (a-Si) TFTs and Low Temperature Polysilicon (LTPS) TFTs with their advantages of high mobility, simple process, low cost, and good large area uniformity. However, due to the characteristics of the energy band of the metal oxide semiconductor material, the metal oxide semiconductor material is easily affected by light, and the working performance of the metal oxide thin film transistor is further affected. To this, current display screen corresponds metal oxide semiconductor usually and sets up the metal shading layer, but the metal shading layer light transmissivity is relatively poor, and then leads to the light transmissivity of display screen to reduce, influences the sensitization device and normally works.

Disclosure of Invention

The application provides a display panel and a manufacturing method thereof, which aim to solve the technical problem that a metal shading layer arranged in the display panel in the prior art causes light transmittance reduction.

The application provides a display panel, it has first display area and second display area, the second display area surrounds first display area sets up, first display area corresponds to photosensitive device, display panel includes:

a substrate base plate;

the transparent ultraviolet light blocking layer is arranged on the substrate base plate and comprises a first blocking part, and the first blocking part is positioned in the first display area;

the buffer layer is arranged on the transparent ultraviolet light blocking layer; and

the metal oxide semiconductor layer is arranged on the buffer layer and comprises a first semiconductor, and the first semiconductor is located in the first display area and arranged corresponding to the first barrier.

Optionally, in some embodiments of the present application, the display panel further includes a gate insulating layer and a first transparent conductive layer, which are sequentially stacked;

the gate insulating layer comprises a first gate insulating sublayer, and the first gate insulating sublayer is arranged on the first semiconductor and covers a part of the first semiconductor; the first transparent conductive layer includes a first gate electrode disposed on the first gate insulating sublayer.

Optionally, in some embodiments of the present application, the display panel further includes an interlayer insulating layer and a second transparent conductive layer, the interlayer insulating layer is disposed on the first transparent conductive layer and covers the buffer layer, the metal oxide semiconductor layer and the first transparent conductive layer, and the second transparent conductive layer is disposed on the interlayer insulating layer;

the second transparent conductive layer includes a first source electrode and a first drain electrode, and the first source electrode and the first drain electrode are respectively connected to the first semiconductor.

Optionally, in some embodiments of the present application, the metal oxide semiconductor layer further includes a second semiconductor, and the second semiconductor is located in the first display region and spaced apart from the first semiconductor;

the display panel further comprises a third transparent conducting layer, the third transparent conducting layer is located between the substrate and the buffer layer, the third transparent conducting layer comprises a first transparent conducting piece, the first transparent conducting piece and the second semiconductor are arranged correspondingly, and the first transparent conducting piece and the second semiconductor form two poles of a first capacitor.

Optionally, in some embodiments of the present application, the transparent ultraviolet blocking layer further includes a second blocking member, and the second blocking member is located in the second display region; the metal oxide semiconductor layer further comprises a third semiconductor, the third semiconductor is located in the second display area, and the third semiconductor is arranged on one side, far away from the substrate, of the buffer layer and corresponds to the second blocking piece;

the display panel further comprises a shading metal layer, and the shading metal layer is arranged on one side, close to the third semiconductor, of the second blocking piece.

Optionally, in some embodiments of the present application, the third transparent conductive layer further includes a second transparent conductive piece and a third transparent conductive piece, the second transparent conductive piece is disposed on one side of the first blocking piece close to the first semiconductor, the buffer layer is attached to the top surface and the side surface of the second transparent conductive piece, and the third transparent conductive piece is disposed between the second blocking piece and the light-shielding metal layer.

Optionally, in some embodiments of the present application, the gate insulating layer further includes a second gate insulating sub-layer, the second gate insulating sub-layer is disposed on the third semiconductor and covers a part of the third semiconductor, the first transparent conductive layer further includes a first portion, the first portion is disposed on the second gate insulating sub-layer, the second transparent conductive layer further includes a second portion and a third portion, and the second portion and the third portion are respectively connected to the third semiconductor;

the display panel further comprises a first metal layer and a second metal layer, the first metal layer is arranged on the first part, and the first metal layer and the first part form a second grid;

the second metal layer includes a first metal sublayer and a second metal sublayer, the first metal sublayer is disposed on the second portion, the second metal sublayer is disposed on the third portion, the first metal sublayer and the second portion form a second source electrode, and the second metal sublayer and the third portion form a second drain electrode.

The application also provides a preparation method of the display panel, the display panel is provided with a first display area and a second display area, the second display area is arranged around the first display area, the first display area corresponds to the photosensitive device, and the preparation method of the display panel comprises the following steps:

providing a substrate base plate;

forming a transparent ultraviolet blocking layer on the substrate base plate, wherein the transparent ultraviolet blocking layer comprises a first blocking part, and the first blocking part is positioned in the first display area;

forming a buffer layer on the transparent ultraviolet blocking layer; and

and forming a metal oxide semiconductor layer on the buffer layer, wherein the metal oxide semiconductor layer comprises a first semiconductor, and the first semiconductor is positioned in the first display region and corresponds to the first barrier.

Optionally, in some embodiments of the present application, the method for manufacturing a display panel further includes:

forming a gate insulating layer on the metal oxide semiconductor layer;

sequentially forming a first transparent conductive material layer and a first metal material layer on the gate insulating layer;

and patterning the first transparent conductive material layer and the first metal material layer by adopting the same process to form a first transparent conductive layer and a first metal layer.

forming an interlayer insulating layer on the first metal layer, the interlayer insulating layer covering the buffer layer, the metal oxide semiconductor layer, the first metal layer, and the first transparent conductive layer;

sequentially forming a second transparent conductive material layer and a second metal material layer on the interlayer insulating layer;

and patterning the second transparent conductive material layer and the second metal material layer by the same process to form a second transparent conductive layer and a second metal layer.

Optionally, in some embodiments of the present application, before the step of forming the buffer layer on the transparent ultraviolet blocking layer, the method further includes:

sequentially forming a third transparent conductive material layer and a shading metal material layer on the transparent ultraviolet barrier layer;

and patterning the third transparent conductive material layer and the shading metal material layer by adopting the same process to form a third transparent conductive layer and a shading metal layer.

The application provides a display panel and a preparation method thereof. The display panel provided by the application is provided with a first display area and a second display area. The second display area is arranged around the first display area, and the first display area corresponds to the photosensitive device. A transparent ultraviolet light blocking layer is arranged on one side, close to a substrate, of a metal oxide semiconductor layer. In the first display area, the first semiconductor is shielded and protected by the first barrier member. Because the first blocking member can shield the ultraviolet light wave band from one side of the substrate base plate, the first semiconductor can be prevented from being interfered by ultraviolet light. And because the first blocking piece is transparent, the light transmittance of the first display area is effectively improved while the stability of the first semiconductor is ensured, so that the photosensitive device can normally work.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 is a schematic plan view of a display panel provided in the present application;

FIG. 2 is a schematic view of a first cross-sectional configuration taken along line AA' of FIG. 1;

FIG. 3 is a schematic view of a second cross-sectional view taken along line AA' of FIG. 1;

FIG. 4 is a schematic view of a third cross-sectional view taken along line AA' of FIG. 1;

FIG. 5 is a first schematic flow chart of a method for manufacturing a display panel provided in the present application;

FIG. 6 is a second schematic flow chart of a method for manufacturing a display panel provided herein;

fig. 7A to 7L are schematic structural diagrams sequentially obtained in steps 101 to 112 in fig. 6.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating exemplary embodiments of the invention, are given by way of illustration and explanation only, and are not intended to limit the scope of the invention. In the present application, unless otherwise specified, the use of directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the drawing figures.

The present application provides a display panel and a method of manufacturing the same, which are described in detail below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments of the present application.

Referring to fig. 1 and fig. 2, fig. 1 is a schematic plan view of a display panel provided in the present application, and fig. 2 is a schematic first cross-sectional view taken along line AA' in fig. 1.

The present application provides a display panel 100 having a first display area 100A and a second display area 100B. The second display area 100B is disposed around the first display area 100A. The first display area 100A corresponds to a photosensitive device. The display panel 100 includes a substrate 11, a transparent ultraviolet blocking layer 12, a buffer layer 13, and a metal oxide semiconductor 14. Wherein the transparent ultraviolet-blocking layer 12 is disposed on the base substrate 11. The transparent uv blocking layer 12 comprises a first barrier member 121. The first blocking member 121 is positioned in the first display area 100A. The buffer layer 13 is disposed on the transparent ultraviolet blocking layer 12. The metal oxide semiconductor layer 14 is disposed on the buffer layer 13. The metal oxide semiconductor layer 14 includes a first semiconductor 141. The first semiconductor 141 is disposed in the first display area 100A and corresponds to the first blocking member 121.

The substrate 11 may be a hard substrate such as a glass substrate, a quartz substrate, a hard resin substrate, or the like. The substrate base plate may also be a flexible substrate. The flexible substrate is made of organic materials such as polyimide, polyethylene, polypropylene, polystyrene, polyethylene terephthalate, or polyethylene naphthalate, so as to improve the flexibility of the display panel 100. The substrate 11 may have a laminated structure of a hard substrate and a flexible substrate.

The photosensitive device may be a camera lens, a fingerprint recognition unit under a screen, an ambient light sensor, and the like, and may be specifically designed according to the functional requirements of the display panel 100.

The material of the transparent ultraviolet blocking layer 12 may be a high-density thin film material such as graphene oxide. The transparent ultraviolet light blocking layer 12 can effectively block ultraviolet light from the substrate 11 side, and meanwhile, light of other wave bands can be ensured to pass through smoothly, and the light transmittance is improved.

Among them, the buffer layer 13 may be formed of an inorganic material. For example, the buffer layer 13 may be a silicon nitride layer, a silicon oxide layer, a stack of silicon nitride and silicon oxide, or the like. The buffer layer 13 isolates the transparent ultraviolet light barrier layer 12 from the metal oxide semiconductor layer 14, and plays a role of isolation protection. Meanwhile, the buffer layer 13 is used as a transition film layer between the substrate 11 and the metal oxide semiconductor layer 14, which can further block water and oxygen, and improve the stability of the display panel 100.

The metal oxide semiconductor layer 14 is formed of a metal oxide semiconductor. The metal oxide semiconductor may be Indium Gallium Zinc Oxide (IGZO), indium Gallium Zinc Tin Oxide (IGZTO), gallium indium oxide (IGO), indium Gallium Tin Oxide (IGTO), indium Zinc Tin Oxide (IZTO), or the like.

The first display area 100A and the second display area 100B are both used for displaying, which can improve the screen occupation ratio of the display panel 100 and meet the requirement of a full screen. In addition, the first display area 100A may be located at different positions of the display panel 100, such as the middle of the display panel 100, the edge of the display panel 100, and the like. The first display area 100A may have a circular shape, an oval shape, a drop shape, a bang type, etc., which is not particularly limited in this application. The embodiments of the present application are described by taking the first display area 100A as an example at the middle position of the top end of the display panel 100, but the present application is not limited thereto.

It can be understood that, in the research work on the metal oxide semiconductor material, the metal oxide semiconductor is easy to be influenced by the ultraviolet band below 300 nanometers. When the metal oxide semiconductor layer 14 is irradiated with ultraviolet light, photogenerated carriers increase, and the electrical performance and stability of the element are greatly affected. For example, the tft including the first semiconductor 141 may have undesirable phenomena such as a threshold voltage shift and an increase in leakage current. The transparent ultraviolet light blocking layer 12 is arranged on one side, close to the substrate 11, of the metal oxide semiconductor layer 14, and the first semiconductor 141 is shielded and protected by the first blocking piece 121. Since the first blocking member 121 can shield the ultraviolet wavelength band from the side of the substrate base plate 11, the first semiconductor 141 can be prevented from being interfered by the ultraviolet light. And since the first blocking member 121 is transparent, the light transmittance of the first display region 100A is effectively improved while the stability of the first semiconductor 141 is ensured, thereby ensuring that the photosensitive device located in the first display region 100A normally operates.

In this application, the display panel 100 further includes a gate insulating layer 15 and a first transparent conductive layer 16, which are sequentially stacked. The gate insulating layer 15 includes a first gate insulating sublayer 151. The first gate insulating sublayer 151 is disposed on the first semiconductor 141 and covers a portion of the first semiconductor 141. The first transparent conductive layer 16 includes a first gate electrode 161. The first gate electrode 161 is disposed on the first gate insulating sublayer 151.

The gate insulating layer 15 may be a silicon oxide layer or a silicon nitride layer, or may be a multi-film layer combination structure of silicon oxide and silicon nitride, which is not specifically limited in this application. Specifically, the gate insulating layer 15 is required to have a relatively large dielectric constant to ensure that the gate voltage has a relatively strong control capability on the thin film transistor, thereby ensuring the switching speed of the thin film transistor.

The material of the first transparent conductive layer 16 may be one or a combination of Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), tin fluoride oxide (FTO), tin antimony oxide (ATO), or tin zinc oxide (AZO). The transparent metal oxide material has good conductivity and transparency, and is small in thickness, so that the light transmittance of the first display area 100A is improved, and the display panel 100 is light and thin.

The first gate electrode 161 is formed in the first display region 100A using a transparent conductive material. Under the condition of ensuring the normal display function of the first display area 100A, the light transmittance of the first display area 100A can be further improved, and the normal operation of the photosensitive device is ensured.

In this application, the display panel 100 further includes an interlayer insulating layer 17 and a second transparent conductive layer 18. The interlayer insulating layer 17 is provided on the first transparent conductive layer 16, and covers the buffer layer 13, the metal oxide semiconductor layer 14, and the first transparent conductive layer 16. The second transparent conductive layer 18 is disposed on the interlayer insulating layer 17. The second transparent conductive layer 18 includes a first source electrode 181 and a first drain electrode 182. The first source electrode 181 and the first drain electrode 182 are connected to the first semiconductor 141, respectively.

The interlayer insulating layer 17 may be a silicon oxide layer or a silicon nitride layer, or may be a multi-film layer combination structure of silicon oxide and silicon nitride, which is not specifically limited in this embodiment of the application.

The material of the second transparent conductive layer 18 may be one or a combination of ITO, IZO, FTO, ATO, AZO. The transparent metal oxide material has good conductivity and transparency, and is small in thickness, so that the light transmittance of the first display area 100A is improved, and the display panel 100 is light and thin.

The first source electrode 181 and the first drain electrode 182 are formed in the first display region 100A using a transparent conductive material. Under the condition of ensuring the normal display function of the first display area 100A, the light transmittance of the first display area 100A can be further improved, and the normal operation of the photosensitive device is ensured.

In the present application, the metal oxide semiconductor layer 14 further includes a second semiconductor 142. The second semiconductor 142 is positioned in the first display region 100A and spaced apart from the first semiconductor 141. The display panel 100 further comprises a third transparent conductive layer 19. The third transparent conductive layer 19 is located between the substrate base plate 11 and the buffer layer 13. The third transparent conductive layer 19 includes a first transparent conductive member 191. The first transparent conductive member 191 is disposed corresponding to the second semiconductor 142. The first transparent conductive member 191 and the second semiconductor 142 constitute both poles of the first capacitor C1.

The material of the third transparent conductive layer 19 may be one or a combination of ITO, IZO, FTO, ATO, AZO. The transparent metal oxide material has good conductivity and transparency, and is small in thickness, so that the light transmittance of the first display area 100A is improved, and the display panel 100 is light and thin.

In the manufacturing process of the display panel 100, the second semiconductor 142 may be conducted to change the second semiconductor 142 from a semiconductor to a conductor, so as to improve the conductive performance of the first capacitor C1. For example, when the material of the second semiconductor 142 is IGZO, hydrogen gas may be filled to change IGZO from a semiconductor to a conductor.

In the first display region 100A, the first transparent conductive member 191 and the second semiconductor 142 are used as two poles of the first capacitor C1. Since the first transparent conductive member 191 and the second semiconductor 142 are both transparent conductive layers, there is no problem of light shielding, and thus the light transmittance of the first display region 100A is effectively improved.

In addition, the present application uses the first transparent conductive member 191 and the second semiconductor 142 as both poles of the first capacitor C1. The distance between both poles of the first capacitor C1 may be adjusted according to the thickness of the buffer layer 13. It can be understood that the smaller the distance between the two electrodes of the first capacitor C1, the larger the value of the stored capacitance per unit area, and the better the performance of the first capacitor C1. Therefore, the thickness of the buffer layer 13 is set to be close to that of the first transparent conductive member 191, so that the distance between the first transparent conductive member 191 and the second semiconductor 142 is effectively reduced, and the performance of the first capacitor C1 is improved. That is, on the premise that the structural requirements of the display panel 100 in actual production are met, the distance between the two electrodes of the first capacitor C1 can be controlled by controlling the thicknesses of the first transparent conductive member 191 and the buffer layer 13, so as to improve the working performance of the first capacitor C1.

Further, the display panel 100 of the present application may be a bottom emission display panel or a top emission display panel. When the display panel 100 of the present application is a bottom emission display panel, the first transparent conductive member 191 and the second semiconductor 142 are used as two electrodes of the first capacitor C1, so that the pixel aperture ratio of the display panel 100 can be effectively improved, and the light emitting luminance of the display panel 100 can be improved.

In this application, the transparent uv blocking layer 12 further comprises a second barrier 122. The second blocking member 122 is positioned in the second display area 100B. The metal oxide semiconductor layer 14 further includes a third semiconductor 143. The third semiconductor 143 is positioned in the second display region 100B. The third semiconductor 143 is disposed on a side of the buffer layer 13 away from the substrate base plate 11, and is disposed corresponding to the second barrier 122. The display panel 100 further includes a light-shielding metal layer 20. The light-shielding metal layer 20 is disposed on the second barrier 122 on the side close to the third semiconductor 143.

The light-shielding metal layer 20 is disposed corresponding to the third semiconductor 143. The light-shielding metal layer 20 and the second blocking member 122 constitute a stacked light-shielding structure to protect the third semiconductor 143 from light.

The material of the light-shielding metal layer 20 is a metal with good light-shielding property, and is generally molybdenum, copper, aluminum or a composite metal, which is not limited in the present application. The light-shielding metal layer 20 can effectively shield light from the substrate base plate 11 side, and prevent the light from affecting the stability of the third semiconductor 143.

It is understood that the second display area 100B is not provided with a photosensitive device. Therefore, the requirement of the second display area 100B for light transmittance is lower than that of the first display area 100A. And the display area of the second display area 100B is generally much larger than that of the first display area 100A. Therefore, the second display region 100B is provided with a larger number of the third semiconductors 143, and the stability of the third semiconductors 143 is more required for the normal display of the second display region 100B. Therefore, in the present application, the light-shielding metal layer 20 and the second blocking member 122 are disposed in the second display area 100B to form a stacked light-shielding structure, so that interference of light rays in other bands of the ultraviolet band on the third semiconductor 143 can be avoided, and stability of the display panel 100 can be improved.

Of course, in some embodiments of the present application, when the display panel 100 has a high requirement on the overall transparency, the light-shielding metal layer 20 may not be disposed in the display panel 100. Thereby simplifying the process of the display panel 100 and reducing the thickness of the display panel 100.

In this application, third transparent conductive layer 19 also includes second transparent conductive member 192 and third transparent conductive member 193. The second transparent conductive member 192 is disposed on a side of the first barrier member 121 close to the first semiconductor 141, and the buffer layer 13 is attached to a top surface and a side surface of the second transparent conductive member 192. The third transparent conductive member 193 is disposed between the second blocking member 122 and the light-shielding metal layer 20.

It is understood that, since the third transparent conductive member 193 and the light-shielding metal layer 20 are stacked, the first transparent conductive member 191, the second transparent conductive member 192, the third transparent conductive member 193 and the light-shielding metal layer 20 may be simultaneously formed by the same process when the display panel 100 of the present application is manufactured. Thereby simplifying the process.

Further, the metal oxide semiconductor layer 14 further includes a fourth semiconductor 144. The fourth semiconductor 144 is located in the second display region 100B and spaced apart from the third semiconductor 143. The third transparent conductive layer 19 further includes a fourth transparent conductive member 194. The fourth transparent conductive member 194 is disposed corresponding to the fourth semiconductor 144. The fourth semiconductor 144 and the fourth transparent conductive member 194 form two poles of a second capacitor C2.

It can be understood that the transmittance of the display panel 100 plays an important role in the overall display performance, and the higher the transmittance is, the higher the displayable brightness of the display panel 100 is, and the better the transparency is. The fourth semiconductor 144 and the fourth transparent conductive member 194 are used as two poles of the second capacitor C2 in the second display region 100B. Since the fourth semiconductor 144 and the fourth transparent conductive member 194 are both transparent conductive layers, there is no problem of shading, and the overall transparency and pixel aperture ratio of the display panel 100 can be improved.

In this application, the gate insulating layer 15 further includes a second gate insulating sublayer 152. The second gate insulating sublayer 152 is disposed on the third semiconductor 143 and covers a portion of the third semiconductor 143. The first transparent conductive layer 16 also includes a first portion 162. The first portion 162 is disposed on the second gate insulating sublayer 152. The second transparent conductive layer 18 further includes a second portion 183 and a third portion 184. The second portion 183 and the third portion 184 are connected to the third semiconductor 143, respectively.

The display panel 100 further includes a first metal layer 21 and a second metal layer 22. The first metal layer 21 is disposed on the first portion 162. The first metal layer 21 and the first portion 162 form a second gate 210.

The second metal layer 22 includes a first metal sublayer 221 and a second metal sublayer 222. The first metal sublayer 221 is disposed on the second portion 183. The second metallic sublayer 222 is disposed on the third portion 184. The first metal sub-layer 221 and the second portion 183 form the second source 231. The second metal sub-layer 222 and the third portion 184 form a second drain 232.

The material of the first metal layer 21 and the second metal layer 22 may be any one of silver, aluminum, nickel, chromium, molybdenum, copper, tungsten, or titanium, and these metals have good conductivity and low cost, so that the production cost can be reduced while the conductivity of the first metal layer 21 and the second metal layer 22 is ensured.

In the present application, the second gate 210 is formed of the first metal layer 21 and the first portion 162. The second source 231 is formed by the first metal sub-layer 221 and the second portion 183. And the second drain electrode 232 is formed by the second metal sub-layer 222 and the third portion 184. Based on the parallel connection principle of the routing, the resistances of the second gate 210, the second source 231 and the second drain 232 can be effectively reduced, so that the leakage current of the thin film transistor is reduced.

In addition, since the first transparent conductive layer 16 and the first metal layer 21 are stacked, the first gate electrode 161, the first portion 162, and the first metal layer 21 can be formed simultaneously by the same process when the display panel 100 of the present application is manufactured, thereby simplifying the process. The second transparent conductive layer 18 and the second metal layer 22 are also omitted here.

Furthermore, when the first metal layer 21 is made of copper, the first portion 162 is added between the first metal layer 21 and the second gate insulating sublayer 152 as a transition layer, so that copper atoms can be prevented from diffusing to the second gate insulating sublayer 152 or the third semiconductor 143, and copper pollution is avoided, and deep level acceptor impurities are formed in the second gate insulating sublayer 152 or the third semiconductor 143. The second metal layer 22 is not described herein.

In the present application, the display panel 100 further includes a passivation layer 24 and an electrode layer 25. A passivation layer 24 is disposed on the second metal layer 22 and covers the interlayer insulating layer 17, the first source electrode 181, the first drain electrode 182, the second source electrode 231, and the second drain electrode 232. An electrode layer 25 is disposed on the passivation layer 24. The electrode layer 25 includes a first electrode 251 and a second electrode 252. The first electrode 251 is disposed in the first display region 100A and is connected to the first drain electrode 182 through a via hole (not shown). The second electrode 252 is disposed in the second display region 100B and is connected to the second drain electrode 232 through a via hole.

The first electrode 251 and the second electrode 252 are anodes. The electrode layer 25 may be made of one or a combination of ITO, IZO, FTO, ATO, and AZO. The transparent metal oxide material has good conductivity and transparency, has a small thickness, and is beneficial to realizing the lightness and thinness of the display panel 100. In addition, the first electrode 251 and the second electrode 252 may also adopt a stacked structure of ITO/Ag/ITO, which is not particularly limited in this application.

Further, in the present application, the display panel 100 may further include, but is not limited to, a pixel defining layer, a light emitting layer, an encapsulation layer, and other devices.

The light emitting layer may include, but is not limited to, a hole injection layer, a hole transport layer, a light emitting material layer, an electron transport layer, an electron injection layer, and the like.

The encapsulation layer generally includes at least one inorganic layer and at least one organic layer, which are alternately stacked. The inorganic layer can be selected from inorganic materials such as aluminum oxide, silicon nitride, silicon oxynitride, silicon carbide, titanium oxide, zirconium oxide, zinc oxide and the like to block water and oxygen. The organic layer may be selected from organic materials such as epoxy, polyimide, polyethylene terephthalate, polycarbonate, and polyethylene to improve flexibility of the encapsulation layer 200.

The thin film transistor in the display panel 100 of the present application is a top gate thin film transistor, but the present application is not limited thereto. The thin film transistor in the application can be a top gate type thin film transistor, a bottom gate type thin film transistor, a double gate type thin film transistor, or a single gate type thin film transistor. The above-described embodiments are merely illustrative of the technical solutions of the present application, and are not to be construed as limiting the present application.

Referring to fig. 1 and fig. 3, fig. 3 is a schematic diagram of a second cross-sectional structure along line AA' in fig. 1. The difference from the display panel 100 shown in fig. 2 is that, in the present embodiment, the gate insulating layer 15 further includes a third gate insulating sub-layer 153 and a fourth gate insulating sub-layer 154. A third gate insulating sub-layer 153 is disposed on the second semiconductor 142 and covers the second semiconductor 142. The fourth gate insulating sublayer 154 is disposed on the fourth semiconductor 144 and covers the fourth semiconductor 144. The first transparent conductive layer 16 further includes a fourth portion 163 and a fifth portion 164. The fourth portion 163 is disposed on the third gate insulating sublayer 153. The fourth portion 163 and the second semiconductor 142 form two poles of a first capacitance C1. The fifth portion 164 is disposed on the fourth gate insulating sublayer 154. The fifth portion 164 and the fourth semiconductor 144 form two poles of a second capacitor C2.

In the present application, the first transparent conductive layer 16 is utilized to form one electrode of the first capacitor C1 and one electrode of the second capacitor C2, so that the process can be simplified. Meanwhile, a new film layer is not added to the display panel 100, thereby reducing the thickness of the display panel 100. In addition, the distance between the two electrodes of the first capacitor C1 and the second capacitor C2 can be controlled by adjusting the thickness of the gate insulating layer 15, so as to improve the working performance of the first capacitor C1 and the second capacitor C2.

Of course, in other embodiments of the present application, one electrode of the first capacitor C1 and one electrode of the second capacitor C2 may be formed by using the second transparent conductive layer 18. Alternatively, one electrode of the first capacitor C1 is formed by the first transparent conductive layer 16 and one electrode of the second capacitor C2 is formed by the second transparent conductive layer 18. This is not a particular limitation of the present application.

Referring to fig. 1 and fig. 4, fig. 4 is a schematic diagram of a third cross-sectional structure along line AA' in fig. 1. The difference from the display panel 100 shown in fig. 2 is that in the present embodiment, the second drain electrode 232 is also connected to the light-shielding metal layer 20 through a via hole.

It can be understood that, since the light-shielding metal layer 20 overlaps the third semiconductor 143 and the second gate 210, parasitic capacitances are formed between the light-shielding metal layer 20 and the third semiconductor 143 and between the light-shielding metal layer and the second gate 210, respectively. When the display panel 100 operates, the voltage applied to the second source 231 changes according to the voltage applied to the data signal line, so that the voltage applied to the light-shielding metal layer 20 changes, thereby affecting the electrical performance of the third semiconductor 143. The second drain electrode 232 is connected with the light-shielding metal layer 20 to form an equipotential, so that the voltage change on the light-shielding metal layer 20 can be prevented from affecting the electrical performance of the third semiconductor 143.

Referring to fig. 1 and fig. 5, fig. 5 is a first flow chart illustrating a method for manufacturing a display panel according to the present application. The display panel 100 has a first display area 100A and a second display area 100B. The second display area 100B is disposed around the first display area 100A. The first display area 100A corresponds to a photosensitive device. Specifically, the preparation method of the display panel 100 includes the following steps:

step 101, providing a substrate.

Specifically, the substrate 11 may be a hard substrate such as a glass substrate, a quartz substrate, a hard resin substrate, or the like. The substrate base plate may also be a flexible substrate. The flexible substrate is made of organic materials such as polyimide, polyethylene, polypropylene, polystyrene, polyethylene terephthalate, or polyethylene naphthalate, so as to improve the flexibility of the display panel 100. The substrate 11 may have a laminated structure of a hard substrate and a flexible substrate.

Step 102, forming a transparent ultraviolet blocking layer on the substrate base plate, wherein the transparent ultraviolet blocking layer comprises a first blocking member, and the first blocking member is positioned in the first display area.

Specifically, a graphene oxide material layer is deposited on the substrate base plate 11 by using a chemical vapor deposition method. And etching the graphene oxide material layer to form the transparent ultraviolet light barrier layer 12. The transparent ultraviolet light blocking layer 12 includes a first barrier member 121. The first blocking member 121 is positioned in the first display area 100A.

Of course, the transparent ultraviolet blocking layer 12 may be formed of other transparent materials capable of blocking ultraviolet light, which is not particularly limited in this application.

Step 103, forming a buffer layer on the transparent ultraviolet light blocking layer.

Specifically, the buffer layer 13 is formed on the transparent ultraviolet blocking layer 12 using a chemical vapor deposition method. The buffer layer 13 covers the base substrate 11 and the transparent ultraviolet blocking layer 12.

Step 104, forming a metal oxide semiconductor layer on the buffer layer, where the metal oxide semiconductor layer includes a first semiconductor, and the first semiconductor is located in the first display region and corresponds to the first blocking member.

Specifically, a metal oxide semiconductor material is sputter-deposited on the buffer layer 13 by a physical vapor deposition method to form a metal oxide semiconductor material layer. The metal oxide semiconductor material layer is subjected to an etching process to form the metal oxide semiconductor layer 14. The metal oxide semiconductor layer 14 includes a first semiconductor 141. The first semiconductor 141 is disposed in the first display area 100A and corresponds to the first blocking member 121.

Here, the material forming the metal oxide semiconductor layer 14 may be IGZO, IGZTO, IGO, IGTO, IZTO, or the like.

The preparation method of the present application forms the transparent ultraviolet light barrier layer 12 on the side of the metal oxide semiconductor layer 14 close to the substrate 11. The first semiconductor 141 is light-shielded by the first barrier 121. Since the first blocking member 121 can shield the ultraviolet wavelength band from the side of the substrate base plate 11, the first semiconductor 141 can be prevented from being interfered by the ultraviolet light. And since the first blocking member 121 is transparent, the light transmittance of the first display region 100A is effectively improved while the stability of the first semiconductor 141 is ensured, thereby ensuring that the photosensitive device located in the first display region 100A operates normally.

Referring to fig. 6 and fig. 7A to 7L, fig. 6 is a second flow chart of a method for manufacturing a display panel according to the present application. Fig. 7A-7L are schematic structural diagrams obtained in steps 201 to 212 of fig. 6. The following describes a method for manufacturing the display panel 100 of the present application in detail with reference to fig. 6 and fig. 7A to 7L.

Step 201, a substrate is provided.

Step 202, forming a transparent ultraviolet blocking layer on the substrate base plate, wherein the transparent ultraviolet blocking layer comprises a first blocking member, and the first blocking member is located in the first display area.

Specifically, a graphene oxide material layer is deposited on the substrate base plate 11 by a chemical vapor deposition method. And etching the graphene oxide material layer to form the transparent ultraviolet light barrier layer 12. The transparent uv blocking layer 12 includes a first blocking member 121 and a second blocking member 122, as shown in fig. 7A.

The first blocking member 121 is located in the first display area 100A. The second blocking member 122 is positioned in the second display area 100B.

The transparent ultraviolet blocking layer 12 may also be made of other transparent materials capable of blocking ultraviolet light, which is not specifically limited in this application.

And 203, sequentially forming a third transparent conductive material layer and a shading metal material layer on the transparent ultraviolet blocking layer.

Specifically, firstly, a third transparent conductive material is sputter-deposited on the transparent ultraviolet blocking layer 12 by using a physical vapor deposition method, so as to form a third transparent conductive material layer. Then, a light-shielding metal material layer is formed by sputtering deposition on the third transparent conductive material layer.

The third transparent conductive material layer is made of one or a combination of several of ITO, IZO, FTO, ATO and AZO. The light-shielding metal material layer is made of a metal with good light-shielding property, and is generally molybdenum, copper, aluminum or a composite metal.

And 204, patterning the third transparent conductive material layer and the light-shielding metal material layer by adopting the same process to form a third transparent conductive layer and a light-shielding metal layer.

Specifically, first, a photoresist material layer is coated on the light-shielding metal material layer. The photoresist material layer is exposed and developed using a Gray-Tone Mask (Gray-Tone Mask) or a Half-Tone Mask (Half-Tone Mask) to form a photoresist layer 31, as shown in fig. 7B.

The photoresist layer 31 includes a first photoresist layer 311, a second photoresist layer 312, a third photoresist layer 313 and a fourth photoresist layer 314. The thickness of the first photoresist layer 311 is greater than that of the second photoresist layer 312. The thicknesses of the second photoresist layer 312, the third photoresist layer 313, and the fourth photoresist layer 314 are the same.

The first photoresist layer 311 and the second photoresist layer 312 are both located in the second display area 100B. The first photoresist layer 311 is disposed corresponding to the second blocking member 122. The second photoresist layer 312 is spaced apart from the first photoresist layer 311. The third photoresist layer 313 and the fourth photoresist layer 314 are both located in the first display region 100A. The third photoresist layer 313 is disposed corresponding to the first stoppers 121. The third photoresist layer 313 and the fourth photoresist layer 314 are disposed at intervals.

Then, the third transparent conductive material layer and the light-shielding metal material layer are etched by a wet etching process using the photoresist layer 31 as a mask to form a third transparent conductive layer 19, and a portion of the light-shielding metal material layer is removed, as shown in fig. 7C.

The third transparent conductive layer 19 includes a first transparent conductive member 191, a second transparent conductive member 192, a third transparent conductive member 193, and a fourth transparent conductive member 194. The first and second transparent

conductive members

191 and 192 are positioned in the first display region 100A. The first transparent conductive member 191 is disposed corresponding to the first blocking member 121. The first transparent conductive member 191 and the second transparent conductive member 192 are spaced apart. The third transparent conductive member 193 and the fourth transparent conductive member 194 are positioned in the second display region 100B. The third transparent conductive member 193 is disposed corresponding to the second blocking member 122. The third transparent conductive member 193 and the fourth transparent conductive member 194 are spaced apart.

When the third transparent conductive material layer is made of ITO and the light-shielding metal material layer is made of copper, the third transparent conductive material layer and the light-shielding metal material layer can be etched by using Cu acid and ITO oxalic acid in sequence.

Of course, in some embodiments of the present application, other acidic solutions or alkaline solutions may be selected as the etching solution according to the properties of the etched film layer, and details thereof are not repeated herein.

Next, the photoresist layer 31 is subjected to a first ashing process to remove the second photoresist layer 312, the third photoresist layer 313 and the fourth photoresist layer 314. The first photoresist layer 311 remains partially due to its thicker thickness. Then, the remaining light-shielding metal material layer is etched by using an etching solution such as Cu acid to form a light-shielding metal layer 20, as shown in fig. 7D. The light-shielding metal layer 20 is disposed corresponding to the third transparent conductive member 193.

Finally, the photoresist layer 31 is subjected to a second ashing process to remove the first photoresist layer 311, as shown in fig. 7E.

Step 205, forming a buffer layer on the transparent ultraviolet light blocking layer.

Specifically, the buffer layer 13 is formed on the transparent ultraviolet-blocking layer 12 using a chemical vapor deposition method, as shown in fig. 7F. The buffer layer 13 covers the substrate 11, the light-shielding metal layer 20, the first transparent conductive member 191, the second transparent conductive member 192, and the fourth transparent conductive member 194.

Step 206, forming a metal oxide semiconductor layer on the buffer layer, where the metal oxide semiconductor layer includes a first semiconductor, and the first semiconductor is located in the first display region and corresponds to the first blocking member.

Specifically, a metal oxide semiconductor material is sputter-deposited on the buffer layer 13 by a physical vapor deposition method to form a metal oxide semiconductor material layer. The metal oxide semiconductor material layer is subjected to an etching process to form a metal oxide semiconductor layer 14, as shown in fig. 7G.

The metal oxide semiconductor layer 14 includes a first semiconductor 141, a second semiconductor 142, a third semiconductor 143, and a fourth semiconductor 144. The first and

second semiconductors

141 and 142 are located in the first display region 100A and spaced apart from each other. The third semiconductor 143 and the fourth semiconductor 144 are located in the second display region 100B and are spaced apart from each other. The first semiconductor 141 is disposed corresponding to the first barrier 121. The third semiconductor 143 is disposed corresponding to the second barrier 122.

The first transparent conductive member 191 and the second semiconductor 142 are correspondingly disposed to form two poles of the first capacitor C1. The fourth transparent conductive member 194 and the fourth semiconductor 144 are disposed to form two poles of the second capacitor C2.

In this case, the second semiconductor 142 and the fourth semiconductor 144 may be subjected to a conductor process to change the second semiconductor 142 and the fourth semiconductor 144 from a semiconductor to a conductor, so as to improve the conductivity of the first capacitor C1 and the second capacitor C2. For example, when the material of the second semiconductor 142 and the fourth semiconductor 144 is IGZO, hydrogen gas may be filled so that IGZO is changed from a semiconductor to a conductor.

Step 207, forming a gate insulating layer on the metal oxide semiconductor layer.

Specifically, an inorganic material is deposited on the buffer layer using a chemical vapor deposition method to form the gate insulating layer 15, as shown in fig. 7H.

Wherein the gate insulating layer 15 includes a first gate insulating sublayer 151 and a second gate insulating sublayer 152. The first gate insulating sublayer 151 covers a portion of the first semiconductor 141. The second gate insulating sublayer 152 covers a part of the third semiconductor 143.

And 208, sequentially forming a first transparent conductive material layer and a first metal material layer on the gate insulating layer.

Specifically, a first transparent conductive material and a first metal material are sequentially sputter-deposited on the buffer layer 13 by a physical vapor deposition method to form a first transparent conductive material layer and a first metal material layer.

The material of the first transparent conductive material layer may be one or a combination of ITO, IZO, FTO, ATO, AZO. The material of the first metallic material layer may be any one of silver, aluminum, nickel, chromium, molybdenum, copper, tungsten, or titanium.

Step 209, the first transparent conductive material layer and the first metal material layer are patterned by using the same process to form a first transparent conductive layer and a first metal layer.

Specifically, the first transparent conductive material layer and the first metal material layer are patterned by using a gray-tone mask process or a half-tone mask process to form the first transparent conductive layer 16 and the first metal layer 21, as shown in fig. 7I.

The first transparent conductive layer 16 includes a first gate 161 and a first portion 162. The first gate electrode 161 is positioned on the first gate insulating sublayer 151. The first portion 162 is located on the second gate insulating sublayer 152. The first metal layer 21 and the first portion 162 form the second gate 210, which can effectively reduce the resistance of the second gate 210.

The specific process of the gray-tone mask process or the half-tone mask process can refer to the content of step 104, and is not described herein again.

Step 210, forming an interlayer insulating layer on the first metal layer, wherein the interlayer insulating layer covers the buffer layer, the metal oxide semiconductor layer, the first metal layer and the first transparent conductive layer.

Specifically, an inorganic material is deposited on the first metal layer 21 using a chemical vapor deposition method to form the interlayer insulating layer 17, as shown in fig. 7J.

The interlayer insulating layer 17 covers the buffer layer 13, the metal oxide semiconductor layer 14, the first metal layer, and the first transparent conductive layer 16. Then, a via hole (not labeled) may be formed in the interlayer insulating layer 17 through an etching process.

And step 211, forming a second transparent conductive material layer and a second metal material layer on the interlayer insulating layer in sequence.

Specifically, a second transparent conductive material and a second metal material are sequentially sputter-deposited on the interlayer insulating layer 17 by a physical vapor deposition method to form a second transparent conductive material layer and a second metal material layer.

The material of the second transparent conductive material layer may be one or a combination of several of ITO, IZO, FTO, ATO, AZO. The material of the second metallic material layer may be any one of silver, aluminum, nickel, chromium, molybdenum, copper, tungsten, or titanium.

Step 212, the second transparent conductive material layer and the second metal material layer are patterned by using the same process to form a second transparent conductive layer and a second metal layer.

Specifically, the second transparent conductive material layer and the second metal material layer are patterned by using a gray-tone mask process or a half-tone mask process to form the second transparent conductive layer 18 and the second metal layer 22, as shown in fig. 7K.

The second transparent conductive layer 18 includes a first source electrode 181, a first drain electrode 182, a third portion 183, and a fourth portion 184. The first source electrode 181 and the first drain electrode 182 are connected to the first semiconductor 141 through via holes, respectively.

The second metal layer 22 includes a first metal sublayer 221 and a second metal sublayer 222. The first metal sublayer 221 is disposed on the second portion 183. The second metallic sublayer 222 is disposed on the third portion 184. The first metal sub-layer 221 and the second portion 183 form a second source 231. The second metal sub-layer 222 and the third portion 184 form a second drain 232. The second source electrode 231 and the second drain electrode 232 are connected to the third semiconductor 143, respectively. The second drain 232 may also be connected to the light-shielding metal layer 20 through the via to form an equipotential, so as to prevent a voltage variation on the light-shielding metal layer 20 from affecting an electrical performance of the third semiconductor 143.

Wherein the first metal sub-layer 221 and the second portion 183 form the second source 231. The second metal sub-layer 222 and the third portion 184 form a second drain 232. Based on the parallel connection principle of the routing, the resistances of the second source 231 and the second drain 232 can be effectively reduced, so that the leakage current of the thin film transistor is reduced.

Further, as shown in fig. 7L, a passivation layer 24 and an electrode layer 25 may be sequentially formed on the second metal layer 22. The passivation layer 24 covers the interlayer insulating layer 17, the first source electrode 181, the first drain electrode 182, the second source electrode 231, and the second drain electrode 232. The electrode layer 25 includes a first electrode 251 and a second electrode 252. The first electrode 251 is disposed in the first display region 100A and is connected to the first drain electrode 182 through a via hole. The second electrode 252 is disposed in the second display region 100B and is connected to the second drain electrode 232 through a via hole.

Further, in the present application, other devices such as a pixel definition layer, a light emitting layer, and an encapsulation layer may also be formed on the electrode layer 25, but are not limited thereto, and are not described herein again.

The preparation method of the present application forms the transparent ultraviolet blocking layer 12 on the side of the metal oxide semiconductor layer 14 close to the substrate 11, so that the first blocking member 121 shields the first semiconductor 141 from light. Since the first barrier member 121 can shield the ultraviolet light wavelength band from the substrate base plate 11 side, the first semiconductor 141 can be prevented from being interfered with ultraviolet light. And since the first blocking member 121 is transparent, the light transmittance of the first display region 100A is effectively improved while the stability of the first semiconductor 141 is ensured, thereby ensuring that the photosensitive device located in the first display region 100A operates normally.

In addition, the first transparent conductive element 191 and the second semiconductor 142 are used as two poles of the first capacitor C1, and the fourth transparent conductive element 194 and the fourth semiconductor 144 are used as two poles of the second capacitor C2, so that the pixel aperture ratio of the display panel 100 can be effectively improved, and the light emitting brightness of the display panel 100 can be improved.

Finally, the first transparent conductive layer 16 and the first metal layer 21 are formed simultaneously by the same process, the second transparent conductive layer 18 and the second metal layer 22 are formed simultaneously by the same process, and the third transparent conductive layer 19 and the light-shielding metal layer 20 are formed simultaneously by the same process, so that the process can be simplified and the production efficiency of the display panel 100 can be improved.

The display panel and the method for manufacturing the same provided by the present application are described in detail above, and the principle and the embodiment of the present application are explained in the present application by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims

1. A display panel having a first display region and a second display region, the second display region being disposed around the first display region, the first display region corresponding to a photosensitive device, the display panel comprising:

a substrate base plate;

the transparent ultraviolet blocking layer is arranged on the substrate base plate and comprises a first blocking part and a second blocking part, the first blocking part is positioned in the first display area, and the second blocking part is positioned in the second display area;

the metal oxide semiconductor layer is arranged on the buffer layer and comprises a first semiconductor, and the first semiconductor is positioned in the first display area and arranged corresponding to the first barrier;

and the shading metal layer is arranged on one side of the second barrier piece, which is far away from the substrate base plate.

2. The display panel according to claim 1, further comprising a gate insulating layer and a first transparent conductive layer which are stacked in this order;

3. The display panel according to claim 2, further comprising an interlayer insulating layer and a second transparent conductive layer, wherein the interlayer insulating layer is provided on the first transparent conductive layer and covers the buffer layer, the metal oxide semiconductor layer, and the first transparent conductive layer, and wherein the second transparent conductive layer is provided on the interlayer insulating layer;

4. The display panel according to claim 3, wherein the metal oxide semiconductor layer further comprises a second semiconductor which is located in the first display region and is provided at a distance from the first semiconductor;

5. The display panel according to claim 4, wherein the metal oxide semiconductor layer further comprises a third semiconductor in the second display region, and the third semiconductor is disposed on a side of the buffer layer away from the substrate and corresponds to the second barrier.

6. The display panel of claim 5, wherein the third transparent conductive layer further comprises a second transparent conductive member and a third transparent conductive member, the second transparent conductive member is disposed on a side of the first blocking member adjacent to the first semiconductor, and the buffer layer is attached to a top surface and a side surface of the second transparent conductive member, the third transparent conductive member is disposed between the second blocking member and the light-shielding metal layer.

7. The display panel according to claim 5, wherein the gate insulating layer further comprises a second gate insulating sublayer provided over the third semiconductor and covering a part of the third semiconductor, wherein the first transparent conductive layer further comprises a first portion provided over the second gate insulating sublayer, wherein the second transparent conductive layer further comprises a second portion and a third portion, and wherein the second portion and the third portion are connected to the third semiconductor, respectively;

8. A preparation method of a display panel is characterized in that the display panel is provided with a first display area and a second display area, the second display area is arranged around the first display area, the first display area corresponds to a photosensitive device, and the preparation method of the display panel comprises the following steps:

providing a substrate base plate;

forming a transparent ultraviolet blocking layer on the substrate, wherein the transparent ultraviolet blocking layer comprises a first blocking member and a second blocking member, the first blocking member is located in the first display area, and the second blocking member is located in the second display area;

forming a light-shielding metal material layer on one side of the second barrier, which is far away from the substrate base plate;

forming a buffer layer on the light-shielding metal material layer; and

9. The method for manufacturing a display panel according to claim 8, further comprising:

forming a gate insulating layer on the metal oxide semiconductor layer;

10. The method for manufacturing a display panel according to claim 9, further comprising:

11. The method for manufacturing a display panel according to claim 8, wherein the step of forming a buffer layer on the transparent ultraviolet light blocking layer further comprises:

sequentially forming a third transparent conductive material layer on the transparent ultraviolet light barrier layer;