CN113421834A - Three-dimensional memory and detection method - Google Patents

Three-dimensional memory and detection method Download PDF

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CN113421834A
CN113421834A CN202110689315.1A CN202110689315A CN113421834A CN 113421834 A CN113421834 A CN 113421834A CN 202110689315 A CN202110689315 A CN 202110689315A CN 113421834 A CN113421834 A CN 113421834A
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etching
channel
layer
etch
etched
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CN113421834B (en
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王庆
陈金星
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H01L22/24—Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

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Abstract

The application provides a method for detecting a three-dimensional memory, which comprises the following steps: partially removing the substrate to expose a part of the storage films of the at least two channel structures to form at least two etching regions; performing a first etching to the at least two etching regions, wherein the first etching is configured to be able to etch away a portion of the channel layer that is in contact with an etching material of the first etching; after the first etching is carried out, second etching is carried out on the at least two etching areas, wherein the second etching is configured to be capable of etching away the storage film and the filling layer and the part of the second etching contacted with the etching material; and comparing the morphology differences of the plurality of etched areas after the second etching is performed to obtain a detection result. The method realizes the detection of the tiny defects in a simpler mode, has the possibility of large-batch operation, and avoids the loss caused by neglecting the defects.

Description

Three-dimensional memory and detection method
Technical Field
The application relates to the technical field of semiconductors, in particular to a three-dimensional memory and a detection method.
Background
The 3D NAND memory is a three-dimensional nonvolatile flash memory device, and the electron storage density of the 3D NAND is greater than that of the 2D memory. The 3D NAND memory includes a stack structure, and the larger the number of layers stacked, the larger the storage capacity. But the greater the number of layers, the deeper the channel hole is formed through the stack structure, and the greater the difficulty of depositing a functional oxide-nitride-oxide (ONO) layer on the sidewalls and bottom of the channel hole. Particularly, when the ONO functional layer at the bottom of the trench hole is deposited, due to the influence of the depth and the bottom material and the limitation of the deposition equipment, the density of the ONO functional layer grown at the bottom of the trench hole is poor, so that holes, gaps and the like are generated.
In some scenarios, it is possible to ignore these tiny defects, and as the number of stacked layers increases, the tiny defects are nearly undetectable by existing inspection means. The 3D memory formed of the ONO structure having the minute defects has a quality problem, and the memory performance is deteriorated while increasing the manufacturing cost. In view of the above, overcoming the drawbacks of the prior art is an urgent problem in the art.
It should be appreciated that the statements in this background section are intended to provide some useful background for understanding the present technology and are not necessarily material to those skilled in the art having become known prior to the filing date of the present application.
Disclosure of Invention
To solve or partially solve the technical problems mentioned above or to solve or partially solve other technical problems in the prior art, the present application provides a three-dimensional memory and a detection method.
According to an aspect of the present application, there is provided a method of inspecting a three-dimensional memory, wherein the three-dimensional memory includes: the device comprises a stacked structure arranged on a substrate and at least two channel structures which penetrate through the stacked structure and extend into the substrate, wherein each channel structure comprises a storage film, a channel layer and a filling layer which are sequentially formed, and the method is characterized by comprising the following steps of: partially removing the substrate to expose a part of the storage films of the at least two channel structures to form at least two etching regions; performing a first etch to the at least two etch regions, wherein the first etch is configured to be able to etch away a portion of the channel layer that is in contact with the first etched etch material; performing a second etching on the at least two etching regions after the first etching is performed, wherein the second etching is configured to be capable of etching away the storage film and the filling layer from a portion that is in contact with an etching material of the second etching; and comparing the morphology difference of the at least two etched areas after the second etching is performed to obtain a detection result.
In one embodiment of the present application, the first etching is a vapor phase etching, and the etching selection ratio of the vapor phase etching to the channel layer, the storage film and the filling layer is in the range of 300-; the etching selection ratio range of the second etching to the channel layer, the storage film and the filling layer is 1: 300-800.
In one embodiment of the present application, the step of performing the first etching includes:
in response to the bottom surface of the channel structure having a void through the memory film and the channel layer, the vapor phase etched etch material etches away a portion of the channel layer proximate the bottom surface of the channel structure in a corresponding etch region via the void.
In one embodiment of the present application, the step of performing the second etching includes:
and etching away the part of the channel layer in response to the first etching, and etching away the storage film and the part of the filling layer close to the bottom surface of the channel structure in the etching region through the second etching.
In one embodiment of the present application, the channel layer is etched to a first length of 1nm to 100 nm.
In one embodiment of the present application, the second length of the memory film and the filling layer etched is 1nm to 100 nm.
In one embodiment of the present application, the first length is equal to the second length.
In one embodiment of the present application, the step of performing the second etching includes:
in response to the first etching not etching the channel layer, etching away a portion of the memory film near a bottom surface of the channel structure in a corresponding etching region by the second etching.
In one embodiment of the present application, the memory film is etched to have a third length of 1nm to 100 nm.
In one embodiment of the present application, the step of forming the at least two etching regions comprises:
and partially removing the substrate by one of wet etching, dry etching or gas phase etching to expose the storage films of the at least two channel structures so as to form the at least two etching regions.
In an embodiment of the application, comparing the topography difference of the at least two etched regions after performing the second etching to obtain the detection result includes:
irradiating detection optical signals to the at least two etching areas;
receiving reflected light signals obtained by reflecting the detection light signals by the at least two etching areas; and
obtaining the shape images of the at least two etching areas according to the reflected light signals;
and comparing the difference of the appearance images of at least two etching areas to obtain the detection result.
In one embodiment of the present application, the method is used to detect 3D NAND memory.
According to another aspect of the present application, there is provided a three-dimensional memory including:
a stacked structure on a substrate;
at least two channel structures penetrating the stack structure and extending into the substrate, each channel structure comprising a storage film, a channel layer and a filling layer stacked in sequence, at least one portion of the substrate being removed to expose a portion of the storage film of the at least two channel structures to form at least two etching regions, wherein a portion of the channel structure of at least one etching region near the bottom surface is completely etched away, and a portion of the storage film of at least one etching region near the bottom surface of the channel structure where the storage film is located is etched away.
According to the detection method provided by the embodiment of the application, the etching gas with high etching rate on the channel layer is selected in the first etching step, and the material with high etching rate on the storage layer and the filling layer is selected in the second etching step, so that the channel structure part with the possible holes is etched, and the channel structure without the holes is hardly etched, so that the different morphological characteristics are formed, and the detection and the identification are facilitated.
The method realizes the detection of the tiny defects in a simpler mode, has the possibility of large-batch operation, and avoids the loss caused by neglecting the defects.
Drawings
Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. In the drawings:
FIG. 1 is a flow chart of a method for testing a three-dimensional memory according to an embodiment of the present application;
fig. 2A-2E are flow charts of a testing process for testing a three-dimensional memory according to an embodiment of the present disclosure.
Detailed Description
While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements can be used without parting from the spirit and scope of the disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in various other applications.
It should be understood that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
In general, terms used herein may be understood at least in part by context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural. Similarly, terms such as "a" or "the" may also be understood to convey a singular use or to convey a plural use, depending, at least in part, on the context. Moreover, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, and may instead allow for the presence of additional factors not necessarily explicitly described, again depending at least in part on the context.
It should be readily understood that the meanings of "on", "above" and "over" in the present disclosure should be interpreted in the broadest manner, such that "on" not only means "directly on" but also includes the meaning of "on" and having intermediate features or layers therebetween, and "above" or "over" not only means "above" or "over" but also can include the meaning of "above" or "over" and having no intermediate features or layers therebetween (i.e., directly on something).
Furthermore, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layers may extend over the entire superstructure or substructure, or may have a smaller extent than the substructure or superstructure. Furthermore, the layer may be a region of a continuous structure, uniform or non-uniform, having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of levels at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically, and/or along the tapered surface. The substrate may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, above, and/or below. The layer may comprise a plurality of layers.
In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. For example, as used herein, the terms "approximately", "about" and the like are used as table-approximating terms and not as table-wise terms, and are intended to account for inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art.
It will be further understood that the terms "comprises," "comprising," "has," "having," "includes" and/or "including," when used in this specification, specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Moreover, when a statement such as "at least one of" appears after a list of listed features, the entirety of the listed features is modified rather than modifying individual elements in the list. Furthermore, when describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to refer to an example or illustration.
Unless otherwise defined, all terms (including engineering and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In addition, the embodiments and features of the embodiments in the present application may be combined with each other without conflict. In addition, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Fig. 1 illustrates a method 100 for testing a three-dimensional memory according to an embodiment of the present disclosure. As shown, a method 100 for inspecting three-dimensional memory includes:
s1: partially removing the substrate to expose a part of the storage films of the at least two channel structures to form at least two etching regions;
s2: performing a first etch to the at least two etch regions, wherein the first etch is configured to be able to etch away a portion of the channel layer that is in contact with the first etched etch material;
s3: performing a second etching on the at least two etching regions after the first etching is performed, wherein the second etching is configured to be capable of etching away the storage film and the filling layer from a portion that is in contact with an etching material of the second etching;
s4: and comparing the shape difference of the at least two etched areas after the second etching is performed to obtain a detection result.
The foregoing steps S1-S4 will be described with reference to the flow charts of the inspection process shown in fig. 2A-2D, respectively, wherein fig. 2A-2D are cross-sectional views of schematic structures of a three-dimensional memory formed after each step of the inspection process, and the cross-sectional views illustrating the structure of the device are not enlarged partially according to the general scale for convenience of illustration when describing the embodiments of the present application, and the schematic diagrams are only examples, and should not limit the scope of the present application. In addition, a three-dimensional space ruler with length, width and depth is required in actual manufacturing. It should be understood that the operations shown in the method are not exhaustive and that other operations may be performed before, after, or in between any of the operations described.
Step S1: partially removing the substrate to expose a portion of the memory film within the at least two channel structures, to form at least two etched regions.
In general, the three-dimensional memory includes a substrate 10, a stack structure 20 disposed on the substrate 10, and at least two channel structures (a channel structure 30 and a channel structure 40 shown in fig. 2A) extending through the stack structure 20 and into the substrate 10, wherein each channel structure includes a memory film 301(401), a channel layer 302(402), and a filling layer 303(403) formed in sequence as shown in fig. 2A. The "bottom surface" described herein is the surface of the channel structure 30 extending into the substrate 10 and perpendicular to the direction of extension.
In one embodiment of the present application, the substrate 10 may be sequentially composed of a base 101, a first dielectric layer 102, a substrate sacrificial layer 103, and a second dielectric layer 104, the stacked structure 20 may be formed on the second dielectric layer 104, and the channel structure 30 may extend into the first dielectric layer 102 of the substrate 10. The substrate 101 comprises single crystal silicon, silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. The first dielectric layer 102 and the second dielectric layer 104 include silicon, such as amorphous silicon, polycrystalline silicon, or single crystal silicon, and the substrate sacrificial layer 103 may be a silicon oxide layer. The first dielectric layer 102, the substrate sacrificial layer 103, and the second dielectric layer 104 may be formed by a thin film deposition process including, but not limited to, CVD, PVD, ALD, or any combination thereof.
The stacked structure 20 may include a plurality of sacrificial layers 201 and insulating layers 202 alternating in the extending direction, each sacrificial layer 201 forming a stacked pair with an adjacent insulating layer 202, the number of stacked pairs formed may be 32, 64, 96, 128, 160, 192, 224, 256 or more. Insulating materials that can be used for the insulating layer 202 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. The material of the sacrificial layer 201 is a sacrificial material that can be selectively removed with respect to the material of the insulating layer 202, and may include an insulating material, a semiconductor material, or a conductive material, and the sacrificial layer 201 may be appropriately patterned so that a conductive layer formed by subsequently replacing the sacrificial layer 201 serves as a control gate. In one example, the sacrificial layer 201 may include silicon nitride, and the insulating layer 202 may include silicon oxide.
The storage film 301 may be a composite layer including a tunneling layer 3011, a storage layer 3012 (also referred to as a "charge trapping layer"), and a blocking layer 3013. The channel layer 302 comprises silicon, such as amorphous, polycrystalline, or monocrystalline silicon, and the remaining space may be partially or completely filled with a fill layer 303 comprising a dielectric material, such as silicon oxide, and/or air gaps. The channel structure 30 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the fill layer 303, the channel layer 302, the tunneling layer 3011, the storage layer 3012, and the blocking layer 3013 of the memory film 301 are arranged in this order radially from the center of the pillar toward the outer surface. Also, at the bottom surface of the channel, the fill layer 303, the channel layer 302, the tunneling layer 3011, the storage layer 3012, and the blocking layer 3013 of the memory film 301 are arranged in this order toward the bottom surface along the direction in which the channel structure extends toward the direction close to the substrate. The tunneling layer 3011 may comprise silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 3012 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. Barrier layer 3013 may include silicon oxide, silicon oxynitride, high-k dielectric, or any combination thereof. In one example, the memory films 301 and 401 may be a composite layer including silicon oxide/silicon oxynitride/silicon oxide (ONO). It will be appreciated by those skilled in the art that the channel structures described herein may comprise any suitable number of more than two channel structures without departing from the teachings of the present invention.
As shown in fig. 2A, in order to obtain a larger storage capacity, the number of stacked pairs of the stacked structure 20 is increased, and the length of the channel hole is increased simultaneously, so that it is more difficult to perform each deposition process in the channel hole. In the process of forming the memory films 301 and 401 and the channel layers 302 and 402, a step-by-step vapor deposition is generally adopted, due to the increase of the length of the channel hole and the difference of materials of the interfaces between the memory film and the channel layers, the deposited film layers are easily uneven and have poor compactness in the vapor deposition process, and minute defects such as pores (for example, pores 70 appear in the memory film 301 and the channel layer 302) are easily formed in the memory film and the channel layer deposited on the bottom surface of the channel hole, and are difficult to be found and detected, so that the yield of the three-dimensional memory is reduced.
In one example, the stacked structure 20 may include a first stacked structure 20a, a channel structure 30a penetrating the first stacked structure 20a, and a second stacked structure 20b located on the first stacked structure 20a, and a channel structure 30b penetrating the second stacked structure 20b, an end aperture of the channel structure 30a away from the substrate 10 being larger than an end aperture of the channel structure 30b close to the substrate 10, wherein the channel structure 30a and the channel structure 30b are aligned. In order to reduce the difficulty of etching the channel, a dual stack (dual stack) process has been developed, in which two channel etches are used to reduce the difficulty of one channel etch. The deposition process of the sidewall and bottom surface of the channel hole can be performed simultaneously in the channel structures 30a and 30b, and since the calibers of the two formed channel holes at the connecting positions are not equal, the deposition difficulty of the memory film and the channel layer is increased. It will be understood by those skilled in the art that the number of the stacked structures 20 shown in fig. 2A is merely exemplary for convenience of illustration, and the specific number thereof can be set according to actual needs.
As shown in fig. 2B, in an embodiment of the present application, the method S1 for detecting a three-dimensional memory includes:
substrate 10 is partially removed to form at least two etch zones (e.g., etch zone 50 and etch zone 60). In one example, the base 101 in the substrate 10 may be removed to form an etching region, and the first dielectric layer 102 may be further removed to expose a portion of the storage films (e.g., the storage film 301 and the storage film 401) in at least two channel structures (e.g., the channel structure 30 and the channel structure 40) to form an etching region, and the base 101 and the first dielectric layer 102 may be removed at one time or may be removed in steps, wherein the removing manner includes but is not limited to one of dry etching, wet etching or gas etching, and a combination thereof. An "etch region" as referred to herein is a region that includes an area that is etched away when a subsequent etch process is performed.
Step S2: performing a first etch to the at least two etch zones, wherein the first etch is configured to be capable of And etching away the part of the channel layer contacted with the first etched etching material.
As shown in fig. 2C, a first etch is performed to at least two etch zones (e.g., etch zone 50 and etch zone 60). When the memory film and the channel layer at the bottom surface of the channel structure are poorly dense, there may be a plurality of pores (for example, pores 70 occurring in the memory film 301 and the channel layer 302) penetrating the memory film and the channel layer. The pores 70 are extremely small in size, and large liquid molecules are difficult to pass through, and wet etching tends to be difficult to handle. Therefore, the first etching adopts gas phase etching, and the gas etching has a first etching selection ratio to the channel layer, the storage film and the filling layer by selecting proper etching gas as an etching material and adjusting the type and proportion of the etching gas, the etching temperature, the etching pressure and the etching time. The etch rate ratio of the first etch selectivity ratio ranges from 300-800:1, so that the applied gas can etch away the portion of the channel layer in contact therewith, but does not etch away the memory film and the fill layer.
Specifically, when the first etching is performed to at least two etching regions (i.e., etching gas is applied to at least two etching regions), if the above-described apertures 70 are present, as shown in fig. 2C, the etching gas will diffuse into and contact with the channel layer 302 via the apertures 70, thereby etching away a portion of the channel layer 302 near the bottom surface of the channel structure 30 in the etching region 50, fig. 2D shows a partially enlarged view of the etching region 50 in fig. 2C, and as shown in fig. 2D, a portion of the channel layer 302 on both the bottom surface of the channel structure 30 and the inner wall near the bottom surface is etched away. The first length of the channel layer that is etched may be 1nm-100nm, but the memory film 301 and the filling layer 303 that are contacted by the gas-etching material are hardly etched away. In this embodiment, the applied etching gas has a high etching rate for the channel layer material polysilicon and a low etching rate for the memory film of the ONO structure, which may have an etching selectivity of, for example, 500: 1. It should be understood by those skilled in the art that the channel structure having the pore-type micro defects may include a plurality of structures, not limited to the one channel structure 30 illustrated in fig. 2C and 2D, and the one channel structure may have one or more pore-type micro defects, and the first etching operation is performed simultaneously in the etching regions of all the channel structures.
In one embodiment, the first etching may be isotropic etching or anisotropic etching, and the etching gas used includes C4F6、C4F8、CH2F2、CHF3One or more of them, illustratively, when C is adopted at the same time4F6、C4F8、CH2F2In the case of three gases, a buffer gas (e.g., rare gas such as Ar, He, etc.) may be further included to improve the diffusivity of the gas, and C4F6And C4F8All flows of are greater than the CH2F2The flow rate of (a); illustratively, when C is employed simultaneously4F6、C4F8、CHF3And a buffer gas, wherein C4F6And C4F8Are all greater than the CHF3The temperature of the first etching is between 15 and 80 ℃, the pressure is between 20 and 200mtorr, the etching time is between 20 and 80 seconds, and in a specific implementation process, the etching gas adopted by the first etching is C with the proportion of 10 in parts4F810 parts by weight of C4F65 parts by weight of CH2F2And 100 parts of Ar at a pressure of 60 mtorr.
In one embodiment, in order to etch the gas etching material along the extending direction of the trench without etching in the direction perpendicular to the extending direction as much as possible, anisotropic etching may be performed such that the momentum of the etching gas along the extending direction is much greater than the momentum perpendicular to the extending direction, thereby having excellent directionality and being capable of etching in the extending direction without affecting the memory film.
When the memory film and the channel layer of the bottom surface of the channel structure (e.g., channel structure 40) are dense and do not have a pore that penetrates through the memory film 401 and the channel layer 402, when the gas etching material is applied to the etching region 60, the gas etching material first contacts the barrier layer 4013 in the memory film 401, the gas etching hardly etches the barrier layer 4013, and the tunneling layer 4011, the storage layer 4012, and the channel layer 402 and the filling layer 403 in the memory film 401 are not in contact with the gas and thus are not etched. It should be understood by those skilled in the art that the channel structure without the pore-type micro defect may include a plurality of, not limited to, one channel structure 40 illustrated in fig. 2C.
In one example, the material of the first dielectric layer 102 in the substrate 10 is polysilicon, and the material of the channel layer is the same as the first dielectric layer 102, so the first dielectric layer 102 may be removed when the first etching is performed.
Step S3: performing a second etch to the at least two etch zones after performing the first etch, wherein the second etch is performed Etching the second etching material to etch away the storage film and the filling layer And (4) partial.
As shown in fig. 2E, after the first etching is performed, second etching is performed to at least two etching regions. By selecting proper etching gas as an etching material and adjusting the type and proportion of the etching gas, the etching temperature, the etching pressure and the etching time, the gas etching has a second etching selection ratio to the storage film, the filling layer and the channel layer, the etching rate ratio range of the second etching selection ratio is 300-800:1, and the etching of the second etching selection ratio can etch the storage film, the filling layer and the part contacted with the storage film and the filling layer but can not etch the channel layer.
When the deposited memory film and channel layer on the bottom surface of the channel are less dense with multiple pores 70 extending through the memory film and channel layer, at least a portion of the channel layer 302 may be etched away by the first etching process, as described above. At this time, when the second etching is further performed toward the etching region 50, portions of the memory film 301 and the fill layer 503 near the bottom surface of the channel structure 30 are etched away at the etching region 50 in the direction in which the channel structure 30 extends, but the channel layer is hardly etched away.
In one example, the second length of the memory film and the filling layer which are etched is 1nm-100nm, and the second length of the memory film and the filling layer which are etched can also be equal to the first length of the channel layer which is etched through the selection of the etching time.
In one example, the substrate sacrificial layer 103 may be a silicon oxide material, and the substrate sacrificial layer 103 is simultaneously removed when the second etching is performed.
In one example, the process of performing the second etching may include dry etching and wet etching, and illustratively, the dry etching gas includes one or more of C4F8, CF, CHF, CH, O. Illustratively, the wet etching may adopt a tetramethylammonium hydroxide solution (TMAH) as an etching solution, wherein the mass concentration percentage of the tetramethylammonium hydroxide is in the range of 1% to 10%, the solution temperature is 20 ℃ to 50 ℃, and the time is 30s to 150 s.
When the memory film and the channel layer deposited on the bottom surface of the channel structure (e.g., the channel structure 40) have good compactness and do not have a hole penetrating through the memory film 401 and the channel layer 402, when the second etching is performed on the etching region 60, the etching material of the second etching sequentially etches away a portion of the memory film 401 near the bottom surface of the channel structure 40 in the etching region 60 along the direction in which the channel structure 40 extends, and etches away the tunneling layer 4011, the storage layer 4012 and the blocking layer 4013 of the portion of the memory film 401. In one example, the third length of the memory film 401 is etched is 1nm to 100 nm. Since the second etch selectivity is lower than the channel layer etch selectivity, the subsequently exposed channel layer 402 will not be etched and will therefore act as a protective layer for the fill layer 403 to protect the fill layer 403 from contact etching.
Through steps S1-S3, the etching region 50 may exhibit a different morphology from the etching region 60, and the different morphology may be detected and identified through a defect detection means.
In the actual production process, because the same process is different in different stages and different in technicians operating the process, the obtained results may be different, so that at least two channel structures composing the same memory may have pore-type micro defects described herein or may not have such micro defects, and such micro defects are difficult to detect.
It should be understood that the detection steps S1-S3 provided in this embodiment may be part of the memory fabrication process and should not be construed as damage to the memory structure, and that other process steps may be performed prior to the steps, such as further etching of the etched region 60 to conform to the topography of the etched region 50 to meet the requirements of the fabrication process.
Step S4: comparing the shape difference of the at least two etched areas after the second etching is carried out to obtain a detection junction And (5) fruit.
After the steps S1-S3 are performed, the topography difference between the at least two etching areas is compared, and visual judgment can be performed, for example, whether the recessed structure formed at the bottom of the trench structure is defective or not can be performed by using an instrument to perform topography detection to obtain a topography image, and the method for detecting and obtaining the topography images of the at least two etching areas includes optical detection. In one example, optical detection may refer to the following steps:
s41: irradiating detection optical signals to at least two etching areas;
s42: receiving reflected light signals obtained by reflecting the detection light signals by the at least two etching areas;
s43: obtaining the shape images of the at least two etching areas according to the reflected light signals;
s44: and comparing the difference of the appearance images of at least two etching areas to obtain the detection result.
Because the etching area with the pore defects is etched, a concave structure is formed in the channel, namely, a hole appears, therefore, an irradiated detection optical signal is reflected by an un-etched area after entering the hole, and a reflected optical signal is reflected and absorbed for multiple times on the inner wall of the hole, so that the reflected optical signal is weaker, the channel layer and the filling layer of the etching area without the pore defects are kept intact, the reflected optical signal is stronger, and the intensity ratio of the optical signal appears between the channel layer and the filling layer, for example, a black spot and a white spot are used for comparison.
The method for detecting the three-dimensional memory, provided by the embodiment of the application, has the advantages that the detection of tiny defects is realized in a simpler mode, the possibility of large-batch operation is realized, the method can be used for detecting the 3D NAND memory, and the loss caused by neglecting the defects is avoided.
As shown in fig. 2E, the three-dimensional memory detected by the method according to this embodiment may be, for example, a 3D NAND memory, and may include: a stack structure 20 disposed on a substrate 10, and at least two channel structures (e.g., channel structure 30 and channel structure 40). The at least two channel structures extend through the stacked structure 20 and into the substrate 10, wherein each channel structure includes a memory film, a channel layer, and a filling layer, which are sequentially stacked, illustratively, as shown in fig. 2E, the memory film 301(401), the channel layer 302(402), and the filling layer 303 (403).
At least a portion of the substrate 10 is removed to expose a portion of the memory film of the at least two channel structures to form at least two etched regions (e.g., etched region 50 and etched region 60). Wherein, the portion of the channel structure 30 near the bottom surface of at least one etching region (e.g., the etching region 50) is completely etched away, i.e., the portion of the storage film 301, the channel layer 302 and the filling layer 303 of the channel structure 30 near the bottom surface are all etched away, and the portion of the storage film 401 near the bottom surface of the channel structure 40 where the at least one etching region (e.g., the etching region 60) is located is etched away, while neither the channel layer 402 nor the filling layer 403 in the etching region 60 is etched away.
It should be noted that additional steps may be provided before, during, and after the manufacturing method, and that some of the steps described herein may be replaced, deleted, performed in a different order, or performed in parallel for additional embodiments of the manufacturing method.
The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims (13)

1. A method of testing a three-dimensional memory, wherein the three-dimensional memory comprises: the device comprises a stacked structure arranged on a substrate and at least two channel structures which penetrate through the stacked structure and extend into the substrate, wherein each channel structure comprises a storage film, a channel layer and a filling layer which are sequentially formed, and the method is characterized by comprising the following steps of:
partially removing the substrate to expose a part of the storage films of the at least two channel structures to form at least two etching regions;
performing a first etch to the at least two etch regions, wherein the first etch is configured to be able to etch away a portion of the channel layer that is in contact with the first etched etch material;
performing a second etching on the at least two etching regions after the first etching is performed, wherein the second etching is configured to be capable of etching away the storage film and the filling layer from a portion that is in contact with an etching material of the second etching; and
and comparing the shape difference of the at least two etched areas after the second etching is performed to obtain a detection result.
2. The method as claimed in claim 1, wherein the first etching is a vapor phase etching, and the etching selection ratio of the vapor phase etching to the channel layer, the storage film and the filling layer is in the range of 300-800: 1; the etching selection ratio range of the second etching to the channel layer, the storage film and the filling layer is 1: 300-800.
3. The method of claim 2, wherein the step of performing the first etch comprises:
in response to the bottom surface of the channel structure having a void through the memory film and the channel layer, the vapor phase etched etch material etches away a portion of the channel layer proximate the bottom surface of the channel structure in a corresponding etch region via the void.
4. The method of claim 3, wherein the step of performing the second etch comprises:
and etching away the part of the channel layer in response to the first etching, and etching away the storage film and the part of the filling layer close to the bottom surface of the channel structure in the etching region through the second etching.
5. The method of claim 4, wherein the first length of the channel layer etched is 1nm to 100 nm.
6. The method of claim 5, wherein the second length of the memory film and the filling layer etched is 1nm-100 nm.
7. The method of claim 6, wherein the first length is equal to the second length.
8. The method of claim 2, wherein the step of performing the second etch comprises:
in response to the first etching not etching the channel layer, etching away a portion of the memory film near a bottom surface of the channel structure in a corresponding etching region by the second etching.
9. The method of claim 8, wherein the third length of the memory film etched is 1nm to 100 nm.
10. The method of claim 1, wherein the step of forming the at least two etched regions comprises:
and partially removing the substrate by one of wet etching, dry etching or gas phase etching to expose the storage films of the at least two channel structures so as to form the at least two etching regions.
11. The method of claim 1, wherein comparing the topography difference of the at least two etched regions after performing the second etch to obtain a detection result comprises:
irradiating detection optical signals to the at least two etching areas;
receiving reflected light signals obtained by reflecting the detection light signals by the at least two etching areas;
obtaining the shape images of the at least two etching areas according to the reflected light signals; and
and comparing the difference of the appearance images of the at least two etching areas to obtain the detection result.
12. The method of any of claims 1-11, for detecting a 3D NAND memory.
13. A three-dimensional memory comprising:
a stacked structure disposed on a substrate;
at least two channel structures penetrating the stacked structure and extending into the substrate, each channel structure comprising a storage film, a channel layer and a filling layer stacked in sequence, wherein at least a portion of the substrate is removed to expose a portion of the storage film of the at least two channel structures to form at least two etching regions, wherein a portion of the channel structure of at least one etching region near the bottom surface is completely etched away, and a portion of the storage film of at least one etching region near the bottom surface of the channel structure is etched away.
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